CH626480A5 - Device to output digital data corresponding to analog signals via data lines of a programmable control device - Google Patents

Description

The invention relates to a device according to the invention is provided.

the preamble of claim 1. 50 Fig. 7 shows schematically an address of the type used in the

Analog signals are already known for converting converter circuits converting the preferred embodiment data shown in FIG. 4 into corresponding digital operation, which is used in the form.

different implementation principles work, as illustrated in FIG. 8 in a simplified connection

Counting principle and the iterative principle. So far, however, there has been no diagram of how certain pulses in the converter circuits shown in FIG. 4 become known, which control the preferred embodiment of the invention, which is operated in conjunction with a programmable control device, in this embodiment, 9, which illustrates, in particular by means of a microprocessor, FIG. 9 in a pulse diagram a central unit formed with address lines, with bidirectional erase and release or write pulse, which operates the data lines shown in FIG. 8 and with control lines for the link arrangement provided as well as a corresponding delivery of a write signal, upon the occurrence of which 60 linkage arrangement in the digital data shown in FIG. 4 controls the selected data acquisition devices before the data lines appear on selected embodiment of the invention. In the following, the general control device is closer

A programmable control system explained in the. 1, 2 and 3 are used for the purpose of the present invention is particularly suitable, is otherwise described in more detail on the basis of a programmable control device A (US patent application, serial No. 6.5, which is used to control machines, Processes and other 701 858, dated 1.7.76). Systems based on input information from inputs and

The invention is based on the object of serving a path to existing states or other parameters. To show this, as in a device of the control device mentioned at the beginning, uses the module and the method

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according to the present invention. The input signals as they are schematically determined by a digital computer 22

States and parameters are clearly shown to the control device A. In the exemplary embodiment shown, the computer is connected to various external connections and locations via schematically illustrated lines 24, which are capable of connecting binary information to the direct access module 20 as a single bit. When to hold on or as a plurality of bits, that is bytes, to provide. 5 request signal from the module 20 to the central unit. These external connections can be switches, coding disks dui 10, the computer 22 or others or decoding disks, lamps, decoded analog data, external control devices can be the control of the address and binary-coded states . According to the usual practice lines, the input identification line DBINP, which contains the control device memory locations, and the processing read / write line and the data lines Do to D7 as well as Tung is carried out according to a program, which as a multiplicity 10 over other lines which in 1 are indicated by arrows of steps or commands in such a system memory. When this happens, the CPU module is stored in the rather. To store the intermediate information essential from the remaining part of the control device or data, certain memories are separated with optional ones and the computer 22 can load memories, i. H. the

Access provided. These memories can also be programmed for a control device, and the control-specific program storage can actually be used, although in all devices, as with testing and in the event of a fault, a program read-only memory searches for storage. The direct access module is used, the program information or program steps uses all the memories of system A with the desired logic. 'to load inputs and outputs in the desired states

As shown in Fig. 1, the programmable control setting, the content of the memory or the various direction A is a digital processing system which selectively reads 20 input and output circuits, the control variety of separate and different plug-in devices A, intermediate stop and drain options which are connected to the control devices A via a multitude of control lines and which are connected to others, which generally contain in a mother status all the memory positions and registers of the control plate connection system are. An exception device A, including the registers of the microprocesses, however, form remote input / output modules. 25 sors MP in the central unit module 10 to check. The direct access module for the basic modules and the control lines for these modules is for the data flow to and from the system are schematically illustrated in Fig. 1, in which a central A is used under the control of an external unit to the unit module (CPU) 10 or module C711 uses a standard computer, external tape readers, a teletype microprocessor as its central processing unit. This etc. belong.

Microprocessor is a well-known, in MOS integration technology 30 In order to transfer the control to the module 20 to executed circuit chip, the internal register, counter, time, the microprocessor MP of the module 10 is in the ger and the associated logic circuit in itself Hold state brought, which contains below known manner. The microprocessor has one to be addressed. The external programming

Number of output address connections, a number of direction, such as a computer or a tape reader, sends via the bidirectional data connections, setting devices, the 35 data lines Do to D7 data to and from the control device chip in a multitude of known states A off, and the location of the data is permitted by the address lines, and facilities controlled at the beginning of each separate Ao to Ais. The fact that the microprocessor puts the status code of the module 10 in the hold state (HOLD) on the data lines. Although a variety of microprocessors could be used with these rather than in the HALT state, the functions standard properties could be used, for the 40 of the microprocessor by a programmed signal or by the embodiment illustrated by FIGS. 1, 2 and 3 is the one programmed Requirement to be made by module 20 using an Intel 8080 microprocessor. In addition, control can be seen by the micro-view, which has sixteen address connections and eight bidirectional processors restored by means of a simple command and no data connections. The control device A can be operated without complicated programming.

concludes the various concepts related to what is useful when the microprocessor goes into a microprocessor halt state to process an input (STOP). It is not necessary to provide a trigger pulse and output information for the purpose of controlling one in order to regain control over system A through the programmed series of events of a machine, a module 10. Once the hold state (HOLD) process etc. on. When the input information is triggered, the central unit module 10 again takes over digital information, namely the control over the lines shown in FIG. 1. Both at the entrance and at the exit. For the execution of represents a suitable way to give the control device A a conversion process between analog signals and digital direct access for the programming and for the

However, signals could give converters at the interface in between and then for the release of the control of the device shown in FIG. 1 and the various control device which is separate from the module 20.

which use analog inputs and / or analog outputs. 55 The central processing unit module 10 can be detected by external states. The central processing unit module 10 is interrupted with the others in order to interrupt the program and modules in connection with the input and output information in order to be controlled by the microprocessor on a line on the lines Do to D? to process. To transmit a short rather saved subroutine. This is an explanation of the separate modules, which should be sufficient to standard interrupt property of most 8-bit micro-their intended use in conjunction with the Zen 60o processors. However, controller A contains a central unit module 10 and the overall operation of the program variety to illustrate by separate interrupt expansion-controllable control device A. duln, three of which are shown schematically as

In order to initially program the control device A, I, II, III and 30, 32, 34 are indicated. The under and test is a module 20 with direct access between the first expansion module and the downstream, which controls the expansion modules following the central unit module by over-connecting the various control lines connected to the Freiga-10 E of module 30 with a link signal 1

takes. This makes it possible to directly load the memory of the control, which in practice is to program a voltage from direction A by an external device, 5 V in the control device or in system A. The

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subsequent modules 32,34 and any additional nevertheless an easily available, relatively inexpensive microprocessor

Modules contain an input-free input at port E.

The module 40 is a programmable read-only memory module, which is a programmable read-only memory and is also referred to below as a PROM module. This connection arrangement represents a priority level system. This PROM module is used in system A to provide a system in which the interrupt input signals of the link state, which is permanently given priority by the link signals on the module 30 lines, via the interrupt input signals Ao to Ais, to the various extension modules 32 which are subsequently connected , 34 to keep those addressed. In practice, will own etc. In each of the interrupt expansion modules, generally the organization program and the various ones in the illustrated embodiment, there are 16 separate io that subroutines at the various addressed interrupt inputs, which are schematically represented as multiple memory locations within the PROM module 40, permanent number of unipolar, mass or formwork connected to earth. This memory module is illustrated for a long-term tern 30a-30x, 32a-32x and 34a-34x. or permanent storage of the program used; he

These interrupt inputs can be used by logic MOS memory chips, which are exposed to ultravio-gages, which receive information which the excess light can be erased and which, by means of separate devices, causes the module 10 to be in the interrupted state, as by a computer 22 or by a tape reading device

For the purpose of processing a selected subroutine, the direct access module 20 can be programmed. In general. Accordingly, triggering an input of the practice, the PROM module has a capacity of 4096, the microprocessor MP of the module 10, an interruption of 8-bit words. The number of words to be executed in the read-only memory module and transferred to the subroutine, the words available to be processed can be processed in accordance with. Then the controller will change to the desired capacity of device A. In the Pra execution program of the control device or the xis, due to the memory used in the module 40,

Systems A returned. By using this interrupt technology, a static, silicon-erasable, expandable circuit expansion arrangement can provide a large number of and electrically re-programmable read-only memory subroutines and can be used by dispensing 25 MOS-based chips.

an interruption request to one of the logic inputs shown schematically in a multiplication during the normal operation of the control device A is lifted by the module 40 via the lines Do to D7. The execution or organizational report submitted. The parallel transmission of binary data via this gram of system A requires the processing of a “to-line leads to the delivery of an 8-bit word, which by means of a see” command or a sequence for those data or connections 30 the link signals on the lines Ao -Au addresses link input signals and output signals below which. In Fig. 1 it is indicated that the data lines D0-D7 at

Interrupt control only if an interruption to the PROM module 40 are bidirectional. This only serves to record a request that indicates that for the purpose of loading the memory during the program, a specific connection or connections should be de-rated and tested using the direct access module and / or updated. 35 20. The memory chips of module 40 are in practice under

If an interrupt request cannot be deleted by the central normal circumstances. For this reason, the permanent unit module is not required to be connected to an extension module for supplying power to this particular module, the microprocessor goes into a loan in order to transfer the stored link or the stored state of refraction, and to hold data from the extended link signals. Of course, a particular subroutine could be selected by an address appearing on 40 a variety of different types of fixed value lines D0-D7, or rather used to program information for "canceled". Then the call input signal or system A will be saved, as shown schematically in Fig. 1 - output signal in accordance with the desired and put.

required interrupt subroutine processed. Thereafter, with particular reference to the one memory, the subroutine returns to the main memory module 50 comprising random access program (RAM). If there is no interrupt request - indicating that this memory module is available periodically, the organization program is repeatedly processed while the control device A is being used, without the interrupt subroutines being able to be. Various memories could be processed in the system. Accordingly, the subroutines will only be used with random access. The loan was called up and edited if necessary. The number of memory modules 50 with random access in this way contains a certain expansion connections of the modules 30 to 34, which can be increased to large standard parity check circuit 52, as shown in FIG. The only practical is shown. This will transfer the data to and from the storage

Limits are the amount of memory that can be extended to capacity information directed to various random access chips and that checks for parity processing in accordance with the time available to the interrupt subroutines. 55 usual practice to make a fault determination. In

By providing the interrupt expansion practice, the module uses 50 solid state memory chips, the system microprocessor or the controller with random access, with a capacity of 4096 device A in a much greater frequency under 8-bit words . In this module an external battery storage will be broken as this is used in known microprocessors of the solution to expose the information or the data to the. Accordingly, the normal microprocessor-60 different memory locations in the module 50 can be held until the refraction concept of priority evaluation and jumping the information or the data in an intended manner by means of a subroutine which, by a certain interruption, changes the operation of the control device A. The semiconductor memory technology used in FIG. 5 for many separate input signals or module 50 is one

States are used. This saves programming time leading to a static random access memory, and furthermore the use of subroutines that are in 6.5 N-MOS technology. The module 50 can be stored both for reading and storing the device A, and also for writing by the link signals to the one periodic purpose only. The versatile lines Ao-Ais addressable. This link signals speed of device A is thereby greatly expanded, while or address selects the desired address for the PROM

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Module and derives the 8-bit word in question can be processed in terms of linkage, as in one of the corresponding memory locations parallel to the data line and single-bit data processor. This makes it relatively easy to move towards D0-D7. the DBINP logic signal and the one AND, OR and inverting logic process R / W logic signal determine whether data in the module 50 is to be carried out at various inputs and outputs in order to be introduced or not or whether data from the relevant To implement linking functions that can be read with the module or not. The operation of a memory of the extended 8-bit microprocessor can be considered as a complex chers with random access in connection with a micro. In order to illustrate the use of both the byte processor or another type of digitally programmable operating mode and the bit operating mode, the control device is known; accordingly, a byte input and output module 60 and a bit-different systems can be used. 10 illustrates input and bit output module 70. In addition to the PROM module 40 and the RAM module 50, the module 60 has a series of input words, of which it is possible to provide an additional memory which comprises eight data bits each. These words are generated by ver-PROM memory and / or by various input devices designed as RAM memory, as can be done by an encoding. In practice, the parity circuit 52 is formed by a sol-disk network 62. In a corresponding manner, the outgoing circuit type is formed, which delivers a 9-bit word and which comprises 15 words from the module 60 as display signals in a display arrangement that is required to illustrate a unit 64. Accordingly, the module will generate 60 bits for an odd parity per word and will be used to test an information byte as an 8-bit word. When an 8-bit word is written into memory to be input to the various input or output locations, the parity generator checks the word and generates or outputs.

ninth bit, which is either a link signal «1» or 20 A single information bit is generated by the driver scarf as a link signal «0», so that the resultant device or the 9-bit word entered into module 70 on the single data line Do is always one odd number of «1» links or output. When a bit operation operation by states or link signals. If a word is selected from the circuit arrangement which is read from the memory according to the present invention, the parity check circuitry according to the invention is constructed or designed, then a check is carried out to determine whether this relates only to that on the Line sig- ning sig- ning word still processed an odd number of «1» link nals. Contains the link signals on the remaining signals. If the test circuit detects an even number of bidirectional data lines which are ignored and ignored by "1" link signals, the processor is ignored. To determine whether a single informa match with the usual microprocessor practice bit to the output units 80 is interrupted via the driver circuit. Other parity check circuits 30 70 may be routed or not, the system driver circuit or systems will be used so that errors in the information can be detected on the input line DBINP and the read / write mation to which one Access has been made. Line R / W occurring logic signal controlled. The programmable control device A uses supply voltage source 12 gives a DC voltage of 5 V to a standard microprocessor which has eight data connections and sixteen address connections for operating the logic arrangement in system A. This allows a 35 and a DC voltage of 12 V for the operation of 8-bit word or one byte other components determined simultaneously by the microprocessor. The 2 V and 4 V Lei can be processed. This capacity brings clear advantages from the supply voltage source 12 to be used with a view to reading different inputs and supplying voltages, through which the link-writing to different outputs is involved. The RAM memory signals are maintained when the logic processing of a single bit within 40 supply voltage is inadvertently broken under an 8-bit word, such as an improper, or moderate or broken. These two lines are controlled by re-inverting processing, but brings a lot of rechargeable batteries. Of course, there could be a difficulty. A significant part of the software variety of other supply voltage devices in over-programming is required in order to be linked with the desired supply voltage-required processing of a single bit of an 8-bit word or 45 bytes of the programmable control device A uses bytes. This requires space and one.

extensive programming. This disadvantage is even explained below. Some definitions regarding the still more serious in the control of machines and control lines are given. Referring again to a process, namely a large number of simple Fig. 1, it should be noted that a number of control lines logic functions are required there. The doubling line 50, which establishes a connection between the central unit of a conventional relay link diagram unit module 10 and the various other modules or conductor diagrams, represents the largest part of the processing which the programmable control device A represents Link processing of a single bit information or include. These control lines are not shown. Around this single-bit information in an 8-bit half of the central unit module. In many cases, corresponding to the data capacity to be processed, there is a considerable connection connection of the micropro increase in the program storage space and the control processor of the type Intel 8080 or are those of the complexity. If, for example, a single input microprocessor is logically associated, as is to be compared with a single output signal in the case of the illustrated embodiment of the present invention, the use of an 8-bit input information constitutes a disadvantageous programmable control device. If memory addresses or binary coded 6o applies. Taking into account the general operation of data being transmitted or processed, the large number of programmable control devices A is the basic number of radio data lines. In order to avoid the disadvantages associated with the version of each of the lines shown in FIG. 1, which are caused by the tert. In the course of the description, the inverted increase in the capacity of the microprocessor, in the form of a line designation, indicates that a lower, to overcome, is provided by the control system - logic state - whether pulse state or permanent state - a circuit arrangement by which one exists or there is a "yes" status. Thus, in the case of one-bit information, which indicates the read / write line labeled R / W on a selected example, shows the data line “like the data line Do, in a similar way that a read state with a link signal“ 1 ” in front

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and that there is a write status with a logic signal of the type Intel 8080. This internal flip-flop can be due to Freinai «0». This convention will be used in most of the give and lock interrupt instructions or back microprocessors and similar digitally controlled numerical controls and will cause the equipment used to lock the receptacle or processing equipment to be used. Acceptance of subsequent interrupt requests on the synchronization signal line SYNC, a negative 5 occurs by the microprocessor when the relevant flip-ver or a low potential 1 OO-ns link flop is in the reset state. The internal flip-flop, which is the start pulse of the respective 8080 machine on the chip itself, is automatically displayed back cycle. This pulse is not programmable; it is set to further interruptions at time Ti one is used to lock the status word in the respective command fetch cycle Mi and then when a subcomponent or the respective module is locked, the break has been accepted by the microprocessor. Status information from the central unit for the line. The HLDA line is the hold or hold acknowledgment application required during an entire machine cycle. The link signal occurring on this line, which may contain or include one or more words. changes to a logic signal «0» when a hold

The external clock pulse 02 is generated by the internal central request (HOLD REQUEST) from the unit clock generator; it can be used if microprocessor MP is confirmed. These hold requests are synchronized to the operation of the various modules is supplied by the hold request line, as specified in this. This pulse or signal can also be illustrated as FIG. 1. The hold state (HOLD) of an accurate time base signal can be used. In practice microprocessor transfers the address and data connections, this clock signal has either a frequency of 2.0 MHz of the microprocessor in a high impedance state, or 3.0 MHz. 20 these connections control over the address lines

The address lines Ao-Ais run with the exception of the Ao-Ais and enable via the data lines D0-D7. This address line Ais actually all of the link signal lines can be accessed by the access module 20 during the "0". The logic signal on these lines is used in the programming and during the testing to control the rest of the address for all the memories. The signal on the HLDA line begins at the timer and input / output modules for the control system A 25 point T3 for a read-memory or input cycle. To provide for one. These address lines are from the module memory write or output cycle or for a corresponding general output lines. If the direct operation is carried out a shift on the HLDA handle module 20 is used, the lines concerned are lines with the clock period following the Ts clock pe- however bidirectional lines that riod the input of addresses. In practice it is known to allow the signal on the module 10. With Ao the address bit is never HLDA line, which denotes a third value on the address lines after a rising edge. Impulse 01 impulse on the one with a high impedance

The direction of transmission of the address lines and data lines appears on the DBINP line, after which fol data lines D0-D7 are designated. This control line will appear on the edge of an 02 pulse. The signal used on the hold to key or forward data on the data bus lines from the request line (HOLD REQUEST) to the respective module of device A indicates that there is an external request for the zenith. traleinheit and in particular the microprocessor chip in the

The R / W line is brought into the device A to bring it into the hold state (HOLD). In this hold state, data on the data bus lines to the addressed external devices can key or route the address and data line memory locations. Consider with control, as soon as the central processing unit module has exploited the similarity between the DBINP line and the 40 of these lines with regard to the processing of the existing R / W line, these lines are generally completed or the existing machine cycle. The sam used. The DBINP line is used for this, the central unit module uses the DBINP gene to determine the direction of the data flow and the line and the R / W line are also abandoned. With

Pushing or routing data onto the data bus lines. In other words, this means that these lines read / write line R / W are used to be determined by the direct access module 20 for programming or whether these data are written or read. Can be controlled by other external control functions. Provision of these two control lines, the data are to be summarized. It should be noted that if a hold of the data bus line or lines D0-D7 is required during the (HOLD) state, the microprocessor in the Hal-pulse-wise reading and writing on the R / W line status changes (HOLD) and an output signal via bil. 50 HLDA line releases to just this hold state (HOLD)

The waiting line will be displayed in connection with the ready line. This condition occurs after a certain

shaft management used. These lines are available with the men or a certain completion during an

Microprocessor connected, which times an additional machine cycle. The relevant stop state will be used for reading slower memory or input at the next machine cycle and will enable the output / output points. If the module 10 does not record a link state of the microprocessor chip during an address-related internal link with regard to the register-added output.

stood or a link signal "1" on the standby line. A corresponding arrangement is recorded for the reset option, then the microprocessor enters the wait relation. A reset request is received from the supply stand, as long as the standby line supplies a voltage 12 or leads from the direct access module 20 low link signal. In this state, 60 is generated on the reset request line, the wait line generates a logic signal “0”. As soon as this request is received by module 10 and the standby input signal is received, the microprocessor is reset. In this microprocessor from the wait state, and on the state becomes the content of the internal program counter of the wait line, a link signal «1» occurs. This 8080 microprocessor erased. After the reset feature occurs, it is clearly shown in FIG. 2 that the program relates to operation 65 impulses at one point with the word 0 in of the Intel 8080 microprocessor. start the memory. The internal INTE and HLDA flip

The INTE output indicates the contents of an internal flop of the microprocessor chip are also reset interrupt enable FIIP flops in the microprocessor. The internal accumulator, the stack pointer and the regi

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are not deleted. If in the reset state the PWR state - which is triggered by a logic signal zero, there is a shift or change that is formed when the supply voltage supply has been switched-off logic signal on the reset line (RESET) - the interruption with the highest priority whereby the various flip-flops and other links are. In the presence of this condition, the program will be deferred within System A 5 depending on other interrupt conditions to the subroutine. This serves to put the control device system A into operation «supply voltage switched off», to put it into operation. which is at a selected location in memory

The bidirectional data bus lines or lines Do is located; in practice, this memory location is through the octal to D? provide an 8-bit data connection to the central value 010. The next interrupt input module 10 ago. In addition, these lines with the 10 nal is in practice the signal BOOT, which is an interrupt-different memory modules and input / output module request INT2 for a memory location in the memory. The modules that only perform bit functions are more likely to be generated. In this way there is a minimal program - in contrast to byte functions - use single-program for the initial operation of device A to borrow one of these lines, at least for data output. If available. This introductory minimal program is housed under the preferred embodiment, it is the 15 octal address 020 of the memory; it is called by line Do. During the first clock cycle of each machine, various devices are “called”, which in FIG. 1 shows the cycle of the microprocessor in the central unit module, which is indicated by a table as a pushbutton switch or pushbutton status word via the data line or the bus line D0-D7 are. The interrupt request INT3 stores the module. This status word is an 8-bit word, which defines the counter-locking and parity status, which describes in the corresponding machine cycle. With this status word 20 mung is worked with the known practice in order to maintain the continuity of the line Do in the preferred embodiment to maintain the nuance of the different modules. The least significant bit. The present invention relates to interrupt request INT4, which is a microprocessor of the type which uses eight data-true clock interrupt requests through which the probits. However, a different number of datagrams for the bits designated by the octal address 040 can be transferred into the memory without deviating from the purpose of the present invention. This will be used in When using an 8-data bit microprocessor with regard to the interrupt functions of the system A cessors, however, the status word can have eight bits, which will be explained in detail later. The interrupt or from the microprocessor corresponding to the command or interrupt request INT5 has been generated a transmission sub-instruction which has been obtained from the interrupt in the preferred embodiment of the invention. 30 As a result of this interruption, a memory cell with the

In the microprocessors now available, octal designation 050 exists in the memory. This is an interruption property, as briefly described above, which enables a connection from external devices. An interruption property or possibility as from the direct access module 20. The interruption of the microprocessor allows its present INT7, which has the lowest priority, to save the micro setting or position in a program, to 35 processors in the interrupt state, to jump from external to a called subroutine, edit the subroutine facilities such as coding disks or coding wheels and then read back to the correct position in the props, switches and visual display devices which jump back to the program that had previously been processed. or to write in these external institutions. In order to carry out this function, the microprocessor still has the interrupt INT6, which has an input INT in connection, and the module 10 has various io with the modules 30, 32 and 35, the interrupt request connections INT0-INT7. To extend the link signal occurring to the INT connection at the extent of the possibility of interruption in the device A. The microprocessor is acknowledged from the IIV6 output in the interrupted state. At this time of the recording and processing of an interrupt request time, the connection INTE (INTE line) is fed, the request INT6. This signal line remains in the low state in order to avoid subsequent interruptions until the sufficient link level, while the interruption-selected subroutine defers the INTE connection at the time in question a request from one of the modules 30 to 34 Has. An interruption CPU unit 10 transmits. The call command becomes a syn-higher priority can transmit the operation of the control device with a 02 clock signal; it provides the take before a lower priority interrupt subroutine in memory, under which a call is terminated during a priority level, provided the INTE port is accommodated by the 50 selected additional interrupt, has been reset. So far it has been supplied by the added modules, of which only three are shown in processing systems using a microprocessor.

There has been the possibility of merely receiving a final description of the basic lines or a relatively limited number of interrupt request command paths that are required to and from the central processing unit module 10. This limitation has run through the 55, should suffice for a full understanding of the

Limitations of the various codes have been defined, invention in which the use of an improved module is intended for the subroutine selection or "subroutine prompt" which is used in connection with a micro-

tion »were available. System A uses a system which contains eight interrupt inputs via programmable controllers using a processor, via which the device of the type shown schematically in FIG. 1 is used

Microprocessor is brought into the interrupt state. 6o will. These output and input lines correspond to those in FIG. 1 are the interrupt connections INT0-INT3 and the nomenclature illustrated by the Intel Corporation for their INT5-INT7. In practice, these interrupt microprocessor chips, labeled 8080, are used to map external ports, ports, or parameters in the preferred embodiment of the present meter, which may be input or output signals. A corresponding nomenclature will be used. The priority of the interrupt requests is also in other commercially available microprocessors in the reverse order of the numbering, using the chips that have the properties that have the lowest number as the highest priority. The background information and the lowest priority in the area in question has the highest number. Accordingly, known explanatory information has been given. The

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Properties of this microprocessor chip are known per se. The module 10 could generate an I-STROBE or I-Tastim pulse on a control line, specifically for the software delivery of a touch pulse for the various inputs and outputs, if this should be necessary.

The status word for the microprocessor is now considered in more detail. In the microprocessor as used in module 10, as with most microprocessors, a status word occurs at the data connections as the first word of the respective machine cycle. This status word indicates the operation to be performed by the microprocessor during the current machine cycle. Although a variety of status codes and status states could be provided, the diagram of FIG. 2 illustrates the ten status words used in the Intel 8080 microprocessor. The data connections carry coding as indicated in the vertical columns for each of the different types of machine cycles during the introductory part of the respective cycle. The binary status code at connections D0-D7 is locked in a status interlock circuit with the initial synchronization pulse on the SYNC line.

If the machine cycle is given by a command fetch, then the code word occurring on the data lines D0-D7, which is held or locked in the status interlock circuit, is given with 01000101. The one occurring at each of the data connections during the introductory part of the cycle Binary code indicates a status as specified in the "Status information" column. According to the terminology used in the Intel 8080 microprocessor, the link signal of the data bus line Do represents the interrupt acknowledgment signal (INTA). This link signal indicates whether an interrupt request has been confirmed or acknowledged; it can be used to push a restart command on the data bus lines if the DBIN or DBINP line is active or effective. The link signal occurring on line Di during the introductory part of the machine cycle indicates whether a write function is present or not. This status is denoted by W; the status in question is identified by a link signal 0 if data are written into the memory or into an output point in the machine cycle. If a link signal 1 occurs on the command line Di and is held or locked in the status locking circuit, then reading is from a memory or from an input point. A link signal 1 appearing on line D2 during the command read portion of the cycle indicates that address bus lines Ao-Ais hold the backstack address from the stack pointer of the microprocessor. This status, which is denoted by STACK or by batch, is only effective during a batch read machine cycle or during a batch write machine cycle.

If a link signal 1 occurs on the data line D3 during the initial microcycle of a machine cycle, this indicates that a STOP has been confirmed. As can be seen from Fig. 2, this occurs during the stop acknowledge machine cycle or during a machine cycle, in the meantime an interruption acknowledgment occurs during the stop. Otherwise, during the introductory microcycle, which is denoted by Ti in FIG. 3, this data bus line Dj will carry a logic signal 0. During an output function, the link signal on line D4 is given by a link signal 1. This link signal occurs when the machine cycle is in an output write cycle. A link signal 1 occurring on data line D4 indicates that the address bus lines are the address of an output device contain or lead and that the data bus line finally contains or carries the output data during the cycle if the line R / W carries a logic signal 0. The logic signal occurring on the data line Ds represents a signal which indicates that the microprocessor in the fetch or fetch cycle for the first byte of a command. Accordingly, a link signal 1 appearing on line Ds during the introductory part of the machine cycle indicates that a command is available from memory or other location. This represents the status Mi represents how it ver in Fig. 2 The status INP is received on the data line Ds. A link signal 1 occurring on this line during the status part of a machine cycle indicates that the address bus lines carry or contain the address of an input device and that the input data should be passed to the data bus lines when the DBIN output of the microprocessor is active. This output naturally corresponds to the DBINP line of the central processing unit module 10. The logic signal MEMR occurs on the data bus line D7. A link signal 1 occurring on this bus line during the status information part of the cycle indicates that the data bus lines are used for a memory read operation.

During the status part of any cycle, the logic signal occurring on the data lines D0-D7 represents the codes indicated in FIG. 2. This logic signal results from a function specific to the Intel 8080 microprocessor. The encoding in question is given here only for the purpose of easier understanding of the preferred embodiment of the present invention.

Let us now consider the basic instruction cycle for the central processing unit module. The microprocessor used in the preferred embodiment of the present invention has a basic instruction cycle as illustrated in FIG. 3. The microprocessor is timed by the input pulses 01.02. The first-mentioned input pulse defines the introductory part of a microcycle; this part of the cycle is designated Ti-Ts. The micro cycle Tw is used for the purpose of designating a wait state, which was discussed above in connection with the interaction between the read link arrangement and the wait link arrangement. If a memory is not available, the microprocessor goes into a wait state, as is characterized by the occurrence of a link signal 1 on the wait line. This means that a link signal 0 occurs on the line WAIT. When the memory is then ready, a logic signal 0 occurs again on the wait line and the microprocessor continues in the microcycle Ts. There is a synchronization pulse labeled SYNC for each machine cycle. This synchronization pulse essentially corresponds to the internal synchronization pulse of the microprocessor of the Intel 8080 type. The pulse is somewhat shaped. The pulses shown in FIG. 3 are those pulses which are introduced into and removed from the module 10. However, these are basically the pulses from the microprocessor itself. During each of the microcycles, the function specified in the lower part of FIG. 3 takes place. Sometimes three microcycles are used. In other cases, many microcycles are required for a particular instruction. If, for example, the Intel 8080 microprocessor has memory access, up to 18 microcycles can be used in normal operation. During the micro cycle Ti of a machine cycle, the link signal on lines D0-D7 is read. The address on the Ao-Ais lines (to

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the address connections of the microprocessor MP) is supplied either by the internal program counter or by another register within the microprocessor.

This address information is inserted into the program counter or into the program register during a previous 5 machine cycle. The DBINP line corresponds to the internal DBIN line. This line determines whether or not data is to be delivered to the data lines D0-D7 in a subsequent part or microcycle of the machine cycle. During the initial part, data 10 on the microprocessor data ports indicates the type of cycle to be processed during the machine cycle, which may require several microcycles. The link signal appearing on the lines shown in Fig. 3 changes according to the type of instruction to be processed, in accordance with the conventional microprocessing practice. These linkage states are used in describing the preferred embodiment of the present invention. 20th

Referring to FIG. 1, it should be noted that system A includes an analog-to-digital converter module or A / D circuit 100, as best shown in FIGS. 6A, 6B and 6C. In a certain respect, this circuit comprises conventional concepts with regard to the conversion of an analog input voltage into digital output data or digital output data. According to the preferred embodiment of the invention, the digital data signal achieved or implemented in multiplex operation is routed via the data lines D0-D7 of system A in a manner to be described. An analog signal to be converted is supplied via lines 110, 112. A converter signal ADC is provided on line 114 to cause the converter circuit 100 to begin operating at the end of this pulse. After the conversion of the analog signals into the 35 digital data has been completed by the circuit 100, a logic signal 1 occurs on the reset line 116. Accordingly, an analog signal is passed to circuit 100 along with a conversion signal on line 114. A termination 40 link signal 1 is then generated on the reset line 116. The multiplex module 120 is present in system A, as shown in FIG. 1. Various modules of these modules could be used to conduct a large number of analog input signals to the circuit 100 in multiplex mode. In the embodiment shown, the module 120 is indicated as an input module I, which will be discussed in more detail in connection with FIG. 4. This module is illustrated schematically in FIG. 6A with analog input modules 122 and 124. Of course, several modules could be used to increase the possibilities of analog input. These modules are always the same modules, each comprising eight separate analog input circuits or input circuits TC0-TC7. Of course, any analog signal could be applied to one of the input circuits 55 TC0-TC7 without changing the operation of the input module 120. The input lines or input circuits TC0-TC7 route analog state signals to module 120. These status signals can be formed by a temperature signal, a speed signal, an acceleration signal, a position signal or by any other signal which is inherently an analog signal. Referring to FIG. 6A, it should be noted that the remaining input modules 122, 124 are connected in parallel on lines 110, 112 to feed selected analog signals to conversion circuit 100 by selectively closing switches 126, 128 of a module. As indicated in Fig. 4, only the input circuits at TCO and

TC7 shown in detail for clarity. In practice, however, eight separate inputs or input circuits TC0-TC7 are provided for each analog input module.

Returning to FIG. 6A, it should be noted that in operation, the various analog input circuits or inputs TC0-TC7 of the analog input modules 120, 122 and 124 with the various analog data to be read and converted into digital data for use in system A Signals are applied. One of the modules 120, 122 and 124 is addressed and made effective by a suitable address of the type shown in FIG. 7. This provides an ADC conversion signal on line 114 that extends from the enabled modules 120, 122 or 124 to the analog-digital circuit 100. The input module 120 reads and decodes the logic signal occurring from the data lines D0-D3. This decoded information causes the selection of one of the analog inputs TC0-TC7 and leads to the delivery of the selected signal via the analog signal lines 110, 112. After completion of the implementation, a link signal 1 occurs on the reset line 116, which is connected to all modules 120, 122 and 124. The occurrence of this link signal leads to the resetting of all modules for the subsequent selection and operation. In this way, multiple input modules can be multiplexed to the converter circuit 100 for the purpose of generating digital data corresponding to a selected input analog state from the addressed analog input modules.

Referring now to FIG. 4, the preferred embodiment of analog input modules 120, 122 and 124 is schematically illustrated in only two analog input circuits TC0-TC7. In practice, a larger number of input modules can be used, and in practice each module contains eight separate TC0-TC7 analog input circuits. For the purpose of describing the operation of module 120, the two input circuits TCO and TC7 are shown; the addition of additional input circuits parallel to the relevant input circuits should therefore be evident.

Module 120 will be explained in connection with a cycle for selecting and delivering an analog signal to conversion circuit 100. This description of the operation of module 120, in conjunction with the components used in the preferred embodiment, will clearly illustrate the inventive concepts of the present invention. An address is illustrated in FIG. 7 as it is used to select a predetermined module and the data lines via which one of the circuits or input circuits TC0-TC7 is selected. The address lines A0-A15 are used to select the chassis in which the modules 120, 122, 124 are housed and the particular module during an input / output command from the system A shown in FIG. 1. The address of the module is determined by its position in or on the chassis, by using the hard-wired digital data that are provided at the various chassis locations. This represents an input / output, i. H. represents an input / output address which is to be distinguished from a memory address which is used to store data from lines D0-D7. The address lines As-Aio, A12, A13 relate to the type of data processing operation that is not included in module 120. Data from system A is released over data lines D0-D7 when a write cycle is complete the write pulse on the write line R / W is activated. A module decoding or addressing circuit 130 is provided on the input side of the module 120. The address on lines A4-A7 and An, Am, Ais leads to

626 480 10

A logic 0 signal occurs on CE line 132, conventional 8-bit addressable latch decoder when the chassis in which the 210 is connected is to be activated. This decoder is cleared during

Module 120 is housed. The logic signal occurring on the address lines of the occurrence of an erase pulse on line 206 at Ao-As is to be generated with all output connections 0-7 zeros. The wired link signal in the mother card at the signaling point of the module 120 which occurs on the data line Ds is compared in order to a comparison signal controls the decoder 210. A signal occurring at the port E is to be sent to the address circuit 130. Under the logic signal 0 prevents the occurrence of a selection

Assuming that the addressing is correct, a link logic signal occurs at any port 0-7. The execution signal 1 on the output line 134 from the address connection E of the locking decoder 210 is used for the locking circuit 130. The module 120 is activated by this link signal 10 or to hold a link signal 1 on one. A write logic element of the output or output connections 0-7, specifically in over-140, which is a NAND logic element, is in agreement with the binary logic signal on-with a first input 142 via an inverter 144 on the fork lines Do, Di and D2, which are connected to the input connections DBINP line. The second input 146 of the a, b and c of the locking decoder 120 are connected. Link 140 is connected via an inverter 148 to the Lei-15. It is assumed that the link signal is connected to the device R / W. A line Ds appearing on this line in logic signal 0 is. When on-line pulse generates a write signal for module 120. Under which 150 a write pulse with a duration of approximately 500 ns occurs, assuming that module 120 has been addressed and that lock decoder 210 is locked to the system's central processing unit A to decode an instruction to link signal on lines D0-D2. The DBINP line has received a write operation 20 in response to the output command 20, however, the erase connection CL leads to an overflow or to an override of the locking connection E during the open n. Finally, the write line R / W again a 100 ns erase pulse occurs on line 206. This

Write signal, d. H. A logic signal “0” for the concept input is illustrated in FIGS. 8 and 9. If, accordingly, the inverter 148. At this point in time, all inputs lead to an address, as is illustrated in FIG. 7, and link lines 140 of the link 140 occur when the central unit generates a write signal, the control signal becomes 1. Accordingly, the Output 150 of this locking decoder 210 is initially deleted. During this link in the link state 0, which is the same write signal, a link signal 1 is indicated on a write operation. The write pulse, as illustrated in the output ports 0-7 of decoder 210, Fig. 3, is generally of a length or latch. The selected connection is one of 500 ns. Accordingly, a write pulse formed by a 30 l-out-8 decoding of the link signal to the line link signal 0 is determined on line 150 with a gene D0-D2. This locking a connector

Generated duration of 500 ns. An inverter 152 connects the line to actuate or to take effect of one of the devices 150 with the line 154 at the clock connection 2A of a circuit TC0-TC7. In the embodiment monostable device 160 shown. This device has a shape, only the input circuits TCO and TC7, which are known to cause a time delay of 2.3 ms, as can be seen from the example 35. Accordingly, only the connections 0 and 7 voltage circuits are fixed. A positive voltage is shown at the output of decoder 210. The selection line jump on line 154 causes the occurrence of a positive 220 is connected to the output connection 0, and the Leiven pulse on the Q connection of the line 162 of the monitor 222 is connected to the output connection 7. The stable device 160. This will cause a logic inverter 224,226 to inert the pulse signal occurring on lines 220 or 222 with a duration of 2.3 ms to the logic signal occurring at one input of the 40 in order to supply opposite NAND gate 164. To generate the output of this combination signal on lines 230 and 232, the connecting element is connected to ADC line 114. As far as these last-mentioned lines, of which the one previously described, no selection signal occurs on line 170. According to the preferred embodiment, eight lines are used. Accordingly, the output signal of the logic element at the input of a selection NAND element 240 is a logic signal 1, which has not been switched over. That is on the data line Dì during a module shop in order to trigger or actuate the circuit 100. Training occurring link signal controls the

The link overall operation of the lock decoder 210 is also via the write line 150. When the controller 180 is controlled. A at this input of the link line Since a link signal 0 leads, line D3, link 180 leads, which is a NAND link, which is the data line of system A, leads to link signal 0 that occurs to emit a connection 50 of the locking decoder 210, a logic link signal 1 on the output line or output signal 1. The logic element 210 is thereby released, device 182. This logic signal 1 becomes a logic signal 1 at one of its outputs by the inverter to spei-184 inverted and leads to the output of a link signal. In the course of this explanation of the preferred embodiment on line 186, which is associated with the negative clock terminal 1A embodiment of module 120, it is assumed that the decoder is connected to a monostable device 190. This mono- 55 210 by means of a link signal 1 at the connection E releases stable device giving a negative pulse with a duration.

of 100 ns at the output connected to line 192 if none of the circuits at the output of the latch connector Q are off. Thus, if a write signal on line decoder 210 is to be disabled in module 120, 150 is present, then on line 192, the link signal on lines Ds is fed to a NAND gate 200 to a negative 100 ns pulse , 60 logic signal 0 made to a logic signal 0 which has a reset input. Generate the system reset on the selected output of decoder 210. Cable leads a connection to all output connections of the locking device during the operation of system A.

Linking signal 1. Accordingly, a link signal 0 that occurs on line 192 coders 210 leads to link signal 0 that occurs, the output of a link generating a link signal 1 on all input pulse 1 with a duration of 100 ns from output 202 65 in the direction of the selection. Link 240 and a link 100. The inverter 204 inverts the link signal 0 on a selection line 170. This link link signal and supplies a link pulse 0 link signal 0 is also during the erase cycle of the to the erase line 206 connected to the erase terminal CL one. Decoders 210 generated. If one of the output ports

11 626480

0-7 during a write command by the decoded circuit TC0-TC7 in the closed state, the link signal of the lines D0-D2 has been selected, the relay circuits 320, 322 of the network 302 feed the state of the selection line 170 passes to a line selected relay circuit instead of the ineffective gamma link signal 1. This link signal compares the selected relay circuit. Inverters 324, 326 linkage with the link signal on line 162 to FIG. 5 invert the generation of a negative pulse on lines 320 and 322 on ADC line 114. Link signal. Accordingly, the conversion circuit 100 finally causes the switching circuit 100 to select locking decoders 210, a switching analog signal between the lines 110, 112 into a logic signal 0 at the output of one of the inverters 324, 326. Converting the digital output code into a next logic signal 0 leads to the activation of the manner to be described in more detail. 10 th relay circuits 320,322 and causes the closing of the

Via the selection line 170, an inverter 250 output or output switch CR10a, CR10b or the output is controlled, through which a logic signal 0 on the line gear or output switch CR17a, CR17b. The capacitor 252 is then generated when a selection made by the decoder ren 340 of the circuits TCO, TC7 is made by the 210. This logic signal 0 maintains the occurrence of the thermocouple or other voltages determined by converters of a logic signal 1 on line 182, which are also controlled by circuits TCO, TC7, when the write pulse on line 150 finally charges. If one of the analog states is selected, will disappear during the machining cycle. Accordingly, the input switch is opened by one of the relay circuits becoming ineffective or de-energized during a single write command. In a corresponding device 190 in a manner controlled by line 186, the output switches of the selected switching negative connection 1A are not clocked again. 20 device closed by a corresponding relay circuit

When the link state on line 170 is energized during relay circuits 320, 322.

Due to the occurrence of a write address in a selection die on the capacitor 340 of the input circuit TCO

Link state 1 passes over, this link-stored voltage is selectively released to lines 342, 344 or the link signal 1 when the switches CR10a, CRIOb of the two transistor switches 126, 128 in the circuit 260.25 are closed. The output lines 342, 344 are connected in parallel with the Lei-1. Accordingly, the switches 126, 128 of the module 120 lines 350, 352 are connected, which close the input lines of the, whereby the selected analog state from the signal generation circuit SC of the module 120 represents the module 120 to the input of the conversion circuit 100 The output switch CR17a, CR17b is used to switch on the Kon. In order to obtain an analog signal for the voltage 360 stored on the lines 110, 112 for the uses 360 of the input circuit TC7, relay controls are provided on the lines 350, 352 on the signal generation circuit networks 300, 302. The network 300 controls the device SC connected. The remaining six circuits are for circuit input switches CROa, CROb, CR7a and CR7b. The selection by the decoder 210 also connected to the lines network 302 controls the output or output switches 350, 352 connected.

CR10a, CR10b, CR17a and CR17b. Transmission of Analog The signal generating circuit may have any switching data on lines 110, 112 of a selected circuit form to provide an analog signal with a fixed direction of circuits TR0, TC7 by the operation of the voltage on circuit 100 during of comparison to relay control networks. Generate at the shown execution. In practice, the fixed analog signal by an approximate form, only two input circuits are shown. Constant current signal generated, which is proportional to the voltage stored on one of the con-. Each of these circuits 300,302 contains only two relay capacitors 340,360. control circuits. In practice, however, eight separate relay circuits are used. In the illustrated embodiment, the signal-generated input circuits are used, and each of the network circuit SC has a differential amplifier 400, which contains eight separate relay circuits. Outputs a constant output signal on line 401, which, with regard to network 300, should be noted that this network portion, which is used in proportion to the input voltage of capacitor 340 or the like, is a selected set of capacitor 360. Via this output line, the input switches CROa, CROb, CR7a and CR7b are controlled in the input voltage of a transistor Q2, which can be opened with a gearshift circuit TCO, TC7. The relay circuit 310 current control circuit 402 and with a voltage limiter-opens the supply to the relay-controlled switch supply circuit 404 in such a way that a proportional

CR0a, CR0b in the input circuit TCO. The relay circuit 1 current is generated on the output line 406. This 312 opens the contacts CR7a upon appropriate supply, current is proportional to the analog input voltage. CR7b. If a specific analog input circuit TCO, 50 is selected for the conversion of an input voltage into a precisely TC7 by the locking decoder 210, controlled constant output current occurs, many lines can accordingly use a logic signal 0 on the input side. This concept is based on the pre-one of the inverters 314,316. As a result, a linkage invention is used so that the resistance or the signal 0 occurs at the output of the relevant inverter and at the single impedance on the output side of the module 120 and on the aisle of one of the circuits 310 or 312. 55 Input side of the turnover circuit 100 in connection with the

Circuits 310, 312 are connected to the + 12 V line 318 connection resistor, a negligible effect. In the selected circuit TCO or TC7 will have on the signal which the module 120 switches from which accordingly a logic signal 1 receives one of the relay module or the circuit 100. The in Fig. 4 by circuits 310,312. Since the switches of the relay circuit dash-dot lines framed power generation circuit SC gen by a logic signal 0 or by the absence of 60, the selection state indicated on the various components at the inverters 314, 316 has closed parameters or component values. These values are kept open by opening the input switches, which are controlled by the relay circuit, which is inherently ineffective for the illustration. In the rear of a system, with the aid of which a constant current is produced, which is used in practice and is shown in FIG. 4, which is proportional to a relay circuit indicated on lines 350, 352, it should be noted that the input voltage is 65. Of course, any one relay circuit of the network 300 could ineffectively render a number of current signal generating circuits therefor. The remaining relay circuits remain used for purpose. As schematically illustrated in FIG. 6A, the input voltage of the unselected provides the input voltage on lines 350,352

626 480 12

controlled by the differential amplifier 400 and by a current control - the output of a logic signal 1 via the line 452 arrangement 402 in order to effect a selected constant current flow for a purpose to be described in more detail below via the switches 126, 128 of the selected input. After that, the voltage in the integrator supply analog module 120 increases. The closing of the off at a speed determined by the voltage at the output switch CRI 0a. CRI 0b and CRI 7a, CRI 7b which has an out resistance 440 determined. After a fixed period of time, the switching of the circuits TCO, TC7 is reset by a counter provided at the time Tj, the monostable device 410 is delayed by a duration of 1.5 ms and the sawtooth voltage controls the state of charge in this way. This ensures that the input switch - that the voltage discharge (of the capacitor) from the point ter or input switch are opened before the output M takes place at a lower reference level at the time Ts. Switch CR10a, CRI 0b or CRI 7a, CRI 7b through the supply io This discharge takes place at a fixed speed, which one of the circuits 320, 322 are closed. A variety is controlled by a constant reference voltage. These arrangements could cause the voltage to use the threshold time to trigger the deceleration fixed speed. In the embodiment shown, value voltage is reached at time T ». The distance between the one monostable device 410 due to a time jump T2 and Tt which is characteristic of the line 186 is characteristic of the line 186 of the magnitude of the voltage present at the resistor 440. Output of inverter 184 controlled or made effective. By operating a counter controlled with a fixed frequency. As soon as a write signal occurs, a link appears during the period between the times T2 and test signal 0 at the Q connection of the monostable device. The counter becomes one of the voltage at the resistor 440 device 410 As a result, the base voltage of the transistor Q1 will reach a proportional counter position or a proportional reduction, as a result of which the output of the + 12 V supply voltage will not count for the number of pulses. After reaching the time to the line 328 on the output side of the circuits 320, point T », a link signal 0 322 occurs on the line 452 is prevented. After the time delay of the connection, the purpose of which will be described in more detail below, the start pulse 1 at the Q connection, the full voltage will be. One input of the +12 V is delivered to line 328 via line 452. This allows the trip gate 454 to be controlled. The other input of this solution or actuation of the circuits 320, 322, whereby the 25 AND gate is connected via a line 458 to a fixed frequency output switch of the selected analog input circuit oscillator or clock generator 456. As soon as the time or Analog input circuit CR0-CR7 is closed when point T2 is reached, the AND gate 454 thus becomes effective. Circuits 310, 312 are connected directly via line 318 to line 455 counts with a fixed frequency at the +12 V supply voltage supply. to create. Between the time T4 and the time Ts. Accordingly, the circuits 310, 312 in operation 30, a link signal 1 occurs on the line 460. This is set once a selection made by decoder 210 A / D control logic circuit 470 has been accepted. Regarding the operation of the circuits, to a certain extent the direction of the voltage in the Inte-320,322 there is a time delay during a generation circuit 450 after a fixed period (T3) to an unknown period in order to change or shift the connection of the circuit SC. A sawtooth control pulse is avoided with a measurement voltage source that could generate excessive currents or changeable voltages from the circuit also referred to as the control circuit. 470 is generated to determine the end of the ADC pulse as the operation of the embodiment shown in FIG. 4 is illustrated in FIG. 5. Accordingly, the control form of the invention is further illustrated in FIG. 5, in which the link logic circuit 470 shows pulse sequences determined by the positive rise. As can be seen, the ADC comparison signal is controlled. Via the control line, the illustrated input switch CR7 opens as soon as 40 472 the control logic circuit controls the integra- a selection signal from a monostable device 190 tion circuit 450 in a temporal relationship, as has been generated in FIG. After one is illustrated by the monostable device Fig. 5. In accordance with a time delay controlled in device 410, the practice which is customary in certain respects is then closed via the clock line wired CR 17. The monostable device 190 455 counts the counter 480, which resets the erase pulse during a period of time that has 482. During the occurrence of the ADC pulse is less than the operating time of logic element 140. One counter 480 is reset; the relevant monostable device 160 controls the end of the comparison and cannot count. Thereafter, the signals from the oscilla signal ADC, which originates the comparison function in the gate 456 circuit and is triggered or executed via the link 454 100, are executed. transmitted pulses via the line 455 to the counter 480 In the following, reference is made to FIGS. 6A, 6B and 6C. The counter is a 12-bit counter with outputs in which a type of an analog-to-digital conversion circuit connects DB0-DB11. The counter 480 may be an overflow indicator. In this circuit - for the construction of which device 484 has to be put together so that when the count is exceeded, three drawing figures are to be put together - as it is read from the connections DB0-DB11, an analog input resistor 440 is provided, which can do one a link signal 1 occurs on this line. Supplies voltage which is proportional to the link signal 1 supplied to the activated module 120, 122 or 124 via the switch 126, 55. This link signal causes a link signal 1 to be supplied to the activated line 120, 122 or 124, and that is constant current. An integration circuit 450 with that pending upon completion of the integration, which is signaled by the link integration voltage diagram shown in FIG. 5 on line 460. One of the most characteristic features takes up the constant voltage present at the resistor 440 before completion of the integration or in the event of an overflow and controls the sawtooth logic signal 1 which causes the integration circuit to appear for a fixed period of time Linking signal 1 on the range with «Reset». With regard to the reset line 116 shown in FIG. 5 between the times.

Ti and T2 illustrated integration voltage is to be noted in the following in particular on the output side of the that this integration voltage for charging the circuit shown in Fig. 6A. The linking

The integration circuit (capacitor) with a fixed speed signal at the connections DB0-DB11 shows the frequency leading the percentage or percentage of the maximum counting range that is set within the integration circuit 450. At time T2, the integration voltage has been recorded by the converter circuit 100. For the curve, the capacitor threshold voltage is reached, at a range of 100%, at least ten connections are required

13 626480

such. The eleventh port may indicate and provide an overflow, and then a conversion termination signal for delivery of a link signal on line 484 control use in the terminating module 120. Another line labeled DBn can provide one.

Show sub-area that would exist if there was no return to module 120, note that voltage is present at resistor 440. This can be the case in FIG. 5 when a termination or termination pulse is received if an open input circuit is connected to an analog -One of the reset line 116 towards the inverter 550 there is a linkage circuit CR0-CR7. If so, training pulse 0 is generated on line 551. This linkage-a detection pulse 0 appearing on a line such as line DB11 is a selection ending pulse which the linkage signal is read. Of course, monostable device 410 can be actuated or triggered. Accordingly, other arrangements may be provided to indicate the status io upon deselection by appropriate circuit 100 on certain output ports, such as the control of the reset line voltage on line ports DB0-DB11. It is only reduced to 328. As a result, the activated one circuit is required to provide a suitable digital code to disable the circuits 320, 322. Furthermore, in order to indicate the magnitude of the switches CR10a, CR10b or the voltage switches present on the resistor 440. 15 CR17a, CR17b open immediately. The one ending the selection

The number of output pulses on the line 551 used by the circuit 100 also controls a monostable connections DB0-DB11 exceeds the available data line circuit 552 which biases the lines D0-D7 in the device A in the manner indicated. For this reason is designed to generate a 1.5 ms pulse corresponding to the pulse output multiplexer circuit 500 as shown in FIG. 6C, which is provided at the output of the monostable 410, for all digital data of the 20 is generated. This pulse occurs at the Q port; it is to be used for connections DB0-DB11. One formed on the line by a logic pulse 0. As soon as this 116 occurring link signal 1, which indicates that the pulse disappears, i. H. after 1.5 ms, at which the conversion has been completed, the locking plus connection 1b of the monostable circuit 190 activates a clock setting line 502, as a result of which the data on the control connections. This in turn will lock a 100 ns output pulse DB0-DB11 in multiplexer 500. 25 generated on line 192 to lock the addressable-After that, the multiplexer 500 will be locked. tion decoder 120 by a occurring on line 206, the multiplexer circuit is to be cleared via a line 510 logic clearing pulse 0. Accordingly, that which is controlled by a relay circuit of the relay switching addressing on the input side of a module selection 310,312, which is made ineffective by the mother card on the mother card side, is controlled by the 12 V supply voltage via the line circuit or a module selector 512. This activated 30 318. As a result, the input relay switch module selector corresponds to the selection circuit 130 according to CR0a, CR0b or the input relay switch CR7a, CR7b Fig. 4. The address appearing on the lines Ao-Ais is closed, depending on which of these is fed to an address decoder 516 which the data on the switch has been opened during an input selection operation on lines A0-A3 to the control module selection circuit. Accordingly, no voltage is passed to the line-512. The state or signals of these address lines 35, 350, 352 of module 120 are output. In addition, lines are or are compared with the lines 230, 232, lines 230, 232 which are now on the lines 1, 2, 4 and 8, a link signal 1. hard-wired code signals occurring. This causes a logic signal 0 to appear on the selection line

In addition, the decoded information is up from the 170. The switches 126, 128 are open. The link address line Ao-Ais forth over the line 520 to the link 164 is deactivated or blocked, and the allocation of the multiplexer 500 is routed, namely an 8-bit information link 180 is by a link on the line 252 occurrence of selected connections DB0-DB11 selectable link signal 1 to a certain extent unlocked for the len. This data is output via the bidirectional data line recording of a subsequent write pulse on the line D0-D7. Using a second address, device 150 is selected. After the selection has been canceled, anyone can then select the data from the other connections DB0-DB11 from modules 120, 122 and 124 for the input of another. In practice, the 45 analog states are selected with the first address by the module in question and to the connections DB0-DB7 for data delivery via the bidirectional conversion circuit 100. Nalen data lines D0-D7 are selected. Thereafter, by means of only one conversion circuit for all modules, a second address is used to be the next group of output lines. Although three modules are selected for entering anagen DB8-DB11. Accordingly, in a series of log information, in the embodiment shown, all data have been used by the conversion circuit 50 in two steps, in practice the signals from 16 can be multiplexed decoded via the bidirectional data line modules, specifically by the information

D0-D7 are delivered. By providing two information address lines A0-A3.

mationbytes from the multiplexer circuit 500 can be. The module together with the conversion circuit 100 is one

Full range of information data for use in hardwired, self-sustaining components for Ver-dem System A can be provided. This exploitation can take 55 turns in facility A. After a selection has been made to replace heating elements, one has been requested, module 120 and circuit 100 change speed or change other functions, perform their functions and then wait . The decoded information obtained by measuring the voltage across the resistor 440 remains on the locked lines DB0-DB11. 6A, 6B and 6C, the switching purposes of reading in subsequent or following arrangements illustrate the general 60 cycles until an unlocking by operation and the circuit element structure of a conversion - a new write cycle address on an input module Circuit 100 that may be used by module 120 along with the occurrence of a circuit selection code as illustrated in FIG. 4 could, of course, appear on lines D0-D3.

Modifications to this conversion circuit and its multiplexing are carried out for the purpose of pretensioning the monostable set-up drive, as long as the conversion system anat 160, 110 and 552 is a constant supply voltage log data in the form of a current, this data with 5 V output Supply voltage circuit 560 provided, converts a conversion pulse into a digital form, which relates to a logic signal 1 or a voltage of +5 V of the data after conversion to output connections, the control line 562. In the illustrated embodiment

626 480 14

For example, the control voltage of +5 V will be used for the linked-selected analog signal, on data lines of a test, and the supply voltage of +12 V will be provided for the programmable controller, in the operation of the relay control circuits 310,312,320 and 322 a central unit is used, the output address line

used. a selected number of bidirectional inputs /

As described in the course of the description of the preferred embodiment 5 output data lines, a device for generating the form, various modifications can be made in the circuitry used for a write signal on a write line and device arrangement, which data in response to the write signal from the to the various parameters or sizes and data lines into selected address memory locations

Cause conditions that prescribe when the module 120 is in operation. The system comprises a conversion circuit, which is constructed in accordance with the present invention and which converts the analog input signal into a digital data signal. which occurs at output data connections, and

According to the illustrated embodiment of the present invention - with the acquisition of a conversion signal and the same time the invention - the system uses automatic data acquisition of an analog signal. In addition, setup connections are provided between the analog-digital conversion circuits, which then generate a termination signal, and the analog input circuits via lines ADC and 15 when the conversion is complete. In addition, “resets” are provided in order to reduce the number of programmed commands, at least two input analog signal modules, which are required to provide a digital representation on the connections DB0 of the analogue one of each device for receiving at least two input signals - Includes analog states. In addition, facilities pre-DB11 can be obtained. hen a selected state of the analog states in

The system also uses an automatic 20 to convert an analog signal. In addition, selection device data connections are provided between the analog-digital conversion circuits, which select one of the states upon generation of the device and the analog input reset circuit in order to select the write signal. In addition, the analog input selected for each of the non-selected ones is provided, which control one of the input modules or automatically return the state, independently. In addition, signal guidance devices are provided, gig of programmed commands. This increases the frequency at which a module is activated or actuated, in which an access selected analog signal to a conversion can lead to the conversion circuit, while a desired conversion can be obtained by locking devices the selection accuracy is maintained. directions locked until the final signal is generated

In conclusion it should be stated that. Is through. Finally, control devices are provided which the present invention provides an apparatus for permitting 30 actuating devices of only one of the input modules by means of which digital data, which are characteristic, can be actuated for a specific point in time.

Claims (5)

626 480 2 PATENT CLAIMS kind of a particularly simple yet secure implementation 1. Device for outputting analog signals corresponding to digital data from a number of analog signal input devices via data lines of a programmable analog signal in digital data, which can become a central unit with an address line. tion, with bidirectionally operated data lines (D0-D7) 5 The above-mentioned object is achieved according to the invention with and with control lines for emitting a write signal device of the type mentioned, upon its occurrence on the data lines by the in the characterizing part of the Claim 1 occurring digital data on selected addressed data listed features. receiving devices are characterized, characterized in that the invention has the advantage that relative to the central unit (10) a separate analog-digital-10 simple way a safe implementation of a number of conversion module (100) is connected, which one analog input signal supplied to it by analog signal input devices is made into a digital data signal for the log signals in digital data. In this case, delivery to the data lines can be implemented only after the reception of a special conversion signal (ADC) output by the analog signal input modules and which only converts log signals into digital data according to the multiplex principle upon completion of an analog-digital conversion are set, for which a particularly easily obtained conversion of a further analog signal into a digital data loan programmable control device, namely a final signal enabling a micro signal, and which can be used with a processor, the analog-digital conversion module (100) produces a number von Ana- Further expedient refinements of the present log signal input modules (120, 122, 124) are connected, which result for the invention from the dependent claims, the delivery of analog signals to be converted into digital data. Digital conversion module (100) by delivery, for example, near r explained. corresponding addresses from the central unit (10). Fig. 1 shows schematically in a circuit diagram a program are given. controllable control device that uses a microprocessor as a central 2. Device according to claim 1, characterized in that tral unit is used, to which the present invention in particular that the analog signal input modules (120, 122, 124) can be used with the special one, with a type of analog-digital conversion module (100 ) is selectively actuated, in which the preferred embodiment of the conceivable switch arrangement (126, 128) is connected. lying invention in the programmable control device 3. Device according to claim 1 or 2, characterized thereby is included. 2 shows that the conversion signal (ADC) from the occurrence of FIG. 2 shows a status diagram for one in FIG. 1 the respective analog signal input module (120, 122, 124) 30 shown system using the standard microprocessor is derived from the indicative address. Type 8080 from Intel. 4. Device according to one of claims 1 to 3, characterized in that Fig. 3 illustrates in a standard pulse diagram that a represent the respective analog signal - on different lines one for use in the current signal before an analog-digital conversion in a speaking voltage signal considered in the system shown in FIG. 1 is implemented. 35 microprocessors of the type Intel 8080 5. Device according to one of claims 1 to 4, characterized tion signals. characterized in that each analog signal input module (120, Fig. 4 illustrates in a circuit diagram the 122, 124) considers an addressable interlocking decoder (210), which is a preferred embodiment of the present invention, which, based on the output from the central unit (10), generates a selected analog output signal. Write signal provides link signals, the analog signal 40 Fig. 5 illustrates in a pulse and voltage slide output devices (TCO, TC7) set after the program certain pulses and voltages, such as those in the locking decoder previously one of the concerned 4, the preferred embodiment shown in the invention is supplied with the delete signal derived from the invention. occur or are used, as well as some voltages, the circuits shown in Figs. 6A, 6B and 6C occur. 6A, 6B and 6C overall illustrate an analog-to-digital conversion circuitry suitable for use in the preferred embodiment of FIG. 4