DE2738835C2 - Monitoring of digital signals - Google Patents

Description

Clock monitoring circuit 5 is provided, to which the clock signal Γ is fed and which emits an alarm signal A 2 in the event of a clock failure. Both alarm signals A 1 and A 2 are fed to a gate 6 which combines the two alarm signals and outputs them to an evaluation circuit 7. The evaluation circuit 7 delays the alarm signals so that the alarm is only given to the outside if the alarm signals have a certain minimum duration. This is necessary in particular because the alarm signal A 1 can occur intermittently. This prior art arrangement described is used in particular in receiving parts of PCM multiplex devices. In this case, a clock center for the function of the multiplex device without is required anyway. In applications in which only a time-division multiplex signal is to be monitored without a clock center being available or required for further clock signals, the arrangement according to the prior art is too complex.

The object of the invention is therefore to provide a simple and reliable method for monitoring of digital time division multiplex signals of the type mentioned and corresponding arrangements for To find implementation of this method, which are also as universally applicable as possible and without get along outer frame clock generation, so for different synchronic words and different Frame duration.

The object is achieved according to the invention in that the frequency-dependent power distribution of the pulse signal for the presence of discrete power components (spectral lines) at those frequencies is monitored, which is one or more times the frame frequency of the digital time division multiplexed signal correspond.

The invention is based on the knowledge that a sufficiently precise monitoring criterion from

the spectral lines occurring at the frequencies / 0.2 / 0.3 / 0 ..., where / 0 = _{T0 is} the frame frequency, are obtained in the pulse signal E the pulse signal E certain pulses that occur with the frame period TO , in addition, pulses can occur at the points in the frame at which the frame password is simulated.

The particular advantages of the arrangement are that there is no frame clock signal to be supplied from the outside is required and that an adaptation to other time division multiplex systems is easily possible

An arrangement for implementation that is particularly inexpensive due to the saving of the clock center of the method according to the invention results from the fact that a first shift register is provided, whose number of steps is at least equal to the number of bits of the synchronous word to be evaluated and whose Step outputs are each separately connected to the inputs of a second detection circuit that the signal input of the second shift register with a connection for the digital to be monitored Time division multiplex signal and the clock input of this shift register with a source for the bit clock of the to monitoring time division multiplexed signals are connected that the output of the second detection circuit with the input of a first monitoring circuit is connected to the occurrence of discrete Power components in the frequency-dependent power distribution of the pulse signal in the simple or multiple frame frequency and its output signal is in the absence of the discrete power components changes accordingly. The particular advantage of this arrangement according to the invention is its lightness Construction using commercially available integrated modules.

Further expedient refinements of the invention are detailed in claims 4 and 5 described.

The invention is to be explained in more detail below with reference to the drawing. It shows

F i g. 1 a monitoring arrangement according to the π Staude of technology,

F i g. 2 a monitoring arrangement according to the invention,

3 shows the spectrum of the pulse signal E as a function of the frequency,

4 shows a first variant of the monitoring circuit 28 and

F i g. 5 shows a second variant of the monitoring circuit 28.

The F i g. 1 shows an arrangement according to the state of the art, which has already been explained in detail in the introduction it was stated that further explanations are not given at this point.

F i g. 2, like that in FIG. 1, an n-place shift register 21 with an input for the digital time-division multiplex signal D and a further input for the transmitted bit clock T. The outputs of the π stages of the shift register 21 are the η inputs of the second detection circuit 22 connected to each J5 when the n-digit frame identifier is times in the shift register 21, a pulse signal e to the monitoring circuit 28 outputs Instructs the monitored frame alignment error occurs, then is supported by the monitoring circuit 20, an alarm signal a to an output side connected assembly 27 submitted for alarm evaluation. The arrangement 27 for alarm evaluation has a built-in delay device which corresponds to at least ten times the frame period TO . This prevents bit errors that occur briefly in the frame password from leading to an alarm.

The F i g. 3 shows the spectrum of the pulse signal E, that is, its power distribution as a function of the frequency, from FIG. 3 it can be seen that in the 1

Frequencies / 0, 2/0, 3/0 ... with / 0 ■ = - = .- = , so-called

Spectral lines, that is, discrete power components, occur which have arisen from the frame password periodically contained in the digital signal D. In addition, the spectrum contains a continuous portion which is assigned to the irregularly occurring pulses in the pulse signal E and which can contain irregular additional needle pulses at the points in the frame at which the frame password is simulated

ω becomes.

The first variant of the monitoring circuit according to the invention shown in FIG. 4 contains a phase-locked loop PLL connected to the input 1 of the monitoring circuit, to the output of which one input of a synchronous demodulator Sd is connected, the other input of which is connected to input 1 of the monitoring circuit and its output Output via a low-pass filter with a first

Decision maker E 1 is connected. The pulse signal E is fed to the phase-locked loop and the synchronous demodulator via the input t. The phase-locked loop is synchronized to the frequency η ■ / Ό (n = 1, 2, 3, ...) and emits a sinusoidal oscillation of the same frequency, which is fed to the synchronous demodulator as a carrier oscillation. By superimposing the set spectral lines with the carrier oscillation, the synchronous demodulator generates, in a known manner, a direct voltage on which alternating voltage components are superimposed. These AC voltage components are suppressed by the connected low-pass filter, so that the downstream first decision maker Ei receives a DC voltage. The first decision maker E 1 issues an alarm as soon as the DC voltage at its input falls below a preset threshold value

The F i g. 5 shows a further variant of the monitoring circuit 28 in which a frequency-selective element is a connected to the input 1 of the monitoring circuit Selektiwerstärker is provided the selective amplifier filters and amplifies the respectively set spectral line at the frequency η ■ / 0 and indicates the acting as envelope detector downstream rectifier GR a sinusoidal oscillation of the frequency π · fO . The rectifier in turn generates a direct voltage with superimposed alternating voltage components, which is then

switched second low-pass filter TPl are fed. A second decision maker E 2 is connected to this second low-pass filter and also emits an alarm signal ALI if the DC voltage at its input falls below a certain preset value. For universal applicability of the monitoring circuit described, it is advantageous to make the evaluation circuit 21 switchable for different frame code words and the monitoring circuit 28 switchable for different frame lengths TO. In this way, a transmission path for digital time-division multiplex signals with different pulse frames can be monitored in a simple manner. The length of the frame passwords of the individual time division multiplex systems is expediently selected with regard to the synchronization time. However, since the synchronization time plays a subordinate role in the monitoring arrangement described, the arrangement can be simplified by not monitoring all the bits of the frame password.In a practical embodiment, for example, there is sufficient monitoring if one of the ten bits of the frame password is one: time division multiplex signal with a bit rate of 8448 kbit / i, only 8 bits can be evaluated. In this case, a simple eight-bit shift register, which is available as an integrated module, can then be used as shift register 21.

For this purpose 2 BIaU drawings

Claims (4)

Claims: 5. Arrangement according to claim 3, characterized in that the monitoring circuit 1. A method for monitoring digital (28) signals connected to its input (11), which in the duration of a frame contains corresponding amplifiers (Vs) , which at a corresponding time intervals a monitoring 5 frequency according to the input or multiple sync word, in particular a frame code of the frame frequency of the digital signals, that it is true at the monitoring point that the monitoring circuit continues to recognize this sync word in the continuous time with the output of the selective amplification multiplex signals, a corresponding bee connected series circuit of a constant pulse signal output and its occurrence over- 10 converter (Gr), a second low-pass filter (TP2) and a watch, characterized in that the second decision maker (ES 2) contains and to which the frequency-dependent low-noise distribution of the output of the second decision maker an alarm pre-pulse signal (E) for the presence of ri attention can be connected discrete power components (spectral lines) the frequencies that will be monitored after the 15th One or more times the frame frequency of the digital talen time-division multiplexed signals. 2. The method according to claim 1, characterized in that from the pulse signal (E) a The invention relates to a method for monitoring sinusoidal oscillation with a frequency obtained 20 chung of digital signals, the duration of which is one or more times the frame frequency frame corresponding time intervals corresponds to the frequency of the digital time division multiplex signal monitoring serving synchronous word, in particular and this supplied to a synchronous demodulator contain a frame core word that is monitored by means of the generated sinusoidal oscillation as the intersection point of this synchronous word in the carrier oscillation passed through from the Pulse signal (E) a 25 recognized the time division multiplex signals, generates a corresponding DC voltage, which emits the occurrence of the pulse signal and signals its occurrence over discrete power components, and that is monitored, and arrangements for carrying out this undershooting of the DC voltage under a process. pre-selected threshold value an alarm is triggered For the monitoring of digital signals there are will. 30 mainly two processes, on the one hand the monitoring 3. Arrangement for carrying out the method chung by utilizing the redundancy of the code used in the transmission according to patent claims 1 and 2, and on the other hand the net that a first shift register (21) is provided for monitoring a frame on the receiving side, the number of stages is at least equal to the synchronization word provided for synchronization, in particular the number of bits of the synchronization word and 35 special of the frame password. Since in principle higher inputs of a second detection circuit (22) reliability can be achieved when monitoring the step outputs separately with the chung of the synchronous word, it is mainly connected with the fact that the signal input of the second use of this possibility is made to this shift register (21) with a connection for this purpose, an arrangement is used in accordance with the German disclosure monitoring digital time division multiplex signal and the 40 scripture 22 06 969 which is indicated in the clock input of this shift register with a F i g. 1 is shown In this arrangement, the source for the bit clock of the digital time division multiplex signal D to be monitored is connected together with time division multiplex signals that the output with the associated clock signal T serially into the input of the second detection circuit (22) with the n-place shift register 1 read in. The π outputs input of a first monitoring circuit (28) 45 of the shift register 1 are mil the η inputs of the connected to the occurrence of discrete first detection circuit 2 is connected. Every time Performance shares in the frequency-dependent line if the fl-digit frame password is in the J power distribution of the pulse signal (E) with a shift register 1 is the first detection switch p or multiple frame frequency and device 2 sends a pulse signal E to the monitoring t; whose output signal is reduced in the absence of the discrete 50 device 3. When the frame is recognized for the first time Performance proportions changes accordingly. The monitoring circuit 3 gives a password 4. Arrangement according to claim 3, thereby clear pulse CL to a connected clock center 4 f marked that the monitoring circuit from. The clock center 4 generates from the bit clock signal Γ a phase control frame clock TR connected to its input (1) and others in the respective one t: loop (PLL) and a clock required both with the output 55 transmission system; the clear pulse For this purpose, the phase-locked loop as well as with the input (1) CL sets the divider stages of the clock center 4 in its % of the monitoring circuit connected Syn- starting position. Using the from the clock center jb chrondemodulator (Sd), a first with the generated frame clock TA monitors the monitoring f output of the synchronous demodulator connected circuit 3 the periodic occurrence of the [Low pass (TP) and one with the output of the eo frame password in the digital time division multiplex signal D. Low-pass associated first decision maker (ESi) The exact rules about the loss or the contains that the phase locked loop (PLL) restores the frame synchronism accordingly is set up to respond to the recommendations of the international postal authorities on a frequency. corresponding to the single or multiple of de (CCITT-G 732,742,751). Frame frequency of the digital signals synchronous- <> >. If the frame synchronicity is lost, the siert and that the output signal of the first Ent- monitoring circuit 3 from an alarm signal A 1. There Scheider (ESi) is fed to an alarm device if the clock fails, the monitoring circuit 3 will. cannot give an alarm signal is an additional one