DE2737134A1 - Single transistor V=shaped MOS memory cell - using sapphire or beryllium oxide substrate for epitaxial silicon layer contg. pn junctions - Google Patents

Abstract

The cell has an inorganic, insulating substrate (1) covered by a zone (2) of one conductivity type (a) and an epitaxial monocrystalline semiconducting layer (3) of opposite conductivity (b); layer (3) contain zone (2) and also a separate upper zone (4) of conductivity (a). In layer (3) is a V-groove (V) penetrating right through zone (4) and at least reaching zone (2). In groove (V) is a layer (V1) of insulating material, covered by a gate electrode (G) for the capacitative steering of the two pn junctions. Substrate (1) is pref. sapphire or monocrystalline BeO, whereas layer (3) is Si with a surface coinciding with a (100) plane. Groove (V) is pref. an inverted quadratic pyramid made using square holes in an etching mask. MOS memories with a very high packing density are obtd.

Description

Method for producing a single transistor safety cell

The invention relates to a method for producing a one-transistor memory cell, in which a monocrystalline semiconductor layer on the flat surface of a substrate body deposited epitaxially, two superposed in the semiconductor layer Zones of one conductivity type are generated in such a way that they are through one of the opposite Conductivity type semiconductor areas are completely separated from each other, in which also from the surface of the monocrystalline semiconductor layer one leading through the upper of the two superimposed zones and the lower of the two zones at least reaching a depression with to be converged in depth flat boundary surfaces, then the semiconductor surface in the recess covered with a layer of insulating material and finally with one inside The gate electrode arranged in the recess for the capacitive control of the semiconductor surface two pn junctions between the two on top of each other that reach within the depression arranged zones of a conduction type is provided.

The two zones of one conduction type arranged one above the other form the source and the drain zone of a capacitively controlled by the gate electrode NOS Beldeffekttransistor, in which the pn-8 junction of one of these zones, in particular the zone to be acted upon as the source is designed in such a way that it is practical represents the total storage capacity while the other zone made low-capacity and as a connection to an analog memory cell, is preferably provided as a bit line.

Such a VMOS memory cell as it is defined on the basis of the above Procedure is obtained, for example, in the reference "ElectronicsR (April 1, 1976), P. 77 and 78. In making these cells one goes to the ones there Ausithrungen of an n + -doped disk-shaped silicon single crystal from the surface of which is epitaxially deposited a p-doped monocrystalline silicon layer is, inevitably the lower part of the epitaxial silicon layer one is given certain doping by donor material diffusing out of the substrate. Diffusion is then masked on the surface of the epitaxial layer or implantation generates a second zone that receives the conductivity type of the substrate. Finally, the epitaxial layer is on the surface within the second Zone creates the recess with V-shaped converging boundary walls and driven up to or into the substrate.

Then the surface of the epitaxial layer becomes inside the recess lined with a thin insulating layer made of pure SiO2 and then by vapor deposition or sputtering with a thin, e.g. aluminum or doped Silicon existing gate electrode provided. An alternative to this manufacturing process consists in that one of a p + -doped substrate made of single crystal silicon goes out, on the surface of which in the manner of a buried layer by masked implantation or diffusion creates an island-like zone with n + doping, which then covered with a p-doped epitaxial layer made of single crystal silicon will. Above the island-like bounded zone of the n + -type then one of them second zone of the n + type which is completely separated by the p-doped material of the substrate generated, in which then the V-shaped converging depression is generated and up to the island-like limited zone is driven forward.

The advantage of such a device is obvious - manufactured in {OS technology - Memory in that it has a particularly high packing density of the memory cells permitted. In such a case, the recess will converge with a V-shape 3 boundary walls # r in the shape of an inverted square pyramid, but in Apply the shape of a trench that has the shape of an inverted symmetrical roof has, which is parallel to the columns of the memory matrix containing the memory cell runs.

As has now been recognized according to the invention, the properties of such a memory cell, in particular also the lifetime of one stored in it Information, improve significantly if you follow the manufacturing process defined above applies and designed it according to the invention in such a way that on the flat surface of a substrate made of inorganic insulating material, the single crystal Semiconductor layer deposited and in it the lower of the two arranged one above the other Zones is produced in such a way that it directly adjoins the substrate.

Monocrystalline is advantageously used as the insulating substrate A1203 (sapphire) or monocrystalline beryllium oxide, as a semiconductor material monocrystalline Silicon. The planar surface of the substrate will preferably be chosen in such a way that the free surface of the silicon layer deposited on it with a (100) plane of the silicon lattice collapses. This is the case with one made of sapphire existing substrate on one with a (1, 0, 1, 2) -plane or (1, 0, 1, 2) -plane and in the case of a substrate made of monocrystalline beryllium oxide on one with a (1, 2, 1, O) - or (1, 0, 1, 0) -plane coinciding surface the monocrystalline Silicon is deposited.

As is well known, the following applies with regard to the creation of the depressions Facts: The fact that the etching speed in one Silicon single crystal is a tensor, such that the transfer speed is smallest perpendicular to the (lll) planes. For this reason, Use of appropriately matched etching agents and etching mask spontaneously indentations generate whose four boundary surfaces each one of the four families of (lll) planes of the silicon lattice. As a result, the recesses are given the shape an inverted square pyramid when you have an etch mask with a square Etching window generated on a (100) -oriented surface of a silicon crystal, when the edges of the etching window run parallel to the (III) planes. ~ Degenerate " the square to a rectangle, you get a correspondingly long trench with V-shaped converging side walls. Dilute potassium hydroxide is the main agent (KOH) or rubidium lye (RbOH) and as the material for the etching mask, pure SiO2 in Consideration.

In a first way of carrying out the method according to the invention becomes on the flat surface of a substrate made of sapphire or BeO a first highly doped silicon layer of one conductivity type is deposited in such a way that that the free surface of this silicon layer coincides with a (100) plane.

Then this silicon layer is re-created by means of a photoresist etch technique of the substrate with the exception of the one for the lower of the two to be arranged one above the other Zones of one line type removed. The doping of these first is preferred epitaxial layer n +.

On the remains of this first epitaxial layer and its surroundings a second epitaxial silicon layer is deposited so that its surface coincides with a (100) plane of the silicon lattice. The doping of this second epitaxial layer is chosen so that it has the opposite conductivity type to that of the first epitaxial layer. Eventually, on the surface the second epitaxial layer by masked implantation or diffusion die the second of the zones arranged one above the other is generated, so that z.3. an n + -p -n + zone sequence receives. Finally, in the area of the upper of these zones, a relaxed ecSene to the (11) levels of the Silicon lattice oriented Xtz mask the The recess is created and driven into the lower zone, possibly even as far as the substrate. After creating the recess, its surface is covered with a thin layer pure SiO2, the surface of which is lined with a gate electrode Metallization made of Al or a doped polysilicon layer as a gate electrode is provided.

In a second way of carrying out the method according to the invention becomes the surface of the insulating substrate intended for silicon deposition covered with an implantation mask, which is only attached to the for the lower of the the two points provided in the epitaxial layers to be deposited Leaves substrate surface uncovered. Then it is applied to the surface of the substrate Doping depot, e.g. created by donors by implantation, by adding the doping Atoms with high concentration, but also only with shallow depth in the insulating Substrate to be shot into. Then, after the substrate has been tempered, a opposite conductivity type, e.g. p-type epitaxial layer on the The substrate surface freed from the implantation mask is deposited in such a way that that the free surface of the epitaxial layer with a (100) plane of the silicon lattice coincides. This diffuses from the applied to the surface of the substrate Doping depot doping atoms in the adjacent lower region of the epitaxial Layer and there form the lower of the two zones of the one conductivity type. The second of the two is then superimposed on the surface of the epitaxial layer arranged zones of a conduction type formed such that between the two Zones a separating strip of the conductivity type of the deposited substrate material, that is of the opposite conductivity type remains. Otherwise, the next one takes place Manufacturing process in the first embodiment of the invention Procedure specified way.

In a third way of carrying out the method according to the invention becomes on the surface of the insulating substrate first the epitaxial layer with opposite conductivity type, e.g. p-type, deposited in such a way that its free surface coincides with a (100) plane of the silicon lattice. Then at the place provided for the two zones arranged one above the other the semiconductor surface by means of an implantation mask for the lower one dopant provided in both zones is injected in such a way that it is redoped in the area of the lower of the two zones to be generated. buf this way For example, the lower of the two zones of the n + type is created. If necessary, will in a second doping process, e.g. by diffusion above this lower one Zone restored the original conductivity type of the substrate. In the end becomes the upper of the two on the semiconductor surface above the lower zone Zones of a conductivity type by implantation or diffusion, in particular from ntryp, generated.

A first one-transistor memory cell produced on the basis of the method according to the invention will now be described in more detail with reference to FIG. The etching mask for creating the recess with V-shaped converging walls has been tested with square etched windows. For this reason, the recess V became a tip-down one square pyramid.

On the surface of the insulating substrate S is the p-doped epitaxial layer E deposited and using one of those described above Methods with the two superimposed zones C and B have been provided. Nazi realizes that the lateral geometry of the two n + zones C and B are different is chosen. The lower zone is preferably on the relevant one-transistor memory cell limited and with its pn junction equipped with a high doping gradient represents the storage capacity of the cell in question. The upper zone B, on the other hand, has a low-capacitance pn junction and / or a pn junction with through the recess V greatly reduced area if they at the same time not only play the role of the relevant memory cell associated drain zone (possibly also source zone), but at the same time that of an electrical connection leading to the neighboring cells, e.g. Bit line, should take over.

Outside the depressions V is the surface of the epitaxial Layer s with a thick layer of SiO2, inside the recess V, however just covered with a thin SiO2 layer, as can be seen from the section through the recess V drawn Fig. 1 recognizes. The oxide layer is labeled 0. Furthermore, in the recess V, the gate electrode G is in the form of a thin metalization, e.g. made of aluminum. Just like the drain zone of the individual cells as Bit line B connects to within the same matrix column of the integrated Memory arrangement lying identically dimensioned one-transistor memory cells the individual gate electrodes G are produced from within a matrix line lying memory cells over a line-parallel extending Metallisi Connect the connection strips in order to create a word line parallel to each row in this way W to get.

The strip width of the bit line B is, for example, 7 / µm, the distance between two adjacent memory cells of the matrix to '14 / um, the side length of the square recess V to 5 / µm, the width of the word line to 9 / µm, the thickness of the semiconductor epitaxial layer E to 4.5 / µm, the depth the capacity zone C, i.e. the lower of the two zones arranged one above the other of one type of conduction, to 2.5 / um and the depth of the bit line B, i.e. the upper « of the two zones of one conductivity type, set to 1 / µm. The depth of the pyramidal Wells V is thus inevitably defined, because this is through four (III) planes are defined, which through the edges of the recess V delimiting Squares on the surface of the epitaxial layer.

The arrangement shown in FIG. 1 readily leads to semiconductor memory matrices with a bit density of 5000 bits / mm2.

If you want to increase the bit density considerably, you turn instead the recesses V, which resemble an inverted pyramid, are channel-shaped or trench-shaped Wells V, which, as mentioned above, by using appropriately designed etching mask can easily arise spontaneously through etching. The depression will, as can be seen from Fig. 2, in such a way by the upper of the superposed Zones of a conduction type forming bit line out and in the lower zone pushed to the limit of the insulating substrate S that both the through the lower zones formed by the capacity zones C as well as by the upper zones bit lines formed are halved with the formation of two separate zones will. In this way, those from FIG. 1 can be seen from the individual zones B and C Device In each case two separate zones B and C were created, so that one doubles Number of one-transistor memory cells arranged on both sides of the recess V. and are only connected via the common gate electrode or word line W.

It is easy to understand that you are using twice the bit density than with an arrangement according to FIG. 1 can be obtained.

The embodiment of one-transistor memory cells shown in FIG. 3 and their union into a semiconductor memory matrix can be based on a achieve another variant of the method according to the invention. Essential for this Ausiffhrungsform is that the insulating substrate adjacent to the.

the superimposed zones of one conduction type as a bit line B, the other is designed as a storage capacitor C, one electrode of the storage capacitor is given by a doped polysilicon layer Si, which is separated from zone C by a thin oxide layer 0 ', and which is in operation of the finished arrangement is to be laid on Nasse. The polysilicon layer Si is strip-shaped formed and extends in each case along a matrix column analogous to that of the Column belonging to the bit line over the tops of the individual silicon islands and the between the individual trench-like depressions arranged in the column direction remaining bit lines 3.-When making such an arrangement will on the surface of the insulating substrate S initially a single-crystal semiconductor layer of one conduction type, in the example an n layer deposited, which the Basis for the system of Forms bit lines, for example be switched as source. Bni of this single crystal semiconductor layer becomes a second monocrystalline semiconductor layer having the opposite conductivity type, in the example case a p-doped semiconductor layer is deposited, which in turn is covered with a semiconductor layer of one conductivity type. This can from a less doped lower part and a heavily doped upper part exist, so that for the example there is a lower n zone and an upper n + zone for Eapssiätszone C.

Using a correspondingly shaped etching mask that is placed on a with a (100) -plane of the silicon lattice coinciding surface of the epitaxial Layer E is generated, this is made by a system of equidistant, equally dimensioned trench-shaped depressions V in a number of equal dimensions, with each other merely disassembled strips connected via the insulating substrate S, through which the individual columns of the matrix to be produced are defined. The direction of this Stripe is chosen so that it is parallel to one of the four families of (111) faces of the silicon lattice are oriented.

By a second and oriented perpendicular to the direction of the stripes System of trenches becomes the capacity zone and ggi. the zone from the opposite Line type, i.e. the p-zone and the + -zone covering it, but not the as Bit line provided lower n + zone divided into individual islands, each form an element of the memory matrix. The surface of the arrangement is now with a thin oxide layer 0 'covered.

A layer of doped polysilicon is formed on the oxide layer 0 ' deposited, which by means of photoresist etching technology in strips of the same size Si is divided, which is parallel to the individual bit lines in the direction of the matrix columns and both above the capacitance zones a in the individual Islands are located as well as across the second system of trench-like depressions extend and thus all memory elements belonging to a matrix column Form associated capacitive electrode, which should be placed e.g. on wet ground in case of operation is.

Finally, the surface of the arrangement is covered with another - thicker - oxide layer 0, e.g. by buffer sputtering, which is then used to support the row-parallel word lines W is made. Similar to the examples According to FIG. 1 and FIG. 2, the oxide layer 0 can extend up to the substrate surface continuous, column-parallel extending trench-like depressions V thinner than on the top of the islands in the area above the polysilicon layer Si are made to have an internal effect, sivating the control effect on the pn junctions of the individual memory cells and the channel formation of the associated transistor Use of appropriate control voltages to obtain.

The use of a substrate made of insulating material ensures substantial security Advantages in terms of electrical properties and the speed power product one such memory matrix. This is how the parasitic capacitances, especially those of the Bit lines compared to the same arrangement are considerably reduced as usual a doped semiconductor crystal is used as the substrate.

Furthermore, the storage capacitor C is in one due to the invention Method obtained memory arrangement better than the conventional arrangement isolated, as only reverse currents me through the transistor of the memory cell, not on the other hand to the substrate S can occur. Also, one can because of the use of an insulating Substrate S allow very small gaps between the individual memory cells, which is especially true if you have a memory arrangement according to Fig.3 The application of the polysilicon strips Si in the case of the one described in accordance with FIG. 3 Arrangement above the two superimposed zones of one conduction type on the one hand ensures a particularly high storage capacity, while on the other hand the required ~ manufacturing processes simpler than the rest of those described above Methods is to be carried out. However, one must ensure that the etching of the Trenches running in the row direction - in contrast to those running in the column direction Trenches V - those provided as bit lines. lower epitaxial part layer of one Do not interrupt the line type. It should be noted that in the case of the one shown in FIG Arrangement, the upper n + zone C can also be replaced by an inversion layer.

3 Figures 18 claims

Claims (18)

Patent method for producing a single-transistor memory cell, in the case of a sia-crystalline semiconductor layer on the flat surface of a substrate body deposited epitaxially and arranged in the semiconductor layer two coils Zones of a conductivity type are generated in such a way that they are through a. the opposite conductivity type semiconductor region from each other are completely separated, in addition, from the surface of the monocrystalline Semiconductor layer ago one through the upper of the two arranged one above the other Depression leading to the zones and at least reaching the lower of the two zones produced with flat boundary surfaces converging in depth, then the semiconductor surface in the recess with a layer of insulating material covered and finally with a gate electrode arranged within the recess for capacitive control of the semiconductor surface within the recess reaching two pn junctions between the two superimposed zones of one type of pipe is provided, d u r c h e k e n n n z e i c h -n e t, that on the flat surface of an existing inorganic insulating material The single-crystalline semiconductor layer is deposited on the substrate and the lower one in it of the two superimposed zones is produced in such a way that they are immediately adjoins the substrate. 2. The method according to claim 1, characterized in that the substrate body (S) a sapphire disk and silicon is used as the semiconductor material. 3. The method according to claim 1, characterized in that the substrate a disk made of single-crystal BeO and used as semiconductor material silicon will. 4. The method according to claim 2 or 3, characterized in that the surface side of the substrate to be provided with the epitaxial silicon layer is chosen so that the surface the epitaxial layer with coincides with a (100) plane of the silicon lattice. 5. The method according to claim 2 and 4, characterized in that as Deposition surface for the epitaxial silicon layer is a (1010) plane Sapphire bedded substrate is used. 6. The method according to claim 3 and 4, characterized in that as Deposition surface for the epitaxial silicon layer is a (1210) plane or a (1010) plane of the substrate made of single crystal Be0 is used. 7, method according to any one of claims 1 to 6, characterized in that that on the surface of the substrate (S) a first one having a conductivity type deposited monocrystalline epitaxial # semiconductor layer and then with the aid of a Photoresist ttechnk on that for the lower of the two to be arranged one above the other Reduced zones of a conduction type provided area on the substrate surface is that then the in this way arose in the lower zone and its surroundings the substrate with an epitaxial having the opposite conductivity type Semiconductor layer covered and on the surface of this epitaxial layer second of the zones to be arranged one above the other of a conduction type by local Redoping is generated on the surface of the epitaxial layer and finally in the second of these zones the depression with converging boundary planes, the insulating layer lining them and the pn-t # processes of the two zones capacitive controlling gate electrode are produced. 8. The method according to any one of claims 1 to 7, characterized in that that on the surface side intended for the deposition of the epitaxial semiconductor layer of the substrate body by means of masked implantation on the doping of the lower of the two zones to be arranged one above the other of the one conductivity type dimensioned doping depot generated by ion implantation and then a epitaxial semiconductor layer having the opposite conductivity type deposited and on its surface the second of the superposed zones of the one Conduction type is produced that then on the surface of this zone the recess with converging boundary planes, in the recess the insulating layer lining them and on this insulating layer the pn- # transitions of the two zones of one conductivity type capacitively controlling gate electrode are generated. 9. The method according to any one of claims I to 8, characterized in that that on the surface of the insulating substrate first the epitaxial layer deposited with the opposite conductivity type that then in a first implantation process in it the two zones of one conductivity type and adjacent to the substrate then the upper of these two zones is generated that then on the surface of the the upper of these two zones is the depression with converging flat boundary surfaces, the insulating layer lining them as well as the gate electrode are produced on this will. 10. The method according to any one of claims 1 to 9, characterized in, that on the surface of the insulating substrate body initially a zone of one Conduction type, then on top of this a zone of opposite conduction type and finally on. this again a zone of one conductivity type is deposited and that at least the upper zone by a depression with converging flat boundary surfaces divided into two separate parts and finally an insulating layer in the recess and a metallization is applied to this. 11. The method according to any one of claims 1 to 9, characterized in that that the to generate the wells with converging - limiting planes to using etching masks are provided with windows, the edges of which are parallel to at least a (111) plane of the silicon lattice. 12. The method according to claim 11, characterized in that the for Production of the two zones to be arranged one above the other from one line type using doping and itzxs8ken with Windows are provided, the wheels of which run parallel to at least one (111) plane of the silicon lattice. 13. A method for fabricating one from one-transistor memory cells built-up memory matrix according to one of claims 1 to 12, characterized in that that the upper of the two zones to be arranged one above the other is of one conduction type each of the memory cells to be produced in the epitaxial semiconductor layer each Memory cell is individually assigned and equipped with a pn junction, which represents practically the entire storage capacity of the cell in question, while that of the two to be produced on the surface of the epitaxial semiconductor layer Zones of one conductivity type for the purpose of combining the one matrix column each belonging memory cells as a bit line with only a small capacity and than all in the relevant matrix column located memory elements common zone is designed. 14. The method according to claim 13, characterized in that the gate electrodes of the memory elements belonging to the individual Xatrix lines via a common on one of the surface of the epitaxial layer outside of the recess converging flat boundary surfaces covering thick insulating layer guided metallization strips are summarized. 15. The method according to any one of claims 1 to 14, characterized in that that the depressions with converging flat boundary surfaces as reverse square pyramids are designed. 16. The method according to any one of claims 1 to 14, characterized in that that the depressions with converging flat boundary surfaces as being rectilinear extending trenches are designed with a homogeneous cross-section. 17. The method according to any one of claims 9, 13 and 16, characterized in that that the superposed epitaxial Uslleiterschichten different Conduction type through a system of equidistant, equally sized and parallel to each other running trench-like depressions with planes that converge towards the depth Boundary surfaces are divided into parallel strips that are only about the insulating substrate are in communication that # also at least the upper layer of one type of conduction through a similar one, but not up to insulating substrate continuous system of trench-like depressions in the parallel Re st strip of the epitaxial layer is divided into individual sections, the at least over the lower of the partial layers having the one conductivity type the epitaxial layer and at most over the opposite conductivity type having these sub-layers related that also the surface of the Remnants of the epitaxial semiconductor layer still present with an SiO2 layer coated and that finally perpendicular to the reaching up to the insulating substrate Trench-like depressions over all the remaining strips of the epitaxial semiconductor layer Networking tires running parallel to each other can be seen in such a way that that they attach the individual remaining strips of the epitaxial semiconductor layer to the still with the upper partial layer of a conductivity type of the epitaxial semiconductor layer provided parts of the Re st strip this cross. 18. The method according to claim 17, characterized in that according to the Manufacture of the entire epitaxial semiconductor layer and the upper part layer of a conduction type separating trench-like depressions and the cover the remaining residues of the epitaxial semiconductor layer with a SiO2 layer the top of these residues covered with a layer of doped polysilicon will that then on the surface of the total order of all residues of the epitaxial Semiconductor layer and the layer of polysilicon deposited on this one second oxide layer and only on this the system of transverse to the strip-shaped Metallization strips running remnants of the epitaxial semiconductor layer is applied.