DE2842334A1 - SEMI-CONDUCTOR ARRANGEMENT - Google Patents

Description

Semiconductor device

The invention relates to a semiconductor arrangement as specified in more detail in the preamble of claim 1, as well as a method of making them.

The invention particularly relates to semiconductor logic circuits as well as on semiconductor memory arrays.

US Pat. No. 4,010,036, assigned to the assignee, discloses a single insulated gate (IGFET) memory cell with a buried memory element which is used in a semiconductor read / write memory device . In this prior art memory cell, a buried memory ^{element of a first conductivity type (N +} ) is used, which is located within a substrate with a different conductivity type (P ⁺ ). An etched recess with a V-shaped cross section extends with its lower end into the buried element which forms the source electrode of a VMOS transistor. The recess also extends through

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a further region of the first conductivity type which, in the vicinity of its upper end, forms the drain electrode of the VMOS transistor. The walls of the recess are provided with a thin gate oxide layer and this oxide is covered with a conductive material which serves both as a gate and forms part of the word line of the arrangement. In operation, the N ⁺ buried source element forms the memory array of the cell and the drain region forms part of the buried bit lines. The above-mentioned one-transistor memory element according to the prior art represents an improvement with clear advantages over the three-transistor and six-transistor planar memory cells developed earlier. However, this embodiment also required the formation of transistor drain regions , and the charge capacity of the device was limited by the size of the ^ buried storage elements.

The object of the invention is to provide an improved semiconductor memory cell which is provided with an etched indentation, but which is opposite to the state of the Technique shows undisclosed advantages by using only an etched groove or recess which shows a relatively small space requirement on a substrate, so that the cell density in a memory array per unit area can be extremely high. The invention also aims to provide a single groove or depression using semiconductor memory cells are specified, in which non-buried drain regions in combination with a buried source region can be used to form a transistor, but in the case of a single buried bit line and a thin layer of material on the walls surrounding the recess as a charge storage area be used. Next with the invention

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a semiconductor memory array can be specified, with an array of memory cells at the crossover points is formed by surface word lines with buried bit lines transversely thereto, each Cell exhibits increased charge storage capacity and speed than the one-transistor memory cell According to the state of the art. Furthermore, a semiconductor memory cell is to be specified with the invention, which uses a groove-like type of recess which is less complicated and fewer manufacturing steps required, so that the manufacturing method for a semiconductor memory device is improved and becomes more efficient.

This object is achieved by a semiconductor memory arrangement specified in more detail in the preamble of patent claim 1 solved, designed according to the invention according to the specified in the characterizing part of claim 1 manner is.

Further, advantageous configurations of the semiconductor memory arrangement according to the invention and various, advantageous ones Refinements of a method suitable for producing the semiconductor memory arrangement are shown in FIG Subclaims specified.

The semiconductor memory arrangement according to the invention has a substrate which carries an array of memory cells; included (Each cell has a single well or a single Return to the surface of the arrangement, its lower end into a buried bit line within of the substrate penetrates. Word lines are parallel to and spaced apart from one another on the surface of the arrangement made of conductive material arranged vertically

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to the buried bit lines and which extend into the depressions or the recesses of the memory cells extend. Each well has a threshold barrier at its top as well as one Diffusion wall at its lower end adjacent to the bit line in the material that finds the recess forms a charge storage region so that part of the word line in each recess forms a gate with which the flow of charge to and from the bit line can be modulated during read and write operations.

A preferred embodiment of a memory array according to the present invention comprises an array of memory cells in which each cell has an etched recess with a V- or U-shaped cross-section which extends into the top surface of a semiconductor substrate. The substrate, which is of the first conductivity type, has at least one buried bit line of opposite conductivity type and the lower end of the recess extends therein. Adjacent to and above the buried bit line is a diffusion wall which surrounds the lower end of the recess and which prevents charge from flowing away from the remaining area around the sides of the recess. Within the recess, the sides of the recess can be covered with a thin gate oxide layer in the manner of an IGFET structure. Alternatively, the walls of the recess can be covered directly with conductive material which forms an arrangement similar to a junction field effect transistor (JFET). For the IGFET arrangement, the oxide is covered with a conductive material, which can consist of metal or of polycrystalline silicon. This conductive material forms (for both cases) a gate for the memory cell and also part of an ^M X "line.

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device or word line that is transverse to the buried bit line or the "Y" line. if a memory cell is to be used in a semiconductor memory device which has a large number of word lines and has buried bit lines, then the memory cell can be at each crossing of these lines be trained. In fact, the area that forms the walls and that each T or U-shaped indentation becomes surrounds to a relatively large charge storage area for the cell, and the charge is within this area by means of an insulating threshold barrier located near the top of the recess and a located near the bottom of the recess diffusion wall held. If the Cell is to be written, a voltage is applied to the buried bit line, and then a another voltage is applied to the word line, the latter voltage being such that it is less than that Surface potential of the walls of the recess. This results in a thin layer of epitaxial material around the walls of the recess acts as a storage element and reaches a surface potential equal to that of the underlying bit line is. When the surface potential is removed from the word line, so will cut off the diffusion wall between the buried bit line and the charge storage region, so that the Charge storage area is isolated and separated in the walls of the recess. This charge remains as long stored until the cell is read out. In order to scan the charge, i.e. to read the cell, is again a voltage of suitable polarity is applied to the word line so that an electrical connection between the Charge storage area and the bit line is reached via the diffusion wall. This way it becomes a certain

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Amount of charge determined by the surface potentials and the geometric factors determined is transmitted to the bit line, resulting in a certain potential difference between the existing level and the original level of the bit line, which with a Differential amplifier can be detected.

The invention will now be described below with reference to individual exemplary embodiments and the figures explained in more detail.

1 shows a schematic plan view of a section from a semiconductor memory arrangement with charge storage cells according to the invention,

Fig.2 shows a cross section of a memory cell in who embodies the basic ideas of this invention,

3a show the ver-3i in a series of cross-sections process steps for fabricating a memory cell in accordance with the principles of this invention,

4a show, in a series of cross-sections, _alternative method steps for forming the lower diffusion wall area according to the invention,

FIG. 5 shows a vertical cross section of a modified embodiment of the memory cell according to FIG of the invention, and

6 shows in a vertical cross section a further, alternative embodiment of a memory cell,

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which makes use of the principles of this invention and which uses a U-shaped depression will.

The Fig.1 shows a schematic plan view of a Semiconductor memory device 10 to which the principles of the present invention are applied. The one shown Part of the arrangement has an array of memory cells 12 at the intersections of parallel word lines 14 with a series of buried bit lines 16 running perpendicular to the word lines will. In this field, the memory cells are tightly packed because the parallel word extensions and the Bit lines are relatively close together using conventional rules for semiconductor designs can; Each memory cell essentially only requires the area that is defined by the intersection or crossover a word line and a bit line is formed.

2 shows the structure in a vertical cross section a typical single memory cell 12 according to the invention. The entire memory array is as integrated Circuit constructed on the basis of a semiconductor substrate 18 made of P or N conductive material. In In the illustrated embodiment, the base substrate consists of crystalline silicon, which is essentially one has a uniform thickness (e.g. about 250 µm). This material is doped with boron with an Eoncentra-

1 ¹ O 1Q ^ α.

tion of 10 ^ to 10 ^y atoms per cnr provided with a P ⁺ conductivity.

The parallel bit lines 16, which are essentially one of uniform width and spacing, consist of! ^ - material within the base sub-

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strates 18. The thickness of these bit lines is substantially uniform (e.g., about 2 microns); these bit lines have N conductivity, preferably with

19 20 3

a carrier concentration "of 10 to 10 atoms per cm, by using a dopant with a low diffusion coefficient, for example arsenic or antimony, can be achieved.

The base substrate 18 and the buried bit lines 16 are covered with an epitaxial layer 20 of lightly doped P or F "* material covered with an ordinary Gas phase deposition process (CVD process) has been produced. At the transition between these Layer 20 and the base substrate 18 is an intermediate layer 22, which also consists of P-material, but which is more heavily P-doped than the epitaxial layer 20.

It extends from the surface of the epitaxial layer 20 at each crossover point of a word line a bit line down a recess 24 which has a Y-shaped cross section in the vertical direction. These depressions are formed with the process of anisotropic etching, which has a low attack speed along the [i1 IJ planes and has a high attack speed on the jjooj planes, as shown in U.S. Patent No. 3,924,265. This etching process forms the depressions 24, their side walls converge in the downward direction, the lower edge formed by the converging side walls each recess extends into a buried bit line 16. In the horizontal direction, the V-shaped Wells square or rectangular shape and their sloping walls are covered with a thin gate

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Oxide layer 26 made of silicon dioxide, which is also buried under the upper surface of a Bit line 16 extends. The word lines 14 are off conductive material, for example from a suitable metal or from polycrystalline silicon, and each recess is essentially filled with such conductive material.

The epitaxial, lightly P-doped material 20 that the inclined side walls of the V-shaped depressions 24 forms, contains a charge storage area 28, which extends completely around the recess adjacent to the thin gate oxide layer 26. As by the dashed line is indicated in Fig.2, this charge storage area 28 may be flat, but ssine charge capacity is relatively large, since it takes up the entire area of all four inclined side walls of each well covered.

The top edges of the gate oxide layer 26 terminate at the edges of each V-shaped recess, and at this At point, the thickness of the oxide layer increases abruptly, so that a relatively thick insulating oxide layer 30 is formed covering the epitaxial layer 20 around the various recesses 24. This relatively thick oxide layer 30 forms a barrier (indicated by reference numeral 32) around the top of each recess, the helps maintain the carrier concentration within the inclined charge storage area 28. This retention is based on the effective surface potential beneath the thick insulator area 30 at voltages used during the operation of the cell.

The compared to the epitexial P material is relative

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higher P-doped intermediate layer 22, which surrounds the lower end of each recess, forms a lower one Lock for the charge storage area. The upper and lower barriers are used to control the carrier concentration of the electrons within the storage areas 28 on the sloping sidewalls of each well trained to hold back. The work according to the well-known principles of field effect arrangements Layers 22 and 30 due to the Qua si-Fermi level in the silicon as barriers that prevent the electrons from migrate out of the walls of each well, be it along the top surface 30 or into the top Surface of the buried bit line layer 16 on the Bottom of the recess.

In addition to its blocking effect, the P-type is used Intermediate layer 22 as a transition region which contributes to the flow of electrons from the bit line into the charge storage region 28 to control in or out of this. Furthermore, this transition area or the diffusion wall 22 with the gate portion of the word line that covers the gate oxide layer within the recess, modulated.

When operating the memory cell 12 'according to the invention is to be written into the cell, a voltage is first applied to the appropriate bit line. Thereafter, such a voltage is applied to the word line that the surface potential of the junction region is lowered. That means the positive Voltage on the word line (and thus on the gate of the cell) essentially causes the transition region between the bit line and the charge storage area 28 "turn on". When this occurs, the charge

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storage area has a surface potential that is equal to that of the bit line, so that charge is stored there will. The surface potential is now controlled by the bit line 16 in the charge storage area. When the voltage or surface potential on the word line is removed, the flow of electrons ceases between the bit line and the charge storage area. So at this point is the surface potential isolated within the charge storage area. Since the charge storage area 28 is completely around the As the recess extends around over all inclined walls, it thus covers a relatively large area, and accordingly the charge storage capacity is relatively large. Thus, when this writing operation has been carried out, a strong, permanent signal is enclosed in the memory cell.

If the stored charge is to be queried in a read-out process for the memory cell in order to determine whether a "1" or a "0" is stored in it, the function of the elements is similar Digit "floats" the bit line, i.e. it is at an intermediate potential, which is specified, and from from which all relative changes are made. A voltage of positive value is applied to the word line which in turn results in the bit line being connected to the charge storage region 28. That causes the circle to come into equilibrium, being on the bit line versus the original Potential a potential difference occurs, which can be determined with a suitable differential reading circuit of the arrangement is. Such a sense amplifier circuit is known in the prior art for memory arrangements and is therefore used not described in detail here.

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The listed write and read functions of the memory cell 12 can be done mathematically by applying the laws of conservation of surface potential during the write-in phase and the maintenance of the charge during the read-out phase as well as during read-out by reading the differential voltage can be described.

A method for producing a memory arrangement 10 according to this invention will now be described with reference to FIGS. 3a to 3f. First, it is necessary to have a substrate 18 made of crystalline silicon material with a P ⁺ -

15 19

Charge carrier concentration of 10 to 10 atoms per car provide. This material must also have a crystallographic orientation at which the L100J plane on the surface, so that V-shaped grooves or depressions can be generated therein by anisotropic etching.

To form a first mask, the substrate 18 is provided with a layer 34 of silicon dioxide, which can be formed by oxidizing the substrate surface ^{in steam at 800 to 1200 ° C.} The oxide layer is then treated with a suitable etchant (for example with buffered hydrofluoric acid) in order to remove the oxide at the locations on the substrate surface where the buried bit lines 16 are to be formed. As shown in FIG. 3a, a diffusion with N ⁺ material (for example with antimony) is then carried out in order ^{to produce an N +} buried layer 16 which has a thickness of approximately 2 μm. The oxidation layer 34 is then removed, so that a substrate is obtained in which a series of parallel N ⁺ -doped strips are present at a predetermined distance from one another.

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In the next process step, an epitaxial layer 20 of weakly P -doped material is formed on the substrate surface and on the N ⁺ regions 16, as shown in FIG. This layer can be achieved by thermal decomposition of silane (SiH.) At a temperature of about 800 to 1000 ^° C. with a thickness of about 2.5 μm in an epitaxial reactor. During the formation of the epitaxial layer 20 and the simultaneous heat treatment, the P-material diffuses out of the P-substrate, which creates the transition boundary layer 22, which extends by about 0.5 ^{μm above the N +} -doped buried layer expands.

Another oxide layer 36 is then deposited on the assembly and a second mask is used to define the spaced apart openings 38 which are directly above and aligned with ^{the buried N + regions.} Using an anisotropic etchant (e.g., hydrazine and water), a V-shaped indentation 24 is created at each opening of the assembly above an N -region, with the bottom of each indentation extending into the N ⁺ region, as shown in FIG the Fig.3c is shown.

Using a conventional oxidation process, a thin gate oxide layer 26 is now left with a typical Thickness between 500 and 1000 S grow within the recess 24 (compare Fig.3d).

The surfaces of the V-shaped, groove-shaped depressions are masked with the aid of a further oxidation in order to remove the Provide field oxide layer 30 surrounding each recess (see Figure 3e).

Then another mask (not shown) is

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applies, the conductive word lines 14 do accordingly 3f, these word lines running from recess to recess and perpendicular to the buried bit lines 16 are aligned. The word lines can be made of polycrystalline silicon or consist of metal, and they can with a suitable (not shown) passivation layer of an insulating and protective material.

Clay the surface of the arrangement can, where it is necessary, contacts (not shown) through the epitaxial Layer 20 is carried out to the various bit lines in accordance with the known manufacturing method will.

As has been described above, the intermediate layer 22 made of P-conductive material provides the diffusion wall for the charge storage region 28. Other types of this diffusion wall can also be achieved with other method steps within the scope of this invention. For example, according to FIGS. 4a to 4c, the diffusion wall can also be produced by diffusion or ion implantation of a thin P-element 40 directly on the areas. This is carried out immediately after the formation of the N ⁺ regions using the same mask 34 and before the epitaxial layer 20 is deposited (see FIG. 4a). The epitaxial layer 20 is then deposited as described above (compare FIG. 4b). When the V-shaped recesses are formed, the P-layer 40 on a jecLen N ⁺ -bit line 16 surrounds the lower part of each recess, thereby fulfilling its separating function (FIG. 4c).

Another type of diffusion wall can thereby be formed

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that a layer of P-material is deposited on all areas of the substrate with the exception of the N ^{+ areas.} However, this method requires the application of a second mask after the creation of the N ⁺ regions. A subsequent heat treatment leads to the fact that the P-material ^{diffuses over the N +} regions surrounding the respective depressions and that a further shape of the lower diffusion wall is thereby formed.

In a further alternative embodiment of the invention, a field effect transistor with an isolated Gate (IGFET) corresponding structure of the embodiment described above can be replaced by an arrangement, which has the structure of a junction field effect transistor (JFET). In this latter embodiment, in accordance with FIG. 5, no oxide layer is provided within the recess of an individual cell. Instead, will a suitable conductive material 14a, for example Platinum or some other metal used for the word lines. The metal is located inside the depressions directly on the walls of the depressions and forms Schottky transitions there, so that due to a Schottky effect Load carriers can be transferred. In this case, the functions of the upper and lower locks and the surrounding charge storage areas those in the IGFET embodiment already described.

Although the invention has been described using exemplary embodiments in which the depressions by means of Anisotropic etching have been brought to a V-shaped cross-section, it is also possible to use a semiconductor memory device instead 10b to be provided, in which the recesses 24b are designed so that they are with a U-

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shaped cross-section and not with in the downward direction converging side walls are provided. Such recesses are formed by the silicon wafer is first cut in such a way that its horizontal surface lies in the jj 10 | crystal plane and their M11J planes are perpendicular to the horizontal plane. As shown in Fig.6, extends the U-shaped recess 24b corresponding to the previously described V-shaped recesses 24 by an epitaxial Layer 24b through into a bit line 16b which is located within substrate 18b. The order may be provided with a thin oxide layer 26b which, according to the IGFET embodiment, is located within The recess is located, but it can also be of the Schottky JFET design have according to Fig.5. There is one inside the U-shaped recess Layer of conductive material 14b, for example made of polycrystalline silicon, and which forms the gate part of the word line. According to the embodiment having a V-shaped cell cross-section, there is an upper charge barrier 32b around the top of each Recess in the form of a relatively thick insulating oxide layer 30b. There is also a lower cargo lock in the form of a thin P-layer 22b, which the buried bit line region 16b around the lower end of a covered every well. The top and bottom locks control that on the parallel side walls of the recess 24b located charge storage area in the same way as it was already for the case of V-shaped depressions 24 was described.

The patent attorney

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. -SS-

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Claims (12)

Claims \\ J semiconductor memory arrangement, characterized by a substrate (18, 18b) of a first conductivity type, a number of elongate areas of a second conductivity type within the substrate, which bit lines (16) form, an epitaxial layer (20) of lightly doped material of the first conductivity type forming the substrate and covers the elongated areas forming the bit lines (16), a number of depressions (24) extending from the surface of the epitaxial layer (20) and from each other are arranged separately along the bit lines (16), each of these recesses (24) from side walls which extend into the elongated areas forming the bit lines (16), a relatively thick field oxide layer (30) overlying the epitaxial layer (20) and each well (24) surrounds this thick oxide layer (30) a field threshold barrier layer (32) at the top of a each recess (24) forms, a series of parallel, spaced apart elongated areas of conductive material, the word lines 909827/0610 2042334 Forming lines (14) on the field oxide layer, each word line (14) running transversely to the bit lines (16) and between a row of τοη wells (24) and along wells aligned therewith, means that extend on the bit lines ( 16) near the lower end of each well and forming a diffusion wall, and by charge storage regions (28) formed on the sidewalls of each well (24) between the diffusion wall and the field threshold barrier (32). 2. Semiconductor memory arrangement according to claim 1, characterized by a P ⁺ -type silicon substrate (18), N ⁺ -type bit lines (16), and through an intermediate layer (22, 40) of P-type material forming a diffusion wall, which the bit lines around the lower end of each Well covered. 3. Semiconductor memory arrangement according to claim 2, characterized characterized in that the epitaxial layer (20, 40) consists of P "-conducting material, which is weaker is doped as the intermediate layer (22). 4. Semiconductor memory arrangement according to claim 1, characterized characterized in that the top surface of the substrate (18) with the epitaxial thereon Layer (20) lies in a £ 10OJ crystal plane and that each of the recesses (24) in the upper surface has a V-shaped cross section. 5. A semiconductor memory device according to claim 1, characterized in that the upper surface of the substrate material (18b) is in an [i 1 θ] crystal plane 909827/0610 and that each recess (24b) has parallel side walls and a bottom so that its cross-section Is U-shaped. 6. Semiconductor memory arrangement according to claim 1, characterized characterized in that a relatively thin layer of oxide (26, 26b) forms the side walls of each recess covered and that the conductive material of each word line (14) this thin oxide layer (26, 26b) within of each well. 7. Semiconductor memory device according to claim 6, characterized in that the conductive material of each word line (14) made of polycrystalline silicon consists. 8. Semiconductor memory arrangement according to claim 1, characterized characterized in that the conductive material of each word line is a metal forming the wall surfaces each well (24) covered and a Schottky effect for the transfer of charge between the Charge storage areas (28) and the bit lines (16) evokes. 9. The method for producing a semiconductor memory arrangement according to one of claims 1 to 8, characterized by the following method ^{steps: producing a substrate (18) from crystalline silicon of P +} conductivity, Forming a series of spaced apart diffused strips of N ⁺ conductive material within the substrate to create buried bit lines (16), Forming a diffusion boundary layer (22, 40) over the buried bit lines made of P-conductive material 909827/0810 rial, which is less heavily P-doped than the substrate , Deposition of an epitaxial layer (20) on the substrate, which has a weaker P ~ conductivity, and which is less heavily doped than the diffusion boundary layer (22, 40), etching a number of spatially separated depressions (24, 24b) within the surface of this array, which are so arranged and aligned are that each recess through the epitaxial layer (20) 1 - '. :-( ·] ITtI-: in one of the bit lines (16) extends, Forming a relatively thick layer (30, 30b) of oxidic material around the upper edges of the depressions and Forming connecting lines serving as word lines (14) made of conductive material on the oxidic material, which is transverse to the buried Bit lines (16) run, each of these word lines (14, 14b) being a series of aligned Recesses (24, 24b) connects to one another and the side walls of these aligned with one another Wells (24) covered. 10. The method according to claim 9, characterized in that the process step serving to form the diffusion wall (or the diffusion barrier layer) during the application of the epitaxial layer (20) comprises a heat treatment which diffuses out of P-material in this epitaxial layer (20). 11. The method according to claim 9, characterized in that the formation of the diffusion 909827/0610 sion wall (or the diffusion barrier layer) (40) serving process step comprises an ion implantation of a thin layer (40) with the P-doping material is introduced into the diffused strips of N ⁺ material immediately after their formation and using the same mask. 12. The method according to claim 9, characterized in that the method step with the within a thin layer of gate oxide material (26) is created in each recess prior to formation the word lines (14) located within the depressions (24) takes place. 909827/0610