DE2735478A1 - RECEIVING DEVICE - Google Patents

Description

The invention relates to a signaling device between switching devices or switching devices in one Telephone network receives and sends signals, and relates in particular to a receiving / transmitting device that moves through Can adapt word commands so that it has the necessary scope and transmit function over a wide range of signaling structures.

The economical manufacture of telephone switching equipment is often determined by the size of the world market in which the manufacturer is selling the device can. The future development of new and possibly better telecommunication exchanges will seriously considered from the point of view of the available market potential. One of the main factors driving the Determining the market size and thus also the sales opportunities on the market is the adaptability of the switching facility of the manufacturer on the telephone network standards in the various countries. It is easy to see that the Switching facility before they even get of a possible one Buyer will be considered must be compatible with the customer's existing telephone network.

One of the requirements that the typical telephone switching device must meet is that they have monitoring information received from other switches and monitoring information to other switches can send. Typically, this is done by means of dialing impulses and / or audible signals. Different telephone systems show different standards with regard to frequency or speed and the pulse length ratio of dial pulses. There are also various audio mark standards that relate to the Frequency, amplitude, duration and the combination of audio signals and in certain cases also whether or not signaling is necessary or not necessary. For example

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becomes the multi-frequency signaling system in North America (MF system) used almost universally. With the MF signaling system A destination or intermediate office sends a "proceed to send signal" to the departure office »whereupon the departure office all the monitoring information on audio signals sends. In Europe, the multiple frequency forced task procedure is used (CMP process) applied. In this system sends an office of departure a surveillance information mark until the Endamt indicates via another audio signal that the required monitoring signal has been received, whereupon this Procedure for each character is continued until all of the desired monitoring information is transmitted and received has been.

In order to receive and transmit signals, the device in the particular telephone system must be connected to the signaling system or be compatible with the signaling systems. Undoubtedly the main compatibility problem lies in attempting a switch one type of construction to adapt to telephone networks that use different signaling schemes or formats own. Typically a new receiver / transmitter will need to be used with the switching device and with the signaling scheme of the customer's telephone network should be compatible, each time they are redesigned and developed a manufacturer wants to open up a market that has a different type of signaling system. However, this brings with two major disadvantages; On the one hand, the manufacturer has to bear the costs of new planning and development, which means an economic disadvantage for him, especially compared to a local manufacturer; and the second If the manufacturer is consequently unable to do so, just as promDt like the domestic manufacturer to deliver.

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2735A78

The object of the invention is now to address these disadvantages to avoid.

To solve this problem, a receiving / transmitting device is created by the invention, which is for use in many of the well known automatic telephone network signaling systems is programmable. The puncture of the receiving / transmitting device is that it responds to word commands. The word commands can be processed in a suitably programmed processor with one or more receiving / transmitting units of these units, or in one or more central processing units in the switching device be derived. An input / output circuit is located as an interconnection between each receiving / transmitting device and the assigned processor. The receiving / transmitting device detects HörZeichensignale, these also transmitted, and transmitted Dialing pulses, the parameters of which are determined by command word sets, which the system or the systems in which the receiver / transmitter must work, are clearly assigned.

The receiving / transmitting device, in cooperation with a switching device, has a word memory and for generation of clock signals a clock generator. Each clock signal has a pulse repetition frequency, which is determined by an assigned word, obtained from a predetermined location in the word memory is defined. For receiving signals from the telephone network a receiver is connected to the clock. The center frequency of the passband of the receiver is through the repetition rate of one of those generated by the clock Clock signals determined. A signal generating device is also connected to the clock and transmits an audible signal at a frequency determined by the repetition frequency another of the clock signals is determined. Because the frequency of different clock signals from the clock generator the working frequencies of the receiver and the signal diffraction

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determine device, and since the frequencies of the clock signals are determined by assigned word commands from the word memory, the receiving / transmitting device is so adaptable that it can be used for different signal structures for monitoring signaling signals serves as an intermediary between telephone networks.

One of the main elements that contribute to this adaptability of the receiver / transmitter is the clock circuit, which is used to generate clock signals. The clock circuit is responsive to a master clock signal having a predetermined repetition frequency and to command words each of which, in cooperation with the master clock frequency, determines one of the plurality of clock signals. The clock circuit has a bit circulator which contains bit registers for the lowest and highest significant values. Each bit register has a plurality of stages corresponding in number to the plurality of clock signals generated and is responsive to the master clock signal to shift bits through. An adder has inputs and outputs connected to the first and last stages, respectively, of each of the bit registers. The adder also has inputs to receive the bits of the command words. The bits from the command word are added to the last stage bits of each bit register in the adder, and the sum is applied to the first stage of the bit register. A sample and store device stores the bit in each stage of the most significant bit register at the time given by the frequency of the master clock signal divided by the number of clock signals, thereby increasing the pulse repetition frequency at each output of the sample and store device is defined by the master clock signal and the associated command word.

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In a simple embodiment, the clock circuit generates a frequency that is the master clock frequency times the value of a command word divided by a number η is equivalent to. The clock contains an adder with a first input for receiving the command word, with η second inputs and η outputs. A bit circulator with η sections is between the η second inputs and the η Outputs switched, and responds to the master clock signal so that it bits from the η outputs with a delay from the period of the pulse repetition frequency of the master clock signal to the corresponding η inputs leaves. The output of that section of the η sections of the bit circulator that have the highest priority is the generated clock signal.

The invention is described below, for example, with reference to the accompanying drawing; in this shows:

Fig. 1 is a schematic block diagram of a reception / Transmitting device connected to a telephone switching device connected is,

2 shows a diagram with which the dependencies between the remaining figures of the drawing are shown,

FIG. 3 is a schematic block diagram of one used in FIG word-controlled clock,

Fig. 4 is a schematic block diagram of a clock controlled Multi-frequency signal generator used in Figure 1

Fig. 5 is a schematic block diagram of a filter and Fading compensation circuit used in Fig. 1

Fig. 6 is a schematic block diagram of the clock-controlled filter circuits used in Fig. 1, and

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- ΊΟ -

7 is a schematic block diagram of a register and Verification circuit used in FIG.

As can be seen from Fig. 1, the receiving / transmitting device is with a telephone switch 10 via signal capture and signal transmission trunk circuits 11 and 12, and with address and data bus lines 13 and 1'I- connected. A clock circuit 20 carries clock pulses CK1 to a serial address generator 21 which generates repetitive sequences of 12 address words. The address words become a word memory 22 and an input-output circuit 15 supplied. Data appearing on data bus 14 is entered into word memory 22 through the input -Output circuit written if the address on the Adressensamraelleitung 13 matches the address from the serial address generator 21 matches. The serial address generator 21 generates one of twelve words at each termination Sequence of addresses also includes a clock pulse CK2. Consequently the clock pulse CK2 appears at a speed of one twelfth the speed of the clock pulses CK1. These Clock pulses are input from the word memory 22 to a word-controlled clock generator 23 together with 12 data words per clock pulse. The word-controlled clock generator 23 sends 12 clock signals to the lines in a main clock signal line 24. The frequency of each of the clock signals is determined by the frequency of the clock pulses CK1 and by the value of its corresponding data word determined by the word memory 22. The frequency of the generated clock signal is multiplied by the frequency of CK1 with the corresponding data word and divided by a specified factor.

Telephone switching equipment 10 places connections between them the telephone network and the signal trunk circuits 11 and 12 fe3t. Signals doe from the signal receiving trunk circuit 11 are received in a balanced configuration by an amplifier 30 and from here in unbalanced configuration of an analog AGC amplifier and associated filter circuits 31 are transmitted. The scarf

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Lines 31 are via a high-band line 32 »a medium-band line 33 and a low-band line 34- with clock-controlled Filter circuits 35 connected. The analog AGC amplifier changes signals with a large amplitude range in such a way that these amolitudes lie in a narrow range. The filter circuits are controlled by switches so that one or more frequency passbands are selected to receive signals from the AGC amplifier to the filter circuit 35 to be transmitted. The filter circuits 35 include a plurality of passband circuits, each of which is driven by a clock signal on the main clock line 24 is adjustable to its center frequency.

A word memory 4-0 is connected to the input-output circuit 15 via a two-way main data line 41 and an address home line 42 connected. Received signal input control data is transferred over lines 43 from word memory 40 to the analog AGC amplifier and the filter circuits 31 and to the clock-controlled Filter circuits 35 are transmitted to determine the bands passed through the filter circuits 31 and the input configuration of the controlled filter circuits 35. Each of the filter circuits 35 compares the amplitude of a signal in its pass band with a threshold level, and generates a binary output signal on a digital output main line for this purpose 36b. The digital output main line is provided with a register circuit 37 and a checking circuit 38 tied together. An analog output line 36a and a threshold signal line 39 lie between the filter circuits 35 and the checking circuit 38. The checking circuit 38 determines in a check whether there is sufficient signal through any of the filters in the controlled filter circuits 35 is passed and determines whether signals are on the digital output trunk 36b for the required time periods

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exist and remain in the correct combination for the representation of a valid signaling. Also creates this circuit the threshold signal on line 39 for use by the filter circuit 35. The outputs of the register circuit $ 7 and the verification circuit 38 are via a Audio reception data manifold 44a or via a verification data manifold 44b led to word memory 40. the Information from these buses is stored in word memory 40 for access by telephone switching device 10 the priority output circuit 15 is held. Thus the received by the reception signaling trunk circuit 11 Signaling is digitally recorded in register 37 and in word memory 40, with an indication of the validity of the received Signals is also recorded in the word memory 40.

Signaling transmitted by the receiving / transmitting device is also controlled by word commands via the word-controlled clock generator 23. Each of the clock-controlled signal generator circuits 45 is connected to an individual line in clock bus 24, and is also with a word location in word memory 40 via lines in an output amplitude data bus 46. Each of the clock-controlled signal generator circuits 45 generates a sine wave function, the frequency of which is in relation to the clock pulse repetition frequency of the clock signals on the assigned line in the clock bus 24 and their Amplitude corresponds essentially to the amplitude that is transmitted by a into the memory 40 through the bus 46 Amplitude word is determined. Output signals, i.e. the sine wave functions, are added together and sent to the input an amplifier 47 which amplifies the output signals and outputs these signals in a balanced configuration the signal transmission trunk circuit 12 applies.

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The output of pulses is similarly determined by the clock pulse repetition frequency on one of the lines in the clock bus 24 · controlled, which with a clock-controlled Dial pulse generator circuit (DP encoder circuit) 48 connected i3t. This means that transmission speeds are used for the dialing pulses achieved, which are adjustable and very accurate. The character for a transmission is in a word position in the word memory 4-0 stored, which is via a character data Saramelle line 4-9 is connected to the DP transmitter circuit 48. The pulse length ratio of dialing pulses can be specified internally in the DP encoder or can be saved by an additional word from the word store 4 * 0 can be determined. There are various commercially available digital circuit designs that act as dial pulse generators 48 can be used. An example of this is in GA-PS 926 04-9 with the title "Dial Pulse and Multiple Frequency Signaling Receiver Apparatus ", A.E. Dodson, May 8, 1973". Since that time there has been a wide range of different types of integrated circuits that are commercially available, economically attractive and ideally suited for performing this function, which, however, are based on the principles the dial pulse generation, as it is essentially based on A.E. Dodson was taught. The output of the clock-controlled DP encoder circuit 4-8 is connected to the signal transmission trunk line circuit 12 connected.

The inventive, insofar as described in FIG. 1 as an example Embodiment shows one form of system configuration and operation of an apparatus that meets the requirements a receiving / transmitting device that adapts to a variety of signaling systems through the use of word commands lets be fulfilled. A more detailed discussion of the individual components follows on the basis of Fig. 3-7 » which are related to each other as shown in FIG.

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p ^ ttnci

s.

Fig. 3 shows a word-controlled clock, the one Data input 3OO for receiving eight-bit words, a clock input line 3OI for receiving clock signals (GK1) and a clock input line 302 has, with which it receives clock signals (CK2) at a fraction of the speed of the clock signals (CK1). In this embodiment the speed of the clock signals (CK2) is one twelfth of the speed of the clock signals (CK1). the ■ Clock signals (GK1) and the clock signals (CK2) are generated by the clock generator 20 of FIG. 1 and received by the serial address generator 21 of FIG. The eight-bit words are used by the The output of the Wortsneichers 22 received, with a new word at the data input 3OO synchronous with each clock signal (CK1) is recorded. The data input 3OO is with the input an adder 3O3 connected. A nine-bit output of the Adder 303 is connected to the data input of a register 304 connected, which also has an input that is connected to the clock input line 301. The outcome of the Register 304 is connected to an adder 3 ^ 0 via a data input 311 of the adder 310 is connected. Ten data output lines 321-330 are located between 10 outputs of the adder 'J1O and the corresponding inputs of 10 shift registers .331-340, each of which has 12 levels. The shift register 331 is used as the least significant value Shift register, and the shift register 3 ^ O as the largest Significance indicating. Called shift register. Each shift register 331-340 contains a shift input which is connected to the Clock input line 3OI is connected. The outcome of the last stage of each of the shift registers 331-3 ^ 0 is on one of 10 further inputs of the adder is connected via lines 341-35O. A clock output register 360 contains 12 Inputs connected to the outputs of the 12 stages of the most significant shift register 34-0. The clock output register 3 / * 0 also contains for the receipt of Clock signals (CK2) have an input and is connected to the clock input line 3O2 connected.

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In operation, the clock signal of the lowest frequency that can be generated is determined by the adder 303, which always adds a constant (+32) to the spring command word, the register J) OH- the command word +32 each time a clock pulse appears on line 301 picks up. The shift registers 331-34-0 are caused to shift by the clock signal on the line 301 and are thus synchronized with the input of the register 304-. The output of the last stage of each of the shift registers 331-34-0 is applied to the adder via lines 34-1-350, respectively. The output signal of register 304 and the bits on lines 341-350 are added together, the sum word being applied to the corresponding first stages of shift registers 331-340 via adder outputs 321-330. The most significant bit of each sum word is entered into the clock output register each time a clock pulse (CK2) appears on line 302. Each sum word increases in value to a maximum, beyond which it returns to zero and increases again. Each sum word is monitored by the clock output register 360 at the moment at which each sum word is in the shift registers 331 at a suitable predetermined location. This has the effect that a clock signal with a 50 % duty cycle is generated at each of the twelve outputs of the clock output register. These output clock signals appear on corresponding lines 370-381; these signals are referred to below as corresponding clocks 0-11. Each of these clocks 0-11 has a repetition frequency which is proportional to the value of the instruction words from the corresponding word locations in the word memory 22 of FIG.

A more detailed explanation of the theory of the mode of operation of the word-controlled clock generator according to FIG. 3 now follows. however, an understanding of the detailed theory of operation for constructing this exemplified embodiment is not necessary. A detailed understanding of the operation of the word-driven clock is

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then helpful when considering the specifics for the mode of operation of the receiving / transmitting device at any given Want to derive signal structure required word commands. The detailed explanation is simplified by that the mode of operation of only a single measure is considered; it takes the time staggering aspect of the hardware according to FIG. 3 out of consideration as this is used to generate multiple clock pulses to create. Thus, each shift register 331-340 has a length of only one stage instead of 12 stages, and the pulse repetition frequency of CK1 is equal to that of GK2.

Shift registers 331-340 store at any one time the numerical value Qx. The registers are continuously clocked by the clock signal with the frequency fm, and the contents the registers change with each clock pulse so that

■ * (x + D " ^w modulo 2 ^u;

(N ^ 10 in this embodiment)

where P is a programmable value and K is a fixed value i.5t, and where

P + K <2 ^N ~ ¹ (2)

If you combine (1) and (2), the value of Q results as follows

Q _{x + 1} = Q _x + P ₊ K if (Q _x + P ₊ K) <2 ^N (3a) Q _{x + 1} = Q _x + P ₊ K - 2 ^N if (Q _x + P ₊ K ) * 2 ^N (3b)

The highest value characteristic of Q bit is ,, if Q ^ 2 ^N ~ is high ( "high") defines ^one, and is as deep ( "low") defined when Q <2 ^{N -1.} Because of equation (2), Q takes at least two and at most 2 / (P ₊ K) clock pulses to cycle through, which is a low-high cycle

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of the most significant MSB bit of Q. The high-low transition of the MSB bit is through characterizes equation (3b).

According to η Taktimrmlsen

^ _V 4.n = iQ _v + (P + K) * η modulo 2 or Q " - = Q + η * (P + K) - m * 2 ^N (4-b)

Γθ + η * (P + K)
where m = integer - ^ π

For η = 2, this becomes

ra - integer] -§- + P + K | = P + K

since —fj <■ 1 by definition i:; t; 2 ^1N

Thus, 0 ₊₂ ^N = Q _x

N This means that the cycle always ends after 2 clock pulses repeats, and that during each cycle the number of high-to-low transitions of the MSB bit is equal to P + K. So that is programmed frequency

fp = fm *

The number (t) of clock pulses between any two Tdef transitions of the MSB bit is derived as follows:

Any value 0 is chosen so that

Q _x + P + K * 2 ^N (6b)

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so Q ^ ₊₁ = Q ^ + P + K - 2 ^Ν

from this it follows that

⁰ * Q _{x +} I ^{<P + K (7)}

After t clock pulses and A high-low transitions we get:

where 0 ± Q ₊ * _{+ t} <P + K (9)

From (7, 8, 9) it follows:

t = Λ *

j.

Λ ^ 2

where E <1.

P ^N fm

The factor -p-rr = 7 ^ ^ ^st the average period of the output programmed frequency fp, expressed as a fraction of clock pulses CK1; E is the rounding error that occurs when t is made an integer. The time between any two (and not just between two consecutive) transitions deviates from the average value by less than one clock period of the clock generator CK1. This has the effect that even after one more simple division of fp by R to obtain fx, the phase uncertainty of fx is less than one clock period of fm.

According to Fig. 4-, two sine function generators generate the AC signaling within the voice band required for the operation of the switching equipment i; 3t. Each sine function generator is operated by controlled a clock. The first Sirus function generator

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has a clock input 410 that connects to line 370 3 is connected, while a clock input 411 of the second sine function generator is likewise connected to the line 371 connected is. Data input lines 460 carry output Amplitude data from multipath line 46 of FIG. 1 to, • each the sine function generators.

Referring to Figure 4, only one of the sine function generators is used described below, since the other generator is identical in structure and mode of operation.

The sine function generator contains a divider circuit 420 with the division ratio 1: 4, which is between the clock input 410 and a shift input 422 of a shift register 421 is located. The shift register has eight stages, with the output of the last stage is connected to the input of the first stage. The first four stages have input inputs that are connected to earth, i.e. represent a binary one, and the last four stages have input inputs that start with a positive voltage, i.e. represent a binary zero. Each of these stages is also equipped with a locking device Input line 423 connected. The data input lines 460 are with the input of a digital logarithmic-linear-analog signal converter circuit 461 connected, which has an analog output 462, which is connected to the input of a buffer amplifier 463 is connected. Each of eight transfer switches 430-437 is connected to the output of the buffer amplifier 463 connected. Each of the transfer switches 430-437 is with connected to the output of a corresponding stage of the shift register. The output from each of the transfer switches 430-437 is connected to the input of a low-pass filter 448 via an associated resistor 440 - 447. In the following Table shows suitable ratio values of the resistances for the function of the sine wave generation:

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carrier no: h

Reference number of the Resistance value Resistance 440 and 447 505 R 441 and 446 177 R 442 and 445 118 R 443 and 444 100 r

The output of the low pass filter 448 is connected to an output terminal 412 connected. In the case of the second sine function generator the output connection has the reference number 413 According to FIG. 1, the line 415 of FIG. 4 corresponds to the line, which connects the clock-controlled signal generator circuit 45 to the input of the amplifier 47.

Since transfer switches 430-437 are identical, only one switch 437 is shown in detail. The transfer switch contains a switch control input 470 and an amplitude control input 471. The input 470 is connected to the inputs of an inverting buffer 472 and to the input of a non-inverting buffer 473. Each gate of a pair of transmission gates has an input gate 475, an output gate 476 and a control gate 477. One of the transfer gates 474 is connected to the output of the buffer 472 via its control gate 477, and its second gate is connected to the amplitude control input . The other of the transmission gates 474 is connected to the output of the buffer 473 via its control gate 477 and its input gate is connected to earth or Hasse. The output gates 476 are connected to one another and form the output of the transmission switch, which in this case is connected to the resistor 447 .

During operation, the application of a signal on the blocking and charging line 423 is controlled directly by the switching device or switching device or indirectly via a bit in the word memory 40 . The signal-applying causes

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that the shift register 421 is loaded, the first four stages being low and the last four stages being high. if the signal on line 423 is not applied, clock signals from line 370 are passed through divider circuit 420 divided by the division ratio 1: 4; the resulting signal at input 422 causes shift register 421 pushes through. Since the output of the last stage is connected to the input of the first stage, the result is an effective one Result that of a circulating square wave with half the steps of shift register 421 always high and half of the levels are always low.

This circulating square wave causes the control inputs of the transfer switches 430-437 to switch the resistors 440 - 447 alternating with earth and with the amplitude control input Connect 471 via transmission gate 474. The data appearing on lines 460 are a logarithmic representation of the desired signal amplitude in decibels. This data is converted into an equivalent analog voltage are converted, and are after amplification with the voltage amplification factor unity by the buffer amplifier 46 ^ applied to input 471. Definitely from here the voltage at input 471 is directly the amplitude of the alternating current signal, which passes through the low pass filter 448. The AC signal from filter 448 is matched with the signal from the deep wet filter added up in the other sine function generator. This of course assumes that lines 423 from the two Generators are linked. However, if the generators are controlled independently of each other, that breaks Apply a signal on line 423 of a generator whose operation and the receiver-transmitter would then also generate signaling at a single frequency as required by the switching device.

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According to Fig. 5, AC analog signals are on a Line 501 received. Line 501 is the connection between the amplifier 30 and the circuits 51 according to Fig. 1 equivalent. Between the line 501 and the Resistors 504 and 5O5 lie. a deep wet filter 5O2 resp. a high pass filter 503 in series. The transmission switch 506 and 507 »which the transfer switches 4-30-437

flT * fcicr are
4 equal / Ixegen between the resistors 504 and 505 and the input of a fading compensation circuit (AGC-Sehaltung) or. Automatic fading 510. Switch control lines 508 and 509 are connected so that they control inputs of transmission gates 506 and 507, respectively. The AGC circuit 510 has an output terminal 511 'which is connected to the inputs of a low-band filter 512, a medium-band filter

515 and a high band filter 514 · is connected. Every servant Filter is with the corresponding output line 515,

516 and 517 connected.

In operation, the circuit of Fig. 5 determines the fundamental receive band of the receiving / transmitting device. AC signals on line 501 having a frequency within the transmission ranges of low or high pass band filters 502 and 503 are passed to transmission switches 506 or 507 accordingly. Depending on the state (low or high) of lines 5O8 and 5O9, the outputs of filters 50,? and 505 operatively connected to AGC circuit 510 or to ground. Thus, the reception range is defined as high band, low band or both high and low band. The JIG circuit 510 amplifies signals which it has caught at its input omofree and which have an amplitude within a range of about 33 dB, so that these signals at the output of the ACtC circuit 510 have an amplitude which is no more than 1 varies up to 2 dB. These signals are separated according to the frequency on the 3 lines 515-517 by the filters 512-514.

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The circuit according to FIG. 6, in combination with the circuit according to FIG. 3, makes the receiving part of the receiving / transmitting device highly flexible. The circuit of Figure 6 includes eight switch filters 622-629 preceded by twelve filter transfer switches 630-641. Each of the filter transfer switches 63O-633, 636 and 639 has an input which is connected to the high band filter 514 via a line 517 of FIG. Similarly, switches 63I, 634, 637 and 640 are connected to medium band filter 513 via line 516, and switches 632, 635, 639 and 641 are connected to low band filter 512 via line 515. Each of the filter transfer switches 63O-641 is similar to the transfer gates 43O- 437 of FIG. 4 and the transfer switches 506 and 507 of FIG. 5, with the exception that an additional resistor 642 is connected in series with the input port of the transfer gates. Each of the filter transfer switches also contains a control input which is separately connected to a decoder circuit 621. The decoder circuit 621 also has two outputs which are connected to the inputs of the transfer switches 506 and 507 via lines 508 and 509 in Fig. 5. The decoder circuit 621 also includes inputs that are connected with the multiple conduits 643, are received via the command words. This contrasts with another arrangement in FIG. 1 where the analog AGC amplifier and filter circuit 31 and clocked filter circuit 35 are shown to be controlled directly by command words from word memory 40 via receive signal control data bus 43 . Each of the switch filters contains, the filter circuit 629 serving as an example, a divider circuit 644 with the divider ratio 1:64, in which the three stages, which indicate the most significant values, are connected to the input of a decoder circuit 645, which works according to the decoding law "one out of eight". The decoding circuit 645 is connected to the control inputs of eight transmission gates 671-678. Each of the transmission gates lies between one

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adds ■■>! other » J ^

geändei

Electrode of one of the capacitors 681-688 and one

+ V

positive voltage leading line € ?? Q. The other electrodes of the capacitors 681 - 688 are connected together at the input of a rectifier circuit 689. The exit the rectifier circuit is connected to a signal input 691 of a correlator circuit 690 and also to the anode electrode a diode 619 connected. An input resistance 679 is between the signal input of the switch filter and the connection of the capacitors 681-688 and the input of the rectifier circuit 689 connected in series. The comparator circuit 690 has a threshold value input, the a threshold line 617 common to all switch filters and also includes a digital one Output connected to a line 699. The comparator circuit 690 in the remaining switch filters 622 is similarly connected to line 692-698, respectively. The cathode electrode of each of the diodes 619 is connected to a signal threshold line 618.

In operation of the circuit of FIG. 6, signals from the outputs of filters 515-517 of FIG. 5 become different Switch filters of the switch filters 622-629 passed, as they are passed through the outputs of the decoder 621, which the states of the Filter transfer switch 63O-641 controls are set. Clock signals from the clock output register are matched or matched in advance by the divider circuit 644 with the division ratio 1:64. pre-set and decoded by the decoder 645 so that in the following they "switch on" each of the transmission gates 671-678, that each of the capacitors 681-688 are sequentially individually connected to the positive voltage Line 6 £ &. Is connected. Each of these capacitors represents actually represents a switch portion of the filter. When a gate is "on" its associated capacitor begins to on its input level of the signal voltage from one of the filter transmission

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naohtrMgUch alleviated

switch to load. However, the time constant of resistor 679 and capacitor is much greater than the gate's "on time" so that the capacitor cannot be fully charged during a single "on-time interval". The time constant determines the bandwidth of the filter in that the longer the time constant, the smaller the bandwidth. If the input signal has a multiple of the switching frequency of gate 671-673, the signal at a special capacitor is the same every time the tfugeo-dne gate is switched on. After a number of switch cycles, the voltage across the capacitor will reach the value of the input signal. Random or randomly distributed signals, periodic signals and signals that are neriodic, but whose frequency is not a multiple of the switch frequency, are not stored in the capacitors. Signals that are within the bandwidth of the filter will eventually appear at the input of rectifier circuit 639 with essentially no significant attenuation. The rectifier circuit is preferably an active rectifier having an input impedance much higher than the resistance of resistors 679. The rectifier circuit 689 generates a signal which is representative of the envelope of the

Amplitude of the signal at its output. The output signal of the rectifier is compared by the Komoarator-Gchaitung 690 with a threshold voltage on the line 617. At the moment when the threshold value-:. ^% . If the voltage is less than the output signal of the rectifier i ■■ t, the comoarator circuit 690 applies a signal to its assigned output line 692-699. The diode 619 in, each π «of the switch filters connects the rectified outputs for the threshold value line 618 to form a logical ODEtt circuit. From the outputs of the circuit device of FIG. 6, the presence of a signaling frequency which is received and which falls within the limits determined by a command word is detected, and a

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Measurement of its amplitude, when received by the switch filter, is carried out via diode 619.

According to Fig. 7, there is the task of checking and unloading or readout circuit therein, both analog and digital received audio signals or audio signals from switch filters 622-629, and by measuring the amplitude, combination and duration of these signals to decide whether valid data has been received. The circuit also provides a threshold value signal for the switch filters 622-629 ready.

In order to carry out the necessary determination, the circuit works with a time graduation of three intervals. A start timer initially measures the time of signal presence for a period of about 35 milliseconds to the initial To determine the presence of signaling. A subsequent signaling is considered valid signaling before this it is assumed that a timing is performed which is smaller by about 10 milliseconds. This time difference is provided to the AGC circuit 510 and the filter 512 514 to give time in FIG. 5 to carry out a transition from its resting to its dynamic working state. The third time interval is provided by a stop timer and is approximately 11 milliseconds long. This third one The time interval is the time that, if it is exceeded by a signal absence, is used to to determine a valid termination of the signaling, which is different from discontinuous or interrupted shorter interruptions clearly stands out, which are characteristic of some telephone transmission equipment.

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A more detailed description of the circuit in FIG. 7 now follows. This is connected to the circuit according to FIG. 6 via lines 69? 699 connected, which at the input of a Tonemnfangbuffer 770 end up. The threshold value line 618 according to FIG. 6 is connected to an amplifier 711. The output of amplifier 711 is connected to ground via a voltage divider 712 and to a diode 714a in an analog OR gate. A Voltage divider 713 lies between a positive voltage and earth and has a sliding contact that connects to another Diode 714b in the analog OR gate is connected. the Cathodes of diodes 714a and 714b are connected to the input of one Amplifier 715 connected, the output of which is connected to each of the threshold value inputs of the switch filter 622-629 is.

During operation, the circuit part described so far is used to generate the threshold voltage for the switch filter. Normally the signal level from the voltage divider 713 prevails through the diode 714b and thus determines the output level of the amplifier 715 The highest rectified output signal from the switch filter prevails on the line 618 and determines the output of the amplifier 711 Under very noisy conditions this signal becomes which is fed via the variable resistor 712, thus generating from time to time through the diode 714a currently prevailing uni hdnäurch a dynamic threshold signal at the output of the amplifier 715th

The structure of the rest of the checking circuit will now be considered: a comparator 716 contains inverting and non-inverting inputs which are connected to the output of the amplifier 711 or to a reference level via resistors 718. The reference level is provided on the contact arm of a voltage divider 717 which is between positive voltage and earth . A four-phase clock generator 780 is connected to the system clock generator and contains outputs t - t ,. Each of the digital outputs 692 - 699 of the switch

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filter 622-629 is connected to inputs of audio receiving buffer 770, which has eight outputs connected to eight inputs of a audio receiving register 772. The Tonempfangsregister 772 includes a gate input which is connected to the t ~ _o the output of the clock 780th The sound receiving register 772 contains eight outputs, each of which is connected to a separate input of a read-only memory circuit 773 and a holding register 774. The holding register 77 ¹ + also contains a clear input (CL input) and has eight output lines which are connected to a read selection circuit 779. The read only memory circuit 773 contains four outputs which are connected to a NAND gate 775 and to inputs of a tone marking register 777. The tone marking register 777 also contains a clear input (GL input) and four outputs which are connected to inputs of the read selection circuit 779. The read selection circuit 779 also contains a control input 779a.

The remaining part of the circuit according to FIG. 7 contains various gates and flip-flops. Five JK type flip-flops, a threshold flip-flop 725, a valid data flip-flop 729, a select flip-flop 74-3, a start flip-flop 736, and a data flip-flop 739 for invalid data is used in this embodiment . The structure and function of JK flip-flops are well known, so that from now on all VORSETZ inputs are not shown in this figure, since they are never applied or used during operation. Likewise, only the clear inputs that are applied when the circuit is in operation are shown; and finally, assume that the system clock is connected to the flip-flops and various of the registers and used by these circuit elements in a manner well known to those skilled in the art of digital circuitry. The output of the! Comparator 716 is simultaneously with the inputs of the threshold value flip-flop 725 via an inverter 722 and NOR-

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Gates 721 and 723 connected, each of which has an input connected to the t _Q output of clock 780. The Q output of the Schwellv / ert-Flio-FI003 72 ¹ ^ is connected to the J inputs of the Flio-Fionr, 7? 9 for valid data via NOR gates 72 '+ and 728 and via an inverter 727. The Q output i & £ · is also connected to the J input of the flip-flop 739 for invalid data via the IIOR gate 724 and a NOR gate 738. The NOR gate 72γ also has an input which is connected to one of the outputs of the read-only memory 773. The Q-outputs of the flip-floos 729 and 739 are connected to the inputs of an AND gate 731, the output of which is connected to each of the following gates: to an AND gate 732, to a NAND gate 737 and to a NOR Gate 751 · Both the gate 732 and the gate 751, as well as the NOR gate 742 have an input which is connected to the output of the NAND gate 775. The NOR gate 7 ¹ V ?. has an input which is connected to the t _Q output of the clock 780. In the digital part of the circuit arrangement there are 3 timing circuits, namely an interval timer 74-0, a start timer 753 and an otoop timer 750 · ß. The input of the start timer 733 is connected to the output of the AND gate 732. The interval timer 740 has an input which is connected to the output of the AND gate 731, and an output which is connected to the K input of the selection flip-flop 743 and via an inverter 74-1 to the J input of the selection -Flip-flops 743 is connected. The "^ output of this flip-flop is connected to another input timer start timer 733. The output of the start timer circuit 733 is in communication with the inputs of the start flip-flop 736 via an inverter.

ater ter 75 ^ and NOR gate 735 connected. Each ^v NOR gate 735 has an input connected to the t ^ output of the clock 780. The Q output of the start flip-flop 736 is connected to an input of the NAND gate ?; 737 connected. There

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naohtmoiloh Qmänttft

NAND gate 737 has a further input which is connected to the tp output of clock generator 780 via an inverter 73r. The output of the NAND gate 757 is connected to an input of the NOR gate 738 and the NOR gate 728. The output of the NOR gate 751 is connected to the input of the Stonozeitgeberr »750, the output of which is connected to the set input side of a hold or latch circuit 754 via a NOR gate 753, which has an additional input 753a. The output t- of the clock generator 780 is connected to the reset side of the latch circuit 75'I-. One output of the latch circuit 754- is connected to the clear input of the tone tag register 777, and the other side of the latch 754 is connected to the clear inputs or reset inputs of the Flir> -flops 729, 736 and 7 ^ 9 and to one input of a NAND gate 778 connected. The ^ output of the invalid data flip-flop 7 ^ 9 is connected to one input of a NAND gate 77 * , and an operrlüschlinie a is connected to another input of the NAND gate 77 / . The output of the NAND gate 777 is connected to another input of NAND gate 778, whose output is connected to a clear input of the holding register 77 ^1V. Each of the outputs of NOR gates 720 and 7:58 is connected to a corresponding input of NOR gate 761, the output of which is connected to an input side of a latch circuit 760. The t, output of the clock 780 13t is connected to the other input side of the latch circuit 760. An output of the Verriefplungsschaitung 760 is connected to "input control input or charge control input" 77 f es o -a.

During operation, each of the timers works in the millisecond range, and the associated digital circuitry is turned into the sub-micro-seconds domain by the four-phase clock 780 classified. In this embodiment, each of the

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retroactively

Outputs t _Q - t * applied sequentially for a period of approximately 250 nanoseconds. The existing input states are checked during each sequence in order to determine the state of the system.

For a description of the function of the checking circuit it is assumed that valid signaling frequencies f and f ^ are received. A start interval is determined by the start timer 753, and the effect of the checking circuit during the start interval shall now be examined. If f and f ,. are received, an appropriate indication will appear on two of lines 692-699.

During the time t _Q, the applied output signal t _o and the clock signal CK1 cause the audio receiving register to load and receive the state of the lines 692-699 via the audio receiving buffer 770, respectively. The output of the tone reception register 3 is decoded by the read-only memory 773, which generates an output signal that corresponds to one of its four output lines, which are assigned to the number of occupied inputs: output one applies to one tone or an audible signal, output two for two tones , the output three for three tones, and the output four applies to the case of four or more tones received. The output of NAND gate 775 indicates the presence of any tone. This indication is passed through the AND gate 732 to the start timer 773, if a data element is not already present there, which would be indicated at the output of the AND gate 731. The output of the selection flip-flop 7/3 defines one of two time intervals during which the start timer operates. The selection flip-flop 74-3 follows the state of the interval timer only at the moment in which the output of the NAND gate 775 is not applied. Assuming that the signal level is high enough on the line 618, the threshold flip-flop 725 changes state, by its Q-off gear so applies, that it so the

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Indicates reception of a sufficient signal amplitude. Assuming that the tones persist, nothing further happens until the start timer 733 expires the first time interval in approximately 35 milliseconds. When the tones disappear, the start timer resets to its initial state and the cycle then starts again when the tones reappear. When the output of the start timer 733 goes to its lower state, the start flip-flop 736 changes its state during the time t ^ .. The state of the stop timer 750 is also passed to the latch circuit 754- during the time t *. Since the function of the start timer and the stop timer are mutually exclusive, the stop timer is kept in the inactive state while the start timer is active.

During the next time interval t ₂ , a decision is made as to whether the data element in the tone reception register 772 is valid or invalid. In this case, because it is to be assumed to be valid, the second output of read only memory 773 is low and the output of threshold flip-flop 725 is low, causing the output of NOR gate 724 to be high. When the start timer expires, the Q output of start flip-flop 736 goes low which, in conjunction with the output of inverter 737a, causes the output of NAND gate 737 to go low. This causes the output of NOR gate 728 to go high and to set the Q output of valid data flip-flop 729 high to indicate valid data. When either valid data flip-flop 729 or invalid data flip-flop 739 is set , the output of AND gate 731 goes high, thereby resetting and deactivating start timer 733 via AND gate 732, and to the stop timer 750

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! KLJ

to activate via NOR gate 751, and to cause that the interval timer 740 is reset. The exits NOR gates 728 and 738 cause the output of NOR gate 761 to set the latch 760 deep. When the latch 760 is set, the read select circuit 779 outputs the data either from tone tag register 777 or holding register 774, as indicated by the state of the select read line 779a is determined. During the time t, the latch circuit is on 760 in reset state.

Assuming that the tones are no longer being received, when the tone receiving register 772 is loaded, none of its output lines will be asserted. Thus, none of the lines of the read only memory 773 is asserted and the output of the NAND gate 775 is low. This activates the select flip-flop 743 to follow the output of the interval timer 740. Assuming that interval timer 740 has not expired, its output will be high, causing the Q output of select flip-flop 743 to go high, selecting a shorter time interval of approximately 24.5 milliseconds in start timer 733. The conditions now remain in place until the stop timer 750 times out. During the time interval t ^ the state of the stop timer 750 is passed through the NOR gate 755 to the latch circuit 7 / + 5 . When the stop timer 750 times out, the latch 754 is set, causing the tone tag register 777 to be cleared. The start flip-flop 736, the valid data flip-flop, and the invalid data flip-flop 739 are similarly reset, and the holding register 774 is also cleared via the NAND gate 778. Thus, the output of AND gate 731 goes high, activating start timer 733 and deactivating stop timer 750. V / uh-

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At the end of the stop interval, the duration t ~ is not used, and the time interval t causes the latch circuit 754 is reset.

In the event that the number of tones apparently received is incorrect, i.e. in this representation that one tone or three or more tones have been received, the puncturing manner described above is the same except that the first, third or fourth output line of the read-only memory 773 is created. As a result, the output of NOR gate 724 is low, causing the Output of NOR gate 738 is high and sets register 739 for invalid data. This prevents the holding register 774 receives data from the sound receiving register 772, by applying a continuous clear signal to the clear input of the holding register via gates 774a and 778. So if the data value is not valid, no data value appears at the data output until via the blocking delete line of the input-output circuit arrangement according to FIG. 1 the piercing signal is blocked.

In summary, a universally applicable Emofangs / Transmitters device is obtained by a circuit arrangement, the parameters of which can be set by the data processing unit of a switching device by means of binary data words. A clock signal generator supplies output signals, the corresponding binary command words are assigned, while the parameters of an analog signal receiving circuit through binary control words can be controlled. A variety of switch filters take passband limited analog signals from the receiving circuit and deliver binary output signals as under control of signals from the clock generator

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Indicates that a signal is within a predetermined Passband has been received · To secure both the required command and control words and the Output signals from the filter circuits is a data memory intended. In addition snricht a signal generating circuit to predetermined clock signals so that they in Generates substantial sinusoidal signals, one of which, each has a frequency that is directly proportional to the Imoul repetition frequency of the corresponding clock signal is.

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Claims (1)

PATENT LAWYERS Λ H * i Γ / T O ZYoOh / q MANITZ. FINSTERWALD & GRÄMKOW NORTHERN TELECOM LIMITED Munich, August 5th, 1977 Dorchester Boulevard, West PA / Sv-N 2127 Montreal, Quebec, Ganada H3H 1R1 Receiving transceiver Claims \ Λ.) Receiving transmitting device which is suitable for detecting signaling information of a transmission device in a telephone network and transmitting signaling information from a switching device (10) to the telephone network, the receiving transmitting device having operating parameters which are essentially determined by a set of word commands, and wherein the switching device contains a signal trunk circuit (11, 12) for a connection between the receiving transmitter and a transmission device in the telephone network, characterized in that a clock circuit (23) which has a word memory is provided for generating clock signals, each of which has a pulse repetition frequency has, which is determined by a command word from the switching device and stored at a predetermined location in the word memory that a receiving circuit (30, 31, 35, and 38) with the clock circuit and with the signal 809808/0708 DR. C. MANITZ · DIPU-ING. M. FINSTERWALD DIPL.-INC. W. GRAMKOW ZENTWALKASSE BAYER. PEOPLE β MÖNCHEN 33. ROtERT-KOCH-STRASSE I 7 STUTTGART 50 ISAD CANNSTATTI MÖNCHEN. ACCOUNT NUMBER 7970 TtI. «089» 334311. TELEX OS - 29673 PATMF SEELBERCSTR.3S / 3S.TEL.I07I1I56 73 61 POST CHECK: MÖNCHEN 77Ο63-6Ο & ORIGINAL INSPECT » trunk circuit connected to by the signal trunk circuit To receive multiple frequency signals and the presence of a received signal detect the frequency of which approximately corresponds to the center frequency determined by one of the clock signals, and that a signal generating circuit (45) with the clock circuit and the signal trunk circuit connected to transmit a signal having a frequency which is determined by another one of the clock signals. Receiving transmitting apparatus according to claim 1, characterized in that the pulse repetition frequency is each Clock signal generated by the clock circuit is directly proportional to a predetermined frequency signal multiplied with the value of an assigned command word is in the word memory. Receiving transmission device according to Claim 1, characterized in that there are a plurality in the receiving circuit of filter circuits (639, 640, 641) is arranged so that these, when they are triggered by a control word from the switching device are called, respond in such a way that they only let through those received signals that are within of a pass band, which is determined by the particular arrangement of the filter circuits, and that the Receiving circuitry comprises a plurality of switch filter devices (628, 629) each of which has one analog input (679) which is connected to the plurality of filter circuits in order to filter through the plurality to receive signals passed by filter circuits, and has a control input (378, 379), which is connected to the clock circuit (of FIG. 3) to generate a corresponding one of the plurality of clock signals to receive, each switch filter device having a passband center frequency passing through determines the pulse repetition frequency of the clock signal 809808/0708 original inspectbd and has an output (698, 699) to indicate that that a signal has been received within the passband. 4. receiving transmitter according to Ansoruch 1, characterized in that the signal generating circuit has a Amplitude control circuit (461) having an input (462) for receiving one word of the command words and is responsive to the received word to increase the amplitude of the substantially sinusoidal signal controls. 5. receiving transmitter according to claim 4, characterized in that the amplitude control circuit has a Digital-to-analog converter apparatus (461) comprising generates a voltage in accordance with the word command, and that the signal generating circuit responds to the generated voltage Devices (447, 474, 463, 448) which impart an amplitude to the multiple frequency signal which is proportional to the voltage generated. 6. Clock circuit for generating a clock signal in response on a command word and on a master clock signal, having a predetermined pulse repetition frequency, thereby characterized in that an adding device (310) has first inputs (311) for receiving the command word, η second inputs (341 - 35 °) and η outputs (321 - 330) possesses, and that a bit circulator device has η sections (331-340) which between the η outputs and the η second inputs, and responds to the master clock signal in such a way that that they move bits from the η outputs to the corresponding η second inputs with a delay of the pulse repetition frequency period the master clock signal circulates, whereby the output signal of the section (340), assigned the highest priority is a clock signal with a pulse repetition frequency determined by the Master clock frequency multiplied by the value of the command word divided by n. 809808/0708 Clock generator circuit according to Claim 6, characterized in that the bit circulator device accordingly each section η includes shift register circuits (331-34Ο), each of which comprises a plurality of Has stages and responds to the main clock signal by shifting bits through, and that the clock circuit further includes an output register circuit (360) having inputs and outputs (370-38I) each of which Input is connected to one of the stages in the shift register, which is the section for the highest priority is assigned, wherein the output register represents a circuit which is responsive to a second clock signal which appears a number of times equal to the Pulse Repeat3 frequency of the master clock signal divided by the number corresponds to the plurality of stages in each shift register circuit, so that a plurality of clock signals corresponding to one A plurality of assigned instruction words corresponds to, are generated and at the outputs of the output register circuit appear. 809808/0708