DE2724561C2 - Adaptive equalizer for broadband signals - Google Patents

Description

50

The invention relates to an adaptive equalizer for broadband signals, consisting of a transversal filter, the delay elements, controlled setting elements and a first adder, to the output of which the first input of a differential amplifier is connected, the second input of which is connected to the output of a circuit for generating an ideal signal at the output of which the samples of an ideal comparison signal appear within predetermined time intervals, in which the input of the arrangement is furthermore connected to a first shift register containing a number of N outputs and the output of the differential amplifier to another, a number of at least 2N-1 Outputs containing shift register is connected and in which a further adder is provided, the output of which is connected via a controllable changeover switch to the control inputs of the setting member in such a way that an adaptive setting of the transversal filter is given en is

Such equalizers are the basic concept according to from the magazine NTZ, No. 8 (1974), pages 308 to 312, known this equalizer, however, require analog-to-digital converter for there with x _k _j designated signal. The input signals are also quantized in a two-way exponent code, which can impair the convergence behavior. This convergence behavior is, however, brought about exactly in the invention, as will be described later with reference to equations 9 and 10

Such equalization structures for the automatic and adaptive equalization of linearly distorted signals are for example according to the article "Some methods for adaptive adjustment of equalizers" from NTZ 1971, Issue 1, pages 18 to 24, can be found. For such, for example in Figure 5 on page 21 of the Above-mentioned article, specified equalizer structures built with transversal filters exist different setting criteria, of which, for example, the minimization of the error via a Time range which is larger than the access range of the delay line contained in the transversal filter and the minimization of the mean square error is particularly important here comes to. The continuous multiplication and necessary with such equalizer structures is disadvantageous Integration of the sampled values for the formation of the correlation, in particular if to carry out the individual multiplications are only available for a comparatively short period of time.

The object of the present invention is the automatic Eliminate linear distortion in broadband systems. In particular, a fast equalizer for the Elimination of distortions, for example in PCM transmission or in the transmission of television signals which is the evaluation of a frame impulse transmitted at regular intervals or a test signal transmitted in the gaps in an information signal.

Starting from an adaptive equalizer of the type mentioned in the introduction, this object is achieved according to the invention in that the outputs of the first shift register and the last N outputs of the further shift register with regard to the shift direction are each connected to the two inputs of a number N multipliers, the outputs of which are connected to the N inputs of the further adder are switched.

The particular advantage of the equalization according to the invention is based on the fact that the to form the Correlation required multiplications of the samples can be done slowly. Because the required Sizes that are stored and are therefore available at the same time is a simultaneous one Execution of multiplication possible. It is advantageous in this context that the implementation of the required correlation temporally distributed over the gap between two test pulses and thus can be carried out simultaneously with the actual signal transmission.

The invention is explained in more detail below with the aid of exemplary embodiments.

It shows in the drawing

F i g. 1 a known equalizer circuit containing a transversal filter,

2 shows an adaptive equalizer according to the invention

manure,

F i g. 3 shows a matrix representation of the computation process of the arrangement according to FIG. 2.

In Fig. I the structure is given of an adaptive equalizer which includes a transversal filter, the transversal filter includes a delay line VL to each of the delay time T corresponding delay elements not specifically shown, which are each provided with a tap, each tap is in turn connected to an evaluation element Q , for example a controlled setting element, the output of which is in turn connected to one of the inputs of a first summer SU 1.

The transversal filter is called the essential property, that it is the realization of an impulse response or transfer function that is arbitrary within wide limits It delivers as an output variable

Λ = Σ ^c J ' ^x kj

(D where the c "represent the variable parameters (values of the setting elements) of the transversal filter. Equation (1) applies accordingly to the transversal filter with the input signals x _k at the center tap and the output signals y _k.
With

e _k = y _k ~ a _k , (4)

ίο a _k = ideal, correct value (e.g. sample value of the desired equalized impulse response, stored on the receiving end)

will

M j = -.M

and

-r- = lim -
ο c " _K ^" K

e _k -x _k . _n .

Here means:

the sampled signal appearing at input E of the transversal filter

the weighting factors for weighting the signals

the sampled output signal.

The output of the first summer SU 1 is connected to the first input of a differential amplifier D, is present at the second input of an ideal reference signal at the output of differential amplifier D then passes the error signal e _k, which is used as a criterion for the setting of the controlled adjustment members using

The requirement for the simplest possible automatic equalizer setting can always be met particularly easily if the output signal y (t) of the equalizer can be represented as a sum of weighted partial signals x / t) . This is the case with the present transversal filter structure. In the following it is always assumed that the received signals are frequency band limited. It is therefore sufficient to sample the signal at discrete points in time and to process these sample values further. To achieve an automatic equalizer setting, it is necessary to provide estimated values for the samples of the correct? derived ideal signal a (t) . The signal yk thus has the form shown in equation (1)

To minimize the error over a time range which is greater than the access range of the delay line contained in the transversal equalizer, the minimization of the mean square error e _k ² can be used as a criterion. This results in the following expression: A cross-correlation is therefore required to determine this derivative. A disadvantage for the implementation is the difficulty of the instrumentation of threshold correctors.

The x _k _ "are available at the taps of the delay line for jointing, e _k is formed according to equation (5).
In order to reduce E , we now use

- Λ

respectively.

_c (m + l) _

T cJ

So there is an iterative setting in the direction of the gradient. All adjustment members will be changed gradually at the same time and in parallel.

In principle, e ² does not need to be minimized, but the mean value of another suitable function of the error can be considered. (However, because of the termination error caused by the finite length of the transversal equalizer, a different choice of function usually also leads to a different final setting of the equalizer.) For example, it has proven to be well suited

with

SE * _ .. 1

_k - _n ■ sign «· *.

(9)

(10)

E = Hm - Σ β- (2)

In order for this expression to disappear, the following must apply:

A variant of the method according to equation 10 is already known from the article "Automatic equalization for digital communication" by RW Lucky, published on pages 547 to 58rf of the publication "Bell System Technical Journal", 44 from April 1965. Here is a first test pulse and sent to the ^Empfangsse: te the signs of the errors are determined and stored in a shift register. This changes the sign of the signal at each tap of the transversal equalizer when it is switched on

rated or not switching on an inverter. All Taps evaluated in this way are combined at a summer. Will now be a second test pulse are transmitted, the signals appear one after the other at the output of this adder

Σ.ϊΑ-ί · signe,

for y = -M ... + M. These values can be used to change the variable setting elements of the transversal filter. The setting elements should contain an evaluation element, for example a potentiometer with a switchable inverter, as well as a memory for temporarily storing the respective manipulated variable, for example a control voltage which determines the size of the evaluation factor. The stored manipulated variable is changed step by step in the correct direction until the optimal setting is reached. The results of the correlation must be temporarily stored for further processing, and a measurement cycle requires two test pulses.

In Fig. 2 the circuit of an adaptive equalizer according to the invention is shown schematically. The transversal filter, in accordance with the arrangement according to FIG. 1, consists of a delay line VL connected on the input side to the input E of the arrangement with individual delay elements, the outputs of which are connected to the inputs of a first summer SU 1 via controlled setting elements C with the variable parameters c . The output of the first summer is simultaneously connected to the output A of the arrangement and to the first input of a differential amplifier D , to whose other input the output of a circuit (not shown in the figure) for generating the samples a, an ideal signal a (t) is. The lsigna! Bi an i

idealsigna

! Bi a test signal which is inserted into the signal to be transmitted in certain Zc; iabsiärsde "send side, which is known on the receiving side and is therefore stored, for example, in the form of sample values and in the differential amplifier D subtracted. at the output of the differential amplifier D then passes the error signal et.

The input E of the arrangement is connected to a first shift register 51 which has a number yv delay elements and accordingly a number N outputs. The output of the differential amplifier D is connected to a further shift register 52 having at least a number of 2 / V-1 outputs. The outputs of the first shift register Si used to store the x values are connected via latches ZX to the first inputs of a number N multipliers M _x to My , the outputs of which are in turn connected to the inputs of a second adder SLJ 2 . The second inputs of the multipliers M are connected via latches Z 2 to the last N outputs of the second shift register 52 with regard to the shift direction. Both shift registers and the buffers are clocked together via a clock center TZ, shown schematically in the figure, and clock lines TL i... TL 4. The output of the second summer SU 2 is connected via a controllable changeover switch U to the control inputs of the setting elements of the transversal filter, not shown in the figure for reasons of clarity, in such a way that adaptive setting of the transversal filter is ensured.

The samples Xi X2 ... of the distorted test pulse response is written with the aid of a Tastpulsfolge on line TL 1 in the X memory 51st Likewise, the output signals e * with the help of another pulse sequence from the clock center, which is delivered via the clock line TL 4, in the

to £ "memory 52. Since an equalizer with N taps supplies 2N samples of the output impulse response as a response to an incoming impulse response with N samples not equal to zero, the sequence et 2Λ / samples Φ0 . 52 must therefore be twice as long as 5 1 have.

When the sampled values e * and χι are in the registers 5 1 and 52, they are converted into the scanning circle circles with the help of a command pulse supplied via the TL 2 line! Cache

> o Zi and Z2 accepted and saved for further processing.

With the help of shift pulses on the clock line TL 3, the signal in the buffer Z 2 can be slowly pushed further to the left.

An alternative solution, not shown here, consists in continuously reading the ** and e * values into the X and ^ memories 51 and 52 and transferring them to the correct one. To initiate a read-out into the buffers Zi and Z 2 in moments of time by command pulses. It is then advantageous to design the buffers as a series connection of two different sample and hold circuits, of which the first has a short hold and charge time constant and the second, in contrast, has relatively long hold and charge time constants. A sample and hold circuit is able to store a sampled amplitude value over a predetermined time. Such circuits are z. B. known in connection with A / D converters, for example from DE-AS 19 31 242.

While the storage of the digital signals is not a particular problem, the storage creates of the analog values therefore difficulties, since the stored signal for further processing should be as constant as possible. This requires a large hold time constant. The loading time constant should therefore be as short as possible, because the signal in the delay line of the transversal filter after a short period of time already changes again In order to meet these requirements, the storage be carried out in two steps, in such a way that in each case two different sampling HaiteKkreises can be connected in series, the first of which is a short one with a view to precise sampling The hold time constant only needs to be sufficient to enable the second sample and hold circuit to offer a signal that changes only slightly during its work phase. The hold time constant of the second sample and hold circuit can then be sufficiently long.

It is particularly advantageous to design the shift register 52 as a digital shift register and to process only the signs of the error values e *, as was expressed in equation (10). The buffer memory Z2 can then be dispensed with, since a digital shift register can store information that has been written in for any length of time. The signals sign e _ + ... sign e * then appear at the outputs of the shift register 52.

It should be pointed out that the insertion of buffers was only provided for the reasons already mentioned. If memories are used for 51 and 52, which on the one hand allow quick storage and on the other hand a long storage time, for example when designed as a pure digital memory with previous A / D conversion of the input signals, the intermediate memories Z 1 and Z 2 can be omitted.

Once they have been saved, the samples are processed. The following is an example of five Taps and an input impulse response with five samples *** <) considered with reference to FIG will. The result here is an output impulse response with nine values y * # 0. So there are nine samples e * on. The required arithmetic process can be most easily carried out using a matrix representation in accordance with Fig. 3 show.

the first step is the big one

20th

Σ ^X "* l

educated. This is fed as a correction value for c- ₂ via the changeover switch U to the corresponding setting element. Then with the help of a clock pulse on the line 7X3, the information in the buffer Zl is moved one cell to the left.

pushed. It can then change the size

To x _n + \

formed at the output of the summer SUl and fed via the switch i / to the setting element c_i. Subsequently, the buffer Zl is again switched on, and the size becomes

»■ 2

Σ -ν,

η - -2

■ e "

made to control cq.

This process continues until all adjustment elements have been changed.

After receiving the next test signal, the described process is repeated.

This results in a continuous automatic readjustment of the equalizer in terms of achievement smallest, mean square filter in the received test signal. The test signal is representative of the to select the remaining signal content to be equalized.

The entire period is used to calculate the correction values for the adjustment elements available between two test signals.

For this purpose 2 sheets of drawings

Claims (4)

Patent claims: 1. Adaptive equalizer for broadband signals, consisting of a transversal filter, the delay elements, controlled setting elements and a first summer, at the output of which the first input of a differential amplifier is connected, the second input of which is connected to the output of a circuit for generating an Ό ideal signal , at the output of which the samples of an ideal comparison signal occur within predetermined time intervals, in which the input of the arrangement is also connected to a first shift register containing a number of N outputs and the output of the differential amplifier to a further, a number of at least 2N- 1 outputs containing shift register is connected and in which a further adder is provided, the ²⁰ output of which is connected via a controllable changeover switch to the control inputs of the setting member in such a way that an adaptive setting of the transversal filter is given, marked thereby eichnet that the outputs of the first shift register (S 1) and the last N outputs of the further shift register (S 2) with regard to the shift direction are each connected to the two inputs of a number of N multipliers (M) , the outputs of which are also connected to the N inputs Summing (SU 2) are switched. 2. Adapliver equalizer natOi claim 1, characterized in that the further shift register (S2) is designed as a digital shift register. 3. Adaptive equalizer according to claim 1, characterized in that the shift registers (S 1,52) are designed as analog and / or digital shift registers, and that the shift registers (51, 52) are provided with downstream buffers (Zl, Z 2) . 4. Adaptive equalizer according to claim 3, characterized in that the analog buffers are designed as a series connection of two different sample and hold circuits, of which the first short hold time and charge time constant «5 and the second has long hold time and charge time constants.