DE2718175A1 - Scan holding circuit for phase discriminator - has generating circuit separated from holding capacitor by three switches reducing interference to min. - Google Patents

Abstract

The circuit generates a saw-tooth voltage with phase and period equal to those of a reference voltage. The sawtooth generator can be connected to a holding capacitor through two switches connected in series. They are made conducting or blocked depending on the phase difference between the reference voltage and a further voltage of the same frequency. The capacitor is followed by an amplifier with high input impedance, pref. a voltage follower. In order to reduce interferences from the reference voltage (S2) to the scanning holding circuit (3) output signal (Um) the two switches (K1, K2) are always switched together. A third switch (K3) is controlled, by a switching signal (S2) complementary to the switching signal (S2) so that the holding capacitor (CH) is to the highest degree screened from the a.c. voltage component passing through the blocked switch (K1). In order to shorten transient processes capacitance of the capacitor (CH) is small in comparison with that of capacitor (C1) generating the saw-tooth voltage.

Description

"Sample and hold circuit"

The invention relates to a sample and hold circuit, in particular for a phase discriminator, with means for generating a sawtooth voltage with respect to a reference voltage of the same period and phase, said means via a series connection of a first and a second switch, which by means of a Switching signal according to the phase difference between the reference voltage and another voltage with the same frequency is switched through or blocked can be connected to a holding capacitor to which an amplifier with high Input resistance - preferably a voltage follower - is connected downstream. the The invention also relates to a sample-and-hold circuit for sampling the amplitude of voltages with any time course using a series connection from a first and second switch, which with the aid of a sampling switching signal selectable frequency can be blocked or switched to a holding capacitor, an amplifier with high input resistance - preferably a voltage follower - downstream is A phase discriminator of the type mentioned is, for example with arrangements for frequency processing for Send and receive purposes needed. Such an arrangement is e.g. B. shown in Fig. 1. she consists from a highly constant crystal oscillator 1 with frequency fq, signal via a frequency divider 2 is fed to a phase discriminator 3 with a division factor M as reference signal S1 will. The output signal Um of the phase discriminator 3 is passed through a low-pass filter 4 a voltage-controlled oscillator 5 (a so-called VCO) fed as a control variable. The frequency f = f. MM of the voltage controlled oscillator 5 uird by means of a The control loop is kept at the desired value in such a way as its output signal via a frequency divider 6 with a divider factor that can be set via a programming input ó ' N is supplied as voltage S2 to the phase discriminator 3, in which this with respect to their phase position is compared with aem their reference signal S1 of the same frequency. The invention relates to a sample-and-hold circuit, particularly in such a Phase discriminator 3 can be used with advantage. The phase discriminator 3 supplies an analog output signal Um, which is the phase difference between its two input signals S @ and S @ is directly proportional.

The ideal phase discriminator, which does not exist, delivers as The output signal is a pure equilibrium voltage, which - as mentioned - the phase difference is proportional to the two input voltages. A sudden change the phase difference occurs immediately at its output, i.e. H.

without a time delay, a corresponding jump in the output variable.

The real phase detector, on the other hand, is more or less imperfect. Its output signal appears with a delay. Except the desired DC voltage it still contains unwanted components of the two input signals and their harmonics.

In an arrangement for frequency processing, these are effective Remnants of the input signals are very detrimental, since the output signal is frequency processing then modulated with these signals, causing a significant deterioration in the the spectral purity of the output signal of the frequency processing. This interference modulation can be reduced by reducing the cutoff frequency of the lowered to the low-pass filter following the phase discriminator. The> ls trings, however with the disadvantage that the control loop then becomes very slow. A quick one Changing the frequency by changing the division factor N is then no longer possible. In the case of radios with automatic channel selection, a quick frequency change is required but inevitable.

The required speed and spectral purity can be found on the most likely with a sample-and-hold phase discriminator, i. H. a phase discriminator with a sample-and-hold circuit as an integral part.

A phase discriminator of this type is already known to be used in Fig. 2 is shown and will be discussed in more detail later. Such a phase discriminator is fast (with correct dimensioning of the switching elements), disadvantageously However, the two input signals appear here as an interfering signal at the output, because their amplitudes - based on the value on the input side - only attenuated by up to 60 dB are.

Furthermore, a sample-and-hold phase discriminator is already known, which is shown in Fig. 4 and which will be explained in more detail later. This phase discriminator is about 20 dB better than the signal-to-noise ratio of its output signal that of FIG. 2. Because of the intermediate storage of the sampled amplitude however, this phase discriminator is too slow.

The invention is based on the object of a sample-and-hold circuit of the type mentioned in particular for phase discriminators, but also for the sampling of the At3pLitude of voltages with any time course sharp, on the one hand an output signal with the highest possible spectral purity delivers and which, on the other hand, is also as quick as possible Sample-and-hold circuit for phase discriminators achieved according to the invention in that that to increase the signal-to-noise ratio of the output signal of the sampling ilalte circuit in relation to the reference voltage and the switching signal, the first and second switches are always switched through or blocked together and a third switch is provided, which is arranged in such a way and which by means of a to the switching signal complementary switching signal complementary in time to the first and second switch switched through or blocked in such a way that the holding capacitor is largely of the AC voltage components that pass the first switch in the blocked state is shielded, and that to reduce the settling time also the capacitance of the holding capacitor is small compared to the capacitance of a capacitor for the Generation of the sawtooth voltage is selected.

An advantageous embodiment of this solution consists in that the capacitor for the generation of the sawtooth voltage by means of a constant current source loaded and via a fourth switch connected in parallel to it in accordance with the Reference voltage is discharged periodically.

A particularly preferred one because it increases the signal-to-noise ratio of the output signal with respect to the switching signal is an important embodiment given by the first to third switches and, if applicable also the fourth switch as a complementary C-MOS switch a p-channel and an n-channel NOS transistor are formed and that the first and second switch with the switching signal, the third switch with the complementary one Switching signal and the fourth switch applied to the reference signal in the way are, the p-channel and the n-channel M0S transistor of the switch are each in phase opposition are controlled, whereby the anti-phase control signals at the switch output just compensate With a scanning lialte circuit for scanning the amplitude of tensions with any time course becomes the underlying task solved according to the invention in that the voltage to be sampled is said series circuit from the first and second switch can be supplied that the first and second switch are always blocked or switched through by the sampling switching signal, where in the latter case the current amplitude of the voltage to be sampled in the holding capacitor, that an additional third switch is stored is provided, which is arranged in such a way and which with the aid of a to the sampling switching signal complementary switching signal complementary in time to the first and second The switch can be blocked or switched through such that the holding capacitor largely from the alternating voltage components passing through the first switch in the blocked state is shielded, and that the capacitance of the holding capacitor is selected to be as small as possible is.

To increase the signal-to-noise ratio of the output signal with respect to the Sampling switching signal is an embodiment of importance, which is characterized by this is that the first to third switches are each constructed as a complementary C-MOS switch with a p-channel and an n-channel MOS transistor educated are and that the first and second switch with the sampling switching signal and the third Switches with the complementary switching signal are applied in such a way that the p-channel and n-channel MOS transistors of the switch are each driven in phase opposition are such that the antiphase control signals are at the switch output just compensate.

A preferred embodiment of the invention is shown in the drawing and is explained in more detail below.

Fig. 2 shows a known sample-and-hold phase discriminator 3, the as input signals a reference signal So and a switching signal S2 of the same frequency can be fed in and the output signal Um can be removed at the output. The temporal The course of the signals S1, S2 and Um is shown in Fig. 3 as a voltage curve U (t) over the Time t plotted. The phase discriminator 3 has a field effect transistor as a switch T, which is controlled directly by the pulse-shaped switching signal S2 (scanning signal) will. The sawtooth-shaped reference signal S1 is fed to the switch for scanning. The switch T is followed by a holding capacitor CH, which is connected to the respective Sampling is applied. The voltage at the holding capacitor C.f is via a Amplifier designed as a voltage follower SF lait high input resistance given the output of the phase discriminator 3. The input resistance of the voltage follower SF is chosen to be so large that the voltage across the holding capacitor CH between the individual Queries (scans) remain constant (a charge withdrawal by the voltage follower Otherwise the result would be that the output signal would be an interference voltage of the frequency of the appears on both input signals). Let us now consider the case that between the There is no phase difference between signals S1 and S2. In the illustration in FIG. 3 would then be the narrow one Interrogation pulse S2 with the beginning of the sawtooth-shaped Reference signal S1 coincide. The switch T is called c very briefly at a time switched through, at which the reference signal S1 just has the voltage value zero. The holding capacitor CH then stores the sample value until the next interrogation Zero and passes this on to the output via the voltage follower SF. So long the phase difference NuLl remains, every query results in the value zero, i.e. H. the output voltage Un of the phase discriminator 3 is then equal to zero. Changes If the phase difference suddenly changes to a value not equal to zero, the subsequent interrogation of the holding capacitor on the one corresponding to this phase difference Voltage value of the reference signal S, charged. How large is the number m of this necessary interrogation is (see. Fig. 7), ht vcn the pulse width of the Schaltsidgnals S2, the internal resistance of the source of the reference signal S1 and the capacitance of the holding capacitor CH. The pulse width of the switching signal S2 is as small as possible selected because during the pulse of the @gezahnformige reference signal S1 on the output of the phase discriminator 3 is switched on (interference voltage). The sample-and-hold phase discriminator according to Figure 2 is true - provided that the switching elements are correctly dimensioned -fast, a major disadvantage with him, however, is the fact that the Both input signals S1 and S, a's interference signal appear at the output, as their output amplitudes based on the input amplitudes are only attenuated by up to 69 dB. An improvement the damping is essentially opposed to two facts. For one thing, it's that Capacitance C of the blocked switch transistor T and, on the other hand, a capacitance CS2 of the same transistor, via which the reference signal S1 and the switching signal S2 get to the holding capacitor CH.

Fig. 4 shows another known sample-and-hold phase discriminator 3, which differs from that of FIG. 2 in that it has two switches connected in series in the form of a first and a second Field effect transistors T1 and T2 are provided, between which a buffer -Capacitor Cz is connected in parallel to the holding capacitor CH. The first field effect transistor T1 is from dt switching signal S2 directly, the second field effect transistor to an inverter I controlled in such a way that both switches are never switched through at the same time rather, they are alternately switched through or blocked. Clt is achieved that the input signal S1 at no time directly on the holding capacitor CH is switched through, whereby the signal-to-noise ratio of the output voltage compared to the The signal-to-noise ratio of the phase discriminator according to FIG. 2 is increased by about 20 dB. The capacitance C 'or C' 'of the respective blocked field effect transistor T1 or T2 interferes, however, because it is the reference signal 5 on the holding capacitor CH and arrives at the output of the phase discriminator. Also the disturbing influence the gate-drain capacitance C '' 'of the field effect transistor T2 remains over which the inverted switching signal S2 is coupled to the holding capacitor CH Phase discriminator according to FIG. 4 has compared to dt.ijeni gene according to FIG the advantage of higher interference suppression through the use of the intermediate storage capacitor Cz, however, it is much slower than the latter.

5 shows a sample-and-hold phase discriminator according to the invention 3, which has the advantages of the two aforementioned phase discriminators Avoiding their disadvantages united.

It contains a constant current source KS, which has a capacitor C to Generating a sawtooth voltage u1 feeds. To generate the sawtooth voltage U1 the capacitor C1 is periodically in time with the reference signal S1 via one of the reference signal controlled switch K4 discharged. The temporal connection between the sawtooth voltage U1 and the reference signal is in the upper two Diagrams shown in Fig. 6.

Reference signal Si and sawtooth voltage U1 have the same period duration.

The beginning of the sawtooth pulse always coincides with a pulse of the reference signal S1 together. It is important that the - as in the phase discriminator according to FIG. 4 - in Series-connected switches K1 and K2 in contrast to the arrangement according to FIG. 4 of the switching signal S2 are always switched through and blocked together and that between the two switches K1 and K2 in contrast to the arrangement according to FIG. 4 a switch K3 is arranged instead of the intermediate storage capacitor CZ, that of a switching signal S2 complementary to the switching signal S2 is complementary in time to the two switches K1 and K2 is switched through and blocked so that the Switches K1 and Ko are each blocked when switch K3 is switched through is, and vice versa, the switching signal S2 for the switches K and K2 and the complementary Switching signal 5 for switch K are shown in FIG. 6 in the third and fourth diagram shown from above. as can be seen from Fig. 6, the switches K1 and Ko are through the switching signal S2 at a point in time which is the phase difference between the signals St and S2 corresponds, briefly switched through, in which case switch K3 is straight is blocked by the complementary switching signal S2, so that in that, the pulse width of the switching signal S2 corresponding period of the holding capacitor CH through the Sawtooth voltage U1 1 to the voltage value corresponding to the respective phase difference is charged and the associated voltage at the output of the phase discriminator U appears. When switches m K1 and K2 are blocked, switch K3 is straight switched through, whereby the holding capacitor CH largely from the the switch K1 is shielded in the blocked state passing AC voltage components. With a suitable choice of the capacitance ratio C1 / CH - the capacitance of the holding capacitor CH should be compared to the capacitance of capacitor C1 for sawtooth generation be chosen as small as possible - and sufficiently small time constant of the circuit consisting of the sum of the forward resistances of the (switched through) Switches K1 and K2 and the holding capacitor CH is that of the current phase difference received voltage value To practically already reached after a query.

The interference capacitances CK1 and CK2 of the blocked switches K1 and K2 no longer have a negative effect, because the switch K3 is switched on Transfer of the sawtooth voltage U1 to the holding capacitor CH is prevented. Effective all that remains is the interference capacitance CK12 of the entire series connection of the (blocked) Switches K1 and K2, the amount of which is so small that it has almost no effect on the signal-to-noise ratio remains important is the fact that a 1 s switch K1 to K4 preferably used C-MOS switches - to which later in connection 8, the switching signal S2 (or the complementary switching signal S2) as a result of the antiphase control of the p-channel and n-channel MOS transistors of the C-MOS switch at the switch gate no longer appears. With the invention @@@ t-hold circuit can be a suppression of the signals S (or U1) and S2 of 90 dB. To a sudden change in the phase difference between the input signals and S2 practically follows already after a query, d?.

after a sampling, the associated voltage value Um at the output of the Phase discriminator.

If the sample-and-hold circuit according to the invention is not intended for a phase discriminator, but generally for the purpose of sampling the amplitude of voltages with any are used over time, there is no need to generate the sawtooth voltage U1 directed part of the arrangement and the voltage to be sampled is - instead of the Sawtooth voltage U1 - fed directly to the circuit of switches K1 and K2, The frequency of the sampling switching signal S2 can then be freely selected (for example according to the sampling theorem).

As already mentioned, in the sample-and-hold circuit according to the invention, in the event of a sudden change in the phase difference between the two input signals S1 and S2, the associated voltage value Um at the output of the phase discriminator is practically reached after a query. 7 shows the ratio of the output voltage Um after the m-th query and the output voltage U # near an infinite number of queries as a function of the number m of queries. There is an asymptotic approximation of Um to U # with increasing m The ratio Um / U # can be expressed as a function of the number m by the following formula: where C @ is the capacitance of the holding capacitor and C1 is the capacitance of the capacitor for sawtooth generation. Her formula shows that the (approximately) correct value of the output voltage Um is reached faster, ie with um for fewer queries, the smaller the capacitance of the holding capacitor is selected compared to that of the capacitor for sawtooth generation.

Fig. 8 shows an example of one preferably used as a switch K1 i K4 used C-MOS switch with an input E, an output A and an input S for the switching signal The switch has a p-channel and an n-channel MOS transistor on. The n-channel MOS transistor is driven directly by the switching signal while the p-channel MOS transistor from the switching signal inverted by means of an inverter I, d. H. in phase opposition to the n-channel MOS transistor. Consequently delete the overcoupling over the capacities C and C of the transistor stops Voltages (switching signal and inverted switching signal) are mutually exclusive, so that the switching signal S does not appear at the output A of the switch.

Leeward

Claims (5)

Claims sample-and-hold circuit in particular for a phase discriminator, with means for generating a sawtooth voltage ilt compared to a reference voltage same period and phase, said means via a series connection of a. first and second switch, which by means of a switching signal in accordance with the phase difference between the reference voltage and a further voltage with the same frequency switched through or blocked, can be connected to a holding capacitor, de. an amplifier ait high. Input resistance - preferably a voltage follower - is connected downstream, characterized in that to increase the signal-to-noise ratio of the output signal (Um) of the sample-and-hold circuit (i) in relation to the reference voltage (S1) and the switching signal (S2) the first and second switches (K1 and K2) always together are switched through or blocked and a third switch (K3) is provided for this purpose which is arranged in the manner and the means of a switching signal to dea (S2) complementary switching signal (S0) complementary in time to the first and second Switches (K1 and K2) switched through resp. It is blocked in such a way that the holding capacitor (CH) largely from the first switch (K1) passing in the locked state AC voltage components is shielded, and that to reduce the settling time In addition, the capacitance of the holding capacitor (CH) is small compared to the capacitance a capacitor (C1) is selected to generate the sawtooth voltage (Fig 5 and 6). 2. sample-and-hold circuit according to claim 1, characterized in that that the capacitor (C1) for the generation of the sawtooth voltage by means of a constant current source (KS) loaded and via a fourth switch (K4) connected in parallel to it Depending on the reference voltage (S1) is discharged periodically (Fig. 5 and 6). 3. sample-and-hold circuit according to claim 1 or 2, characterized in that the first to third switches (K1 to K3) and possibly also the fourth Switch (K4) each as a complementary C-MOS switch with a p-channel and one. n-channel MOS transistor are formed and that the first and second switches <1i and K2> with the switching signal of the third switch (x3) with the complementary one Switching signal (S2) and the fourth switch (K4) with the reference signal (S1) in the Way are acted upon that the p-channel and the n-channel MOS transistor of the switch each driven in phase opposition are such that the switch output Compensate out-of-phase control signals (Fig. 5 and 8). 4. Abstat-Halt circuit for sampling the amplitude of voltages with any time course using a series connection of one first and second switch, which can be selected with the aid of a sampling switching signal Frequency can be blocked or switched through to a holding capacitor, the one Amplifier with high input resistance - preferably a voltage follower - connected downstream is, characterized in that covering the voltage to be scanned ter series connection of the first and second switch (K1 and 12) can be supplied that the first and second switches (K, and K2) by the sampling switching signal (S2) always are blocked or switched through together, in the latter case the straight current amplitude of the voltage to be sampled is stored in the holding capacitor (CH), that in addition a third switch (K3) is provided, which is arranged in this way and with the aid of a switching signal complementary to the sampling switching signal (S2) (S2) complementary in time to the first and second switches (11 and K2) lockable or can be switched through in such a way that the holding capacitor (CH) is largely of the alternating voltage components passing through the first switch (K) in the blocked state is shielded, and that the capacitance of the holding capacitor (CH) is as small as possible is selected (Figs. 5 and 6). 5. sample-and-hold circuit according to claim 4, characterized in that that the first to third switches (K1 to K3) each have a complementary structure C-MOS switches are formed with a p-channel and an n-channel MOS transistor and that the first and second switches (K1 and K2) with the sampling switching signal (S2) and the third switch (K3) with the complementary switching signal (S2) in the manner are applied that the p-channel and the n-channel MOS transistor of the switch are each driven in phase opposition such that the switch output Compensate out-of-phase control signals (Fig. 5 and 8).