DE1053569B - Arrangement for demodulating phase-modulated pulses - Google Patents

Description

The invention relates to an arrangement for demodulating phase-modulated pulses which a capacitor is charged via a directional conductor during the pulse duration. The condenser is discharged during the pulse pauses, the discharge being caused by a charge reversal takes place via a resistor. This creates a sawtooth voltage. This is on the back flanks sampled by equidistant pulses, and the sampled voltage values are in one Capacitor stored.

Such facilities are known for the purpose of multi-channel message transmission (cf. German Patent 954,518). With this known type of demodulation, the sampled discharge characteristics should of the capacitor have as linear a course as possible. This is achieved in that the capacitor after being charged by a voltage of opposite polarity across a resistor is reloaded. The sampling then only takes place in the partial range of the characteristic that approximates one has to show a linear course. This makes it possible to change the modulation content of the demodulate phase-modulated pulses with almost no distortion.

In this known arrangement, the task (see. German Patent 739 806), the scanned To keep the capacitor and the storage capacitor galvanically separated during the sampling time. This is to prevent the storage capacitor from changing the discharge characteristic during charge exchange of the sampled capacitor affected. In a known way, this task is carried out solved an electron tube, which is arranged between the two capacitors. While the tension values of the sampled capacitor are fed to the grid of the tube stage, this causes the Control of the anode circuit that controls the increase or decrease in the amount stored in the storage capacitor Brings about charge. The known design of a demodulator therefore requires the effort of a Intermediate stage, which is arranged between the two capacitors. Since the intermediate stage through non-linear terms are formed, there is the disadvantage of an increased distortion factor,

The invention avoids this disadvantage by removing the capacitors through the sampling are connected in parallel and their charge equalization is effected, the capacitance of the scanned Capacitor is greater than the capacity of the storage capacitor.

Due to this special measure, it is no longer necessary to arrange an intermediate stage between the two capacitors. The cost arrangement for demodulation
of phase modulated pulses

Applicant:

Telefunken G. mb H.,
BerHn NW 87, Sickingenstr. 71

Helmut Oberbeck, Backnang (Württ.),
has been named as the inventor

This reduces the cost of the system and improves the transmission quality.

An exemplary embodiment of the invention is described with reference to the drawings.

Fig. 1 shows the circuit structure of the demodulator. The incoming phase-modulated pulses U _p are fed to terminals 1, 2 , and the demodulated voltage U _nf is derived at terminals 3, 4. In the idle state of the arrangement, a circuit is formed by the voltage U _b via the high resistance R and the diode D _2. The capacitor C ₁ is thus short-circuited by the diode D _2. It is assumed that the message pulses are fed to terminal 1 with negative polarity. When a pulse arrives, diode D ₁ becomes conductive and diode D ₂ receives blocking potential. The capacitor C ₁ is negatively charged by the phase-modulated pulse U _p. When the trailing edge of the pulse arrives, the diode D _{1 is} blocked and the charging of the capacitor C ₁ is ended. From this point in time on, there is an adestronic circuit for the capacitor C ₁ from the negative voltage U _p across the high resistance R. When the charge is reversed, only the lowest linear part of the characteristic is run through until the voltage on the capacitor C _{1 reaches} the value zero. When the voltage on the capacitor C ₁ exceeds the zero value in the positive direction, the diode D ₂ conducts current again and the charge reversal of the capacitor is interrupted. This process produces a sawtooth voltage with an almost linear trailing edge on capacitor C _1. The voltage curve across the capacitor C ₁ is shown in the upper part of FIG.

The sawing voltages occurring at the capacitor C ₁ change their temporal position according to the phase position of the supplied message pulses. Demented

809 787/384

Claims (3)

In other words, the linear trailing edge of the Draieck pulses is also shifted in parallel with the modulated message frequency, so that different voltage values occur at the capacitor C1 at the same time intervals. These voltage values, which represent the modulation content of the transmitted message, are scanned by the switch. The scanning takes place periodically and equidistantly. Each time the switch S is closed, the amplitude values of the communication voltage sampled at the capacitor C1 are transmitted to the capacitor C2 and stored there until the next sampling. In this way, the step-shaped communication voltage is created at the capacitor C2. The switch 6 ″ can be designed as an electronic switch which is controlled by equidistant pulses Ut, which are derived from the sync pulse of a multi-channel transmission. The capacitor C2 should not influence the discharge characteristics of the capacitor C1 during sampling. This is avoided if possible, in which the capacitance of the capacitor C1 is dimensioned significantly larger than that of the capacitor C2. In a practical embodiment, the ratio of the two capacitors can assume the value 1:10. FIG. 2 contains the various pulse diagrams 2b shows the triangular pulses occurring at the capacitor C1 with the voltage Uc. During the pulse duration t1, the capacitor C1 is charged and discharged during the time period t3. The charge reversal of the capacitor, which is limited by the diode D2, results in the discharge time T3, which is always shorter zer as the shortest time interval τ2 that is possible between two successive message pulses. A mutual influencing of the message impulses can therefore not occur. In FIG. 2 c, the probe pulses Ut are shown, which follow one another equidistantly with the time intervals T. During the sampling times t4, the voltage Uc present at the capacitor C1 is sampled. During these times, there is an exchange of charge between the two capacitors C1 and C2. The higher the ratio C1: C2 of the two capacitances, the less charge can flow from the capacitor C1 to the capacitor C2 during the sampling time ti, whereby the trailing edge of the pulses shown in FIG. 2b is also less influenced. It should also be mentioned that the invention can also be used with the same mode of operation in the case of phase-modulated pulses with positive polarity. For this purpose, the polarity of the diodes Dv D2 and the voltage UB would have to be reversed. Patent claims: 1. Arrangement for the demodulation of phase-modulated pulses, in which a capacitor is charged during the pulse duration via a directional conductor and discharged during the pulse pause, the capacitor being discharged by a charge reversal via a resistor, creating a sawtooth voltage, the trailing edges of which are caused by equidistant pulses sampled and the sampled voltage values are stored in a capacitor, characterized in that the capacitors (C ₁ , C ₂ ) are connected in parallel by the sampling and their charge compensation is effected, the capacitance of the sampled capacitor (C ₁ ) being greater than that Capacity of the storage capacitor (C ₂ ). 2. Arrangement according to claim 1, characterized in that the capacitor (C ₁ ) is charged by the phase-modulated pulses via a diode (D ₁ ). 3. Arrangement according to claims 1 and 2, characterized in that a Rlchtleiter (D ₂ ) is _{arranged parallel to the scanned capacitor (C 1} ), which limits the charge reversal. 1 sheet of drawings © 80 »787/384 3.59