DE2654292A1 - Pulse signals reception and evaluation circuit - has transformer whose secondary winding controls logic circuit and flip=flop - Google Patents

Abstract

The signals come in on a two-wire transmission line, and consist of binary information signals and of clock pulses. Pulses of one polarity appearing on one of the wires at the clock pulse beat represent the 'H' signal elements of the binary information signal, while the pulses of the same polarity on the other wire also appearing at the clock pulse beat, represent the binary 'L' signals. A primary winding (wp) of a transformer (U) is connected to both wires (L1, L2) of the line, and its secondary winding (ws) is connected to a circuit point at a certain potential, esp. frame, through two diodes (D1, D2) and to control inputs of transistors (T1, T2) tripped to the same states by pulses of the same polarity. Transistors (T1, T2) are also connected to an INCLUSIVE-OR logic circuit (GO) which delivers clock pulses corresponding to the above clock pulses. Transistors (T1, T2) also control a flip-flop (FF1) from which the corresponding binary signal can be collected.

Description

Circuit arrangement for recording and evaluating from

binary message signals and clock, pulses formed signals.

The invention relates to a circuit arrangement for recording and evaluation of a two-wire transmission line in the form of pulses occurring signals consisting of binary message signals and clock pulses are formed, with the one wire of the transmission line with a certain Polarity occurring pulses the "H" signal elements occurring in the rhythm of the clock pulses of the respective binary message signal and where the on the other Wire of the transmission line with the specific polarity occurring impulses in the rhythm of the clock pulses occurring "'signal elements of the respective binary Represent a message signal.

A circuit arrangement of the type described above is already available known ("Electronic Design 26, 12/20/74, page 104).

The known circuit arrangement has two antiparallel to one another switched. Optocouplers, one of which responds to impulses that are in rhythm represent "H" signal elements occurring from clock pulses, and the others Impulse responds, the "L" signal elements occurring in the rhythm of the clock pulses represent. On the exit side of these two Optocoupler is one bistable Kippschaltwng connected, the output side the respective binary message signal gives away. In addition, there is an exclusive OR element on the output side of the two optocouplers connected, from the output of which the said clock pulses are emitted. from The disadvantage of this known circuit arrangement is that for the inclusion of the pulses to be evaluated are relatively expensive components, namely the optocouplers mentioned, are to be used. A further disadvantage is that the known circuit arrangement under consideration a relatively low upper limit frequency due to the use of optocouplers owns. Finally, it is disadvantageous that for the clock pulse generation a relative complex logic circuit is to be used.

In another known circuit arrangement of that mentioned at the beginning Art ("Electronic Engineering", September 1970, pages 84 to 87) are-for inclusion and evaluation of pulses from binary message signals and from clock pulses are formed, two operational amplifiers are provided with different inputs are connected to the two wires of the two-wire transmission line. To the Outputs of the two operational amplifiers is an OR-ulied with its inputs connected. The relevant clock pulses are sent from the output of this OR element submitted. The disadvantage of this known circuit arrangement is also the relatively high circuit complexity.

After all, it is already a circuit arrangement for recording and evaluation of on a two-wire transmission line in the form of pulses occurring signals known (FR-PS 2 115 249), which consist of binary message signals and are formed from clock pulses. In this known circuit arrangement occur on each wire of the two-wire transmission line pulses of both polarities Representation of "H" signal elements or "L" signal elements of respective binary message signal. On the two wires of the transmission line mentioned the known circuit arrangement is connected to the primary side of a transformer. One end of the secondary side of the transformer is in particular on one end fixed potential given by ground potential, and with its other end is the relevant secondary winding connected to the inputs of two pulse isolating circuits. The zeine pulse separator circuit is only capable of positive impulses on the input side To pass supplied pulses, and the other pulse separation circuit can only forward negative impulses of the impulses supplied to it on the input side. To the Outputs of the two pulse separation circuits is a flip-flop with bistable connected to a set input or a reset input. From the exit the respective binary message signals can be removed from this bistable multivibrator, which together with the mentioned clock pulses form the pulses that the circuit arrangement can be supplied for evaluation. At the output of a pulse separator circuit is also one input of an OR gate connected directly; with his other The input is the relevant OR element via an inverter amplifier at the output connected to the other pulse isolating circuit. From the output of the said OR gate the mentioned clock pulses are removable. Although with this known circuit arrangement can be managed with relatively cheap components and although an operation up to a relatively high upper limit frequency is possible, it can, however, with the Evaluation of the impulses occurring in each case lead to difficulties when the one Connection of the Si arxicklung of said transformer to which the inputs of the said pulse isolating circuits are connected, has a short to ground, such as due to a ground leak in one of the pulse isolation circuits. In this case, the known circuit arrangement neither binary message signals nor clock pulses are emitted. This error condition can thus not easily be distinguished from the normal idle state of the circuit arrangement in which no pulses occur on the transmission line.

The invention is based on the object of a circuit arrangement of the type mentioned at the outset while achieving a low level of circuitry Design effort so that even if a faulty short to ground occurs clock pulses can at least largely still be obtained in this circuit arrangement can be used to indicate the presence of a faulty state in the circuit arrangement can be used.

The problem indicated above is achieved on the basis of one Circuit arrangement of the type mentioned according to the invention in that the A transformer with its primary winding is connected to both wires of the transmission line is that the two ends of the secondary winding of the transformer on the one hand to one a certain potential, in particular ground potential, leading circuit point via two pn lines polarized in the same direction in relation to this potential and to others at the control inputs of two by pulses of the same polarity are connected in the same states of controllable switching devices and that via the two switching devices on the one hand the inputs of an inclusive-OR link executing logic element, which on the output side said clock pulses emits corresponding clock pulses, and on the other hand a bistable flip-flop is controlled from the output side a corresponding to the respective binary message signal binary message signal can be emitted. The invention has the advantage that with a relatively low circuit complexity ensured is that a short to ground at one of the ends of the secondary winding of said transformer does not yet lead to a general blocking of the clock pulse generation.

So there is the circuit arrangement according to the invention in spite of the presence an error of the aforementioned type clock pulses on the output side, if your input side Pulses are supplied that alternate with the rhythm of clock pulses 'tL "= and' wHt 'signal elements. However, the frequency is that of the present circuit arrangement in this case only emitted clock pulses half as high as the frequency of the clock pulses that go along with the binary message signals have formed the pulses on the input side of the circuit arrangement in question are fed. As will be seen in more detail below, this can The presence of such an error state based on the information provided by the circuit arrangement in question emitted clock pulses are recognized.

According to an advantageous embodiment of the invention, the switching devices formed by switching transistors of one and the same conductivity type. Through this This advantageously results in a particularly low circuitry effort for the realization of the switching devices.

According to a further advantageous embodiment of the invention said logic element is a NAND element. This has the advantage of one thing in particular low circuit complexity for the implementation of said logic element with himself.

According to yet another useful embodiment of the invention said bistable multivibrator is a pulse-edge-controlled RS flip-flop. This has the advantage of being a relatively simple, commercially available one To be able to use toggle switch.

According to yet another useful embodiment of the invention a JK flip-flop is connected to the output side of the RS flip-flop, which is supplied with the clock pulses emitted by the logic element at its clock input are. This has the advantage that an isochronous cycle can be performed in a relatively simple manner Delivery of the message signals from the circuit arrangement is possible, that is, that the message signals with the same phase relation to the clock pulses can occur with which the message signals are related on a transmitting end on the clock pulses present there have occurred, with which from them the pulses were formed, which the present circuit arrangement for evaluation were supplied.

According to yet another useful embodiment of the invention a shift register is connected to the output side of the RS flip-flop. This has the advantage of having the message signals with any desired To allow phase position in relation to the clock pulses.

The invention is explained in more detail below with reference to drawings.

Fig. 1 shows an embodiment of a circuit arrangement according to the invention.

Fig. 2 shows in a pulse plan the course of various Circuit points of the circuit arrangement according to FIG. 1 occurring pulses or Signals.

The circuit arrangement shown in Figure 1 consists of one Signal transmitter S and from a signal receiver E, which via a two-wire transmission line, comprehensively the two Wires L1 and L2 connected to the signal transmitter S. is.

The signal transmitter 5 has two input terminals Es and Et at 0 An the input port Binary message signals occur; at the input port Et clock pulses occur 0 at the input terminal Es is in the signal transmitter S. a NAND gate GU1 with its one input directly connected Input connection There is a further NAND element GU2 with an input via an inverter GN connected The other two inputs of the NAND elements GU19-GU2 are direct connected to the input terminal Et The outputs of the two NAND gates GUl and GU2 are connected to wires L1, L2 of the transmission line.

The signal receiver E contains on the input side a transformer U, the This transformer U can be formed by a simple toroidal core transformer has a primary winding wp, the ends of which are connected to the two wires L1, L2 connected to the transmission line. The transformer U also has a secondary winding ws that have their ends at the bases of transistors T1 and T2, respectively connected 0 These transistors T1, T2 which are of the same conductivity type (here npn) represent switching devices; the control inputs of these switching devices are formed by the bases of the transistors T1 9 T2. Further are the two ends the secondary winding ws of the transformer U via pn paths formed by diodes D1.D D2 connected to a circuit point leading to a certain potential, which is in the The present case leads to ground potential, the two diodes D1, D2 are related poled to this potential in the same sense9 which means that it is for a current flow are stressed starting from the ground potential in the forward direction. On which that called certain potential, here ground potential, are the leading circuit point furthermore, the transistors T1X, T2 with their emitters closed. In addition, the bases of the transistors T1, T2 are each over a resistor R1 or R2 at the relevant ground potential node.

The collectors of the two transistors T1, T2 are each over a resistor RIO or R20 to a rier a positive potential + U leading node connected. The collector-emitter routes of the two Transistors T1, T2 thus represent switching paths of the switching devices that are formed by these transistors T1, T2. These switching distances are dependent whether they are switched through or not, at the circuit points indicated in FIG x and y (with these connection points are the collectors of the two Transistors T15 T2 connected) either the potential + U or ground potential. Occur.

At the previously mentioned circuit points x, y there is a bistable RS flip-flop FF1 connected to their S input or to their R input. These Flip-flop FF1 is a pulse-edge controlled Ifspp circuit, which is on the leading edge of the pulse fed to their respective input can be reversed.

At the connections x9 y there is also a NAND element GO with its inputs connected. The output of the NAND element GO is connected to a clock signal output At of the signal receiver E connected.

There is a bistable at the outputs of the bistable RS flip-flop FF1 JK flip-flop FF2 with its inputs J and K connected. The clock input T of this flip-flop FF2 is connected to the output of the NAND gate GO. Of the an output of the flip-flop FF2 is connected to a message signal output As2 of the Signal receiver E connected. The tilting circuit FF2 is a clock pulse edge-controlled flip-flop that reacts to the clock pulse trailing edges is reversible.

Based on the timing diagram shown in Figure 2, now be the Operation of the Schaf processing arrangement shown in Figure 1 explained in more detail. In Figure 2, the individual pulse sequences or signal sequences are each provided with a reference number as used to designate a corresponding circuit point has been used in the circuit arrangement according to FIG direct relationship between the relevant pulse or signal sequences and the circuit points at which the relevant pulse or Signal sequences occur 0 The pulses shown in the top line in Figure 2 are at the input terminal Et of the signal transmitter, which is a clock input S occurring clock pulses. The signals shown in the second line in FIG represent the input connection Es of the signal transmitter that represents a signal input S occurring binary message signals. With "H" is for the individual pulse or signal sequences each denotes a high signal level, and "L" each indicates a low signal level. The one on the third line according to Signals shown in FIG. 2 are denoted by Es; these signals occur at the output of the egators GN of the signal transmitter S on.

The pulses considered above and shown in FIG Signals are linked in the signal transmitter S by means of the NAND elements GU1, GU2, that on the lines L1, L2 in the fourth and fifth lines in Fig. 2 shown pulse sequences occur. The pulses of these pulse trains are thus from binary message signals (at the signal input Es) and from clock pulses (at the clock input Et). The relevant impulses also occur the circuit points x, y of the signal receiver E. to 0 this gives due to the following mode of operation of the signal receiver Eo On. on wire L1 Negative pulse occurring on the transmission line may result in on the end of the secondary winding ws des connected to the base of the transistor T1 Transmitter Ü a positive pulse occurs0 At this point it should be noted that that the transistors T1, T2 of the signal receiver E normally, that is to say im Idle state of the circuit arrangement D in the non-conductive state are due to the positive existing at the mentioned end of the secondary winding ws of the transformer ü At the potential, a current flows from ground via diode D2, the secondary winding ws of the transformer U to the base of the transistor T1, which is thereby in the conductive state is controlled. This has the consequence that at the one with the node x connected collector of transistor T1 the potential from + U to ground potential is lowered. With the disappearance of the positive pulse at the base of the transistor T1, this transistor T1 returns to its non-conductive state, in at which the potential + U occurs again at the circuit point x The potential In the present case, + U represents the binary logic variable "H" and the ground potential represents the binary link size "L".

Those occurring at the circuit points x, y of the signal receiver E. Impulse, which are shown in the fourth and fifth lines in Figure 2, cause with their leading edges a corresponding reversal of the bistable trigger circuit FF1, which thereupon from their output connected to the circuit point As1 the outputs the signal shown in the sixth line in FIG. Through the in Figure 2 between the pulses occurring at the node x, y and the a node As1 occurring signals entered arrows is the effect Figure 9 illustrates the leading edges of the pulses upon reversing the flip-flop FF1 have0 those occurring at the switching point or signal output As1 Signals already represent the binary message signals9 those of the signal input It has been fed to the signal transmitter 5 0 The relevant signals occur however with a different phase position than the binary message signals9 the the signal input Es 0 in the penultimate line of FIG. 2 are those at the clock output At and thus at the output of the NAND element GO of the signal receiver E clock pulses occurring are shown. These clock pulses correspond to the clock pulses, which have been fed to the clock input Et of the signal transmitter 5, as can be seen the NAND element takes an inclusive-OR link of the input-side supplied to it Pulses vorO In the last line of Figure 2 are those at the signal output As2 des Signal receiver E occurring signals shown, which by linking the from the outputs of the bistable flip-flop FF1 emitted signals with the from Output of the NAND gate GO clock pulses emitted have been obtained from ien between the last three lines in Fig. 2 you can see 9 arrows that the clock pulses with their trailing edges a corresponding reversal of the trigger circuit Effect FF2. The signals appearing at the signal output AS2 are thus located in terms of their signal edges in the same relationship to the clock pulses that at the clock output At occur9 in which the binary message signals9 the have been supplied to the signal transmitter S, found with respect to the clock pulses that have been fed to the signal transmitter S.

In the following the malfunction mentioned above is considered that namely at one end of the secondary winding ws of the transformer U of the signal receiver E there is a short to ground. Such a short to ground can occur, for example result from the fact that one of the diodes Dl, D2 has a breakdown in this context once anS that connected to the base of the transistor Tl At the end of the secondary winding ws of the transformer U there is a short to ground p so this means that the transistor T1 is no longer controlled into its conductive state However, it is possible to control the transistor T2 to the conductive state. This always happens at the point connected to the base of transistor T2 At the end of the secondary winding ws of the transformer Ü positive pulses occur. The consequence such a pulsed control of the transistor T2 and the occurrence corresponding pulses at the node y of the signal receiver E is then that the output of the NAND gate GO emits pulses corresponding to these pulses In relation to the diagram shown in FIG. 2, this means that in this diagram Case at the clock output At of the signal receiver E pulses would occur which they are indicated in the line labeled L2, y. From the appearance of such Pulses can then be deduced from the presence of an error in an evaluation circuit will. The non-periodic occurrence of pulses on the Clock pulse output At are evaluated.

At this point it should be noted that clock pulses do not appear At the clock pulse output At, there is still no reliable statement about the presence of an error to make permitted, since this operating state does not depend on the idle state of the circuit arrangement a distinction can be made in which there are no pulses at all via the transmission line be transmitted.

In the case of the circuit arrangement shown in FIG. 1, it can It can happen that only pulses are transmitted over the transmission line9 the for example only formed from binary signal elements' iL 'or H' and clock pulses In this case there is a short to ground at one of the ends of the secondary winding ws the transmitter Ü of the receiving circuit E before, this means9 that from the clock output At the receiving circuit E either no pulses at all or clock pulses are emitted with the same repetition frequency9 as supplied to the signal transmitter 5 O In order to be able to determine such a faulty operating condition, A pulse train could be fed to the signal input Es of the signal transmitter S9 which consists alternately of "L" signal elements and "H" signal elements, pedaling these signal elements have the same periodicity as the clock input Et of the signal transmitter S supplied clock pulses occur, occurs at the clock output At the signal receiver E a pulse train with only half the pulse train frequency with which the clock pulses occurred at the input Et.

Finally it should be noted that the previously described and in Figure 1 shown successful circuit arrangement when using a transmission line relatively large length can be used. The length of the transmission line can it has been shown, for example, to be 150 m.

6 claims 2 figures.

L e r s e i t e

Claims (6)

Claims. 1. Circuit arrangement for recording and evaluating on a two-wire transmission line in the form of pulses occurring signals consisting of binary Message signals and are formed from clock pulses, the one on the one Core of the transmission line with a certain polarity occurring pulses the "H" signal elements of the respective binary that occur in the rhythm of the clock pulses Representing the message signal and being the one on the other wire of the transmission line with the specific polarity occurring impulses in the rhythm of the clock impulses represent occurring "L" signal elements of the respective binary message signal, characterized in that on the two wires (Ll L2) of the transmission line a transformer (- ~ Ü) with a primary winding (wp) is connected that the two Ends of the secondary winding (ws) of the transformer (Ü) on the one hand on a certain one Potential, in particular iviassepotential, leading circuit point over two, related pn lines (D1, D2) polarized in the same direction to this potential and to the other the control inputs of two by pulses of one and the same polarity into the same States of controllable switching devices (TI, T2) are connected and that over the two switching devices T1, T2) on the one hand the inputs of an inclusive-OR link executing logic element (GO), which on the output side the said clock pulses emits corresponding clock pulses, and on the other hand a bistable multivibrator (FF1) are controlled from the output side of the respective binary message signal corresponding binary message signal is removable. 2. Circuit arrangement according to claim 1, characterized in that ~ that the switching devices (T1, T2) by switching transistors of one and the same conductivity type are formed. 3. Circuit arrangement according to claim 1 or 2, characterized in that that said logic element (GO) is a NAND element. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that that said bistable flip-flop (FF1) is a pulse-edge-controlled RS flip-flop is. 5. Circuit arrangement according to claim 4, characterized in that a JK flip-flop (FF2) is connected to the output side of the RS flip-flop is, the output of the logic element (GG) at its clock input (T) Clock pulses are supplied. 6. Circuit arrangement according to claim 4, characterized in that a shift register is connected to the output side of the RS flip-flop (FF1) is.