DE2362441A1 - SYSTEM FOR TRANSMISSION OF BINARY SIGNALS - Google Patents

Description

Patent attorney
Dipl.-Phys. Leo Thul

Stuttgart

P. Charransol et al 18-6-2

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

System for the transmission of binary signals

The application relates to a system for the transmission of signals. It is particularly applicable in a transmission and / or switching network for coded signals in telephone exchanges can be used, which have a time division multiplex operation with pulse code modulated signals.

In a switching center of this type, the transmission of numerical information generally takes place in the Form of uninterrupted transmission of binary signals, each of which has a unit duration. These signals will be are referred to as elements and the binary values they can take are denoted by O and 1. One of those values (generally the value 1) is characterized by a (positive) potential and causes a current to flow from the transmitter to the Recipient is transmitted. The other value is through one Potential 0 and no current flows. if one element of two is one element with the value 1, so

December 3, 1973
Ti / Mr

40982.6 / 081 1

According to the laws of statistics, a current is sent during half of the transmission time. Through this power consumption there is a warming that should be prevented.

In a time division multiplex exchange one looks for ways to work as quickly as possible. You need but very fast circuits and short connections between these circuits. To such short connections To achieve this, one tries to increase the density of the circuits more and more. This results again the problem of heat loss. This problem becomes critical when the device must operate without special cooling. Therefore, any measure that can be used to reduce power consumption is of great importance.

The invention leigt the object of a system for To create transmission of binary signals in which the power consumption and thus also the heat generation can be limited. This is achieved according to the invention in that in the transmitting device the signal to be transmitted once directly and once via a delay device to a comparator circuit is applied that the comparator circuit with each change in the value of the signal to be transmitted sends a signal to the receiving device, in which a memory device, which can assume two states, through these signals are uncontrolled "This has the advantage of that only very short pulses are necessary for the transmission. Developments of the invention see the subclaims refer to.

The invention will now be explained in more detail with reference to the exemplary embodiments shown in the accompanying drawings. Show it:

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1 shows a block diagram of a signal transmission system according to the invention;

Fig. 2 pulse diagrams showing the signals at different Represent points of the system according to Fig.l;

Fig. 3 a modification of the system according to Fig.l and

Fig. 4 pulse diagrams showing the signals at different The points of the system according to Fig.3.

In the case of a signal transmission system, such as that shown in Fig. 1, a distinction is made between a transmitting device TR and a receiving device RC, which are connected via a transmission line Ig.

The transmission device TR contains at least one delay device BS and a comparator CP, a signal input IN and a clock input IH. The delay device BS is a bistable multivibrator in the exemplary embodiment of type D. This bistable multivibrator, which is in state O at the beginning, toggles with the leading edge of a clock pulse, which is applied to the clock input IH, changes to state 1 when a signal (1) to be transmitted is present at the signal IN. It tilts back to position 0 with the leading edge of a clock signal applied to input IH, if there is no signal (0) to be transmitted at input IN.

In the exemplary embodiment, the comparator CP is a logical OR circuit. Such a circuit inputs at the output Signal with level 1 off if a signal with level 0 at one of the inputs and a signal with at the other input level 1 is applied. It emits a signal with the level 0,

4.0 9 8 26./0-81-1

if the two inputs are at the same level, i.e., if both inputs are at level 0 or level 1.

The receiving device RC consists of at least one memory device BR, the input of which connects to the transmission line Ig is connected. In the exemplary embodiment, this memory is a bistable multivibrator of the JK type. With everybody The pulse that is applied to this flip-flop via the line Ig changes the flip-flop BR changes its state and thus also the level on the line ot connected to the output changes from one Level to the other level.

It is now the mode of operation of the transmission system according to Fig.l explained in connection with the pulse diagrams according to Fig.2.

In line in Fig.2 is an example of a to be transmitted Signal shown, which is present at the input IN of the system according to FIG. This signal contains one element one after the other of the value 0, three elements of the value 1, two elements of the value 0, three elements of the value 1, three elements of the value O and one Element of value 1.

Line ih shows an example of a clock signal which is applied to the input IH of the system according to FIG. The clock signal consists of a series of short pulses, the repetition frequency of which is equal to the bit rate of the Input signal is.

It is now assumed that the bistable multivibrator BS is in state 0 at the beginning and that there is no signal to be transmitted at the input IN Signal (0) is present. It is also believed

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that the bistable multivibrator BR is in the 0 position.

When the bistable multivibrator BS is in position 0, it emits a signal of level O via line db. The exclusive OR circuit CP, the two inputs of which are at level O, does not emit a signal via the line Ig. The bistable multivibrator BR receives no signal and remains in the O position. The output line ot remains at level 0.

If there is no input signal in, the clock pulses are ih has no effect on the bistable trigger circuit BS, which remains in the 0 position. The signal db also remains at level 0 and accordingly also the signal on line Ig. So the bistable flip-flop remains in the position 0 and accordingly the output line ot at the level 0. If a signal in with the level 1 occurs, the clock pulse ih is not yet applied, and the bistable flip-flop BS remains in position 0. The Signal db remains at level 0 and the exclusive OR circuit CP now sends a signal via line Ig with level 1.

In the receiving device RC, the bistable multivibrator BR remains in position 0 when a signal is at the input Will be received. This means that the output line ot also remains at level 0.

With the leading edge of a clock pulse ih has the bistable Toggle switch BS then has an input signal on both inputs and toggles to position 1. The signal db now has

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the level 1. Since now both inputs of the exclusive OR circuit are at level 1, this no longer emits a signal via the line Ig. This tilts the bistable Toggle switch BR in the receiving device to position 1 and level 1 is now applied to the output line ot.

The change of the signal in from level 0 to level 1 is thus shown in the form of a in line Ig Pulse transmitted, the duration of which is equal to the delay of the clock pulse ih compared to the beginning of the signal in is.

As long as the signal remains at level 1, the pulses ih have no effect on the bistable multivibrator BS and accordingly also to the signals on the lines db, Ig and ot.

When the signal in switches to level O, that is Clock pulse ih not yet there and the bistable flip-flop BS remains in position 1. The signal db then remains on the level 1. Since the two inputs of the exclusive OR circuit CP are now at different levels, there are a level 1 signal Ig.

The bistable multivibrator BR, which receives a signal via the input, remains in the receiving device RC Position 1. This means that the output line ot also remains open level 1. As soon as a clock pulse ih occurs, the bistable flip-flop circuit BS flips into position O. This changes the signal db to the level O. Since the two inputs of the exclusive OR circuit CP now receive the level O, this no longer emits a signal Ig. The bistable flip-flop BR toggles to position O and the signal on the line ot changes to level O.

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The change of the signal in from level 1 to level 0 is also transmitted in the form of a pulse Ig, the duration of which is equal to the delay of the clock pulses ih is in compared to the beginning of the signal.

The further operation of the arrangement takes place in the already described above: the signal to be transmitted in is at the output of the bistable trigger circuit BR again manufactured. For this purpose, the transmission line Ig transmits a short pulse only when the level of the signal to be transmitted changes. This results in a significantly reduced power consumption.

However, this system still has the disadvantage that the bistable multivibrator BR are reset; uss _o The signal Ig, which controls the state changes, is transmitted with each change of the signal in, regardless of whether it is a change from level 0 to level 1 or a change from level 1 to level 0. It is therefore necessary that the bistable multivibrator BR is in the 0 state at the beginning so that it then reproduces the signal in correctly.

A modification of the system is now based on FIG Fig.l explains that does not have this disadvantage.

The transmission system according to Figure 3 comprises again the transmitter TR and the receiving device RC and the Sig aleingang _{n f} IN to the clock input IH and the output ot.

The transmission device TR contains a bistable multivibrator BTl, which corresponds to the bistable trigger circuit BS of Dig.l, a bistable trigger circuit BT2 and a comparator CP.

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The bistable multivibrator BT2, just like the bistable Type D flip-flop BTl receives the clock signals ih and the stored signals via the two inputs, that of an output line atl from the flip-flop BTl are delivered.

The comparator CP contains two AND circuits ptl and pt2 and an input IR.

The AND circuit ptl, which is controlled by enable signals from the input IR, receives the signals atl and the Signals that are emitted via the complementary output ctO of the bistable multivibrator BT2. You generated as a function of this, a signal which is emitted via the line spl.

The AND circuit pt2, which is also controlled via enable signals from the input IR, receives signals from the line atO connected to the complementary output of the bistable multivibrator BTl are transmitted, as well as signals from the line ctl. connected to the direct output of the bistable multivibrator BT2 be transmitted. Depending on this, Sfe gives an output signal via a line sp2.

The lines spl and sp2 are connected to the primary winding of a transformer T1 and T2, respectively. The secondary windings of these transformers are connected via two-wire transmission lines IgI, Ig2, Ig3 and Ig4 to the primary winding of a transformer T ¹ I or T'2 of the receiving device RC.

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The receiving device RC also contains a bistable multivibrator BC of the RS type, the inputs of which are connected to the secondary windings of the transformers T ¹ I and T "2.

The mode of operation of the transmission system according to FIG. 3 is now shown in conjunction with the pulse diagrams according to FIG described. In FIG. 4, as in FIG. 2, the one to be transmitted is Signal shown in as well as the clock signal ih.

The enable signals ir are short pulses that are the same Repetition frequency as the clock pulses ih have and respectively occur after the corresponding clock pulse ih.

It is assumed for the description that at the beginning the bistable flip-flops BT1, BT2 and BC are in the 0 state. The signal on the output line ot of the bistable multivibrator BC has the level 0.

If a clock pulse ih is generated and the bistable multivibrator BTl does not receive a signal in, the multivibrator remains in the state 0. It then does not emit a signal atl and in the same way the bistable multivibrator BT2 remains in the state 0. The AND circuits ptl and pt2 that receive the signals atl or ctl with level 0 are blocked. They do not give a signal to the transformers T1 and T2. The transformers T ¹ I and T ¹ 2 then also receive no signal and the bistable multivibrator BC remains in state 0. The output line ot of the receiving arrangement remains at level 0.

The pulse ir then applied via the input IR of the comparator CP has no effect on the AND circuits ptl and

P. Charransol 18-6-2

pt2, as these are blocked by the signals atl or ctl.

If the signal in at input IN now changes to level 1, the clock pulse ih is not yet present, the bistable Toggle switch BTl remains in state 0 and changing the signal in has no effect on the work of the transmission system. The output line ot remains at level 0.

With the appearance of the clock pulse ih, the bistable flip-flop BTl toggles into state 1 and the signal atl now assumes level 1.

If a pulse ir is then applied to the input IR, the AND circuit ptl, the other two inputs of which also receive a signal of level 1, emits a pulse with level 1 via the output line spl. This signal generates a current equal duration in the primary winding of the transformer Tl. A current is generated in the secondary winding of this transformer by magnetic induction which is then transmitted via the cores and IgI Ig2 the line to the primary winding of transformer T ¹ l.

A current is then generated in the secondary winding of the transformer T'1 by magnetic induction and it becomes a pulse is applied to the upper input of the flip-flop BC. This flip-flop switch then toggles into state 1 and there is now a signal on the output line ot level 1. With the next clock pulse ih, signals are present at the two inputs of the bistable multivibrator circuit BT2 with level 1 and this flip-flop switches to state 1. The signal ctl then has level 1 and that

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Complementary signal ctO has the level 0 and thus blocks the AND circuit ptl.

The next pulse ir has no effect, since the AND circuit ptl by the signal ctO and the AND circuit pt2 by the Signal atO be blocked. The AND circuits do not transmit a signal. The bistable remain in the receiving device RC Flip-flop BC in state 1 and the output line ot at level 1.

This state does not change as long as the input signal has level 1. When the signal in changes to the level O, the clock pulse ih, which occurs immediately after this level change, causes the bistable flip-flop BTl to flip over to the state O. The signal atl changes to the level O and blocks the AND circuit ptl of the comparator CP. When the next unlocking pulse ir occurs, the AND circuit pt2, which receives the signals ctl and at0 with the level 1 on the other two inputs, is released and transmits a pulse via the line sp2. This pulse generates a current in the primary winding of transformer T2. A current is generated in the secondary winding of the transformer T2 by magnetic induction and flows via the wires Ig3 and Ig4 of the line to the primary winding of the transformer T ¹ 2.

A current is generated by magnetic induction in the secondary winding of the transformer T ¹ 2 and a pulse is thereby applied to the lower input of the bistable multivibrator BC. This bistable multivibrator BC switches to the state O. The level O then occurs again on the output line ot.

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At the next clock pulse ih the bistable flip-flop BT2 toggles to the state 0. The signal ctl changes to the Level 0 and thus blocks the AND circuit pt2. The AND circuit ptl is already at level 0 by the signal atl locked. All arrangements of the transmission system are thus back in the original version and the other ones Processes in the system proceed as described above.

In the transmission system according to FIG. 3, a signal is also only transmitted when a change in state of the signal to be transmitted takes place. The change of the signal in from level 0 to level 1 controls the transmission of a signal via the AND circuit ptl of the comparator CP and via the transformers Tl and T ¹ I. A change of the level in the opposite sense, ie from 1 to 0 controls the transmission of a signal by the AND circuit pt2 via the transformers T2 and T'2. It is therefore not necessary to provide a system for resetting the flip-flop BC.

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Claims (5)

P. Charransol 18-6-2
Claims System for the transmission of binary signals, characterized in that in the transmitting device (TR) the signal (in) to be transmitted is applied once directly to a comparator circuit (CP) and once via a delay device (BS; BT2) that the comparator circuit is applied with each change the value of the signal to be transmitted sends a signal (Ig; spl, sp2) to the receiving device (RC) in which a memory device (BR; BC), which can assume two states, is reversed by these signals. 2. System according to claim 1, characterized in that as a comparator circuit (CP) an exclusive OR circuit is used. 3. System according to claim 1, characterized at that time delay device and bistable flip-flops are used as the memory device. 4. System according to claim 1, characterized in that as a comparator circuit (CP) two AND circuits (ptl, pt2) are used that the one AND circuit (ptl) to be transmitted Signal (atl) and the complementary value of the delayed signal (ctO) and to the other AND circuit (pt2) of the Complementary value of the signal to be transmitted (atO) and the delayed signal (ctl) are applied and that the output signals (spl, sp2) are transmitted via separate lines to the storage device (BC). 409828/0811. P. Charransol 18-6-2 5. System according to claim 3 or 4, characterized in that the devices of the transmitting device by a clock (in, ir) can be controlled. 409826/0811 Blank page