DE2653716A1 - DATA TRANSFER ARRANGEMENT - Google Patents

Description

BLUMBACH · WESER · BERGEiV. CHANDLER

PATENT LAWYERS IN MUNICH AND WIESBADEN

Postal address Munich: Patentccr.sult 8 Munich 60 Radedcestraöe 43 Telephone (089) 883603/883604 Telex 05-212313 Postal address Wiesbaden- Patcr.tconsüit 62 V. '. Csbader: Sonnenberger Straße 43 Telephone (06121) 562943/561998 Telex 0-1Sun

Western Electric Company

Incorporated
New York, NY 10007, USA Sherman DN 1-1

Data transfer arrangement

The invention relates to an arrangement for the transmission of data between an analog transmission medium and a plurality of digital data ports with a digital signal processor for implementation all functions of a data transmission arrangement of a first type and circuits for sequential connection of the processor to each the data connections.

With the advent of digital computers, the need for a digital messaging between remote Calculators. This need is mostly met by using existing networks with analog voice band channels that are used for voice transmission purposes, i.e. the telephone network. For the transmission of digital signals via such analog

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log channels it is necessary to modify the digital signals in such a way that they fit into the permissible bandwidth and to restore the digital signals at the receiving end. For this purpose, the digital signals are modulated onto a voice-frequency carrier signal and, after transmission, demodulated to recover the original digital data. A digital data transmission arrangement or a data device that can perform the above operations, also known as a MODEM (Mod ulator -the odulator).

The users of such modems often require multiple data devices, each with different properties. To meet this Today, the required types of data devices are installed in each case. However, that means a considerable investment for the user. In addition, it often turns out that the user's needs change from time to time, for example to change the To improve transmission possibilities. This in turn makes the effort and expense of replacing the existing data devices against the required required. In U.S. Patent 3,649,759 (March 14 1972) a circuit arrangement is described, which the functions more as a data device can meet at the same time. This is achieved by

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connection of a high-speed control processor to successive ones Data connections and implementation of the functions of a data device for each connection achieved. In the known circuit arrangement however, all simulated data devices are of the same type. Accordingly, there is a need for greater flexibility a universal data device that fulfills the functions of a variety of data devices and can be rearranged so that each result in the specific characteristics of any desired data device.

The invention is based on solving the problem arising therefrom of an arrangement of the type mentioned and provides that the processor to carry out all functions at least the data transmission arrangement of a second type is designed that the data signals occurring at certain data connections a Require processing by the data transmission arrangement of the first type and that the data signals occurring at other data connections require processing by the data transmission arrangement of the second type.

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The invention is described below with reference to the drawings.

1 shows a general block diagram of a universal data device 10, which is designed according to the principles of the invention. The heart of the universal data device 10 is cyclical Processor 100 and a high speed digital signal processor 200. The processor 100 includes, among other things, a changeable one Memory in which the parameters defining the structure of the data device are written. These parameters define the number and the types of data devices which the data device according to FIG. 1 is to simulate, the priorities of the various data devices and other special ones Features that may be desired. The parameters for defining the structure are transferred to the via a signal bus 101 changeable memory of the processor 100 written. This can be done in the manufacturer's works, by a change by the user or by a The universal data device can be accessed remotely. The cyclic processor 100 contains further memories, the information relating to the particular computations that the high speed processor 100 must perform and the particular order of the necessary calculations. The in the memories of the processor 100

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The information contained therein is used by the processor 100 for control of the high speed processor 200 operations. This control takes place via the command bus 110.

The processor 200 includes an arithmetic logic unit, a multiplier, a read only memory (ROM) with a sine look-up table and a memory or a plurality of registers containing a Form short-term storage. Processor 200 performs all of the logic, delay, and arithmetic operations necessary to implement the Modulation and demodulation functions of the universal data device are required.

In addition to the modulation and demodulation functions, the Processor 200 performs all other signal manipulations of the data device, for example an adaptation, filtering, format formation of digital data and other functions.

The signals fed to the processor 200 arise either in one digital buffer processor 300 or in an analog buffer processor 400. The digital buffer processor 300 takes digital signals from data ports

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700 and transmits the signals compiled in a suitable manner to processor 200. Circuit block 700 may comprise a single data port or a plurality of data ports. In a corresponding manner, the analog buffer processor 400 receives digital signals from the processor 200 and outputs corresponding analog signals to the transmission medium 800. In addition, the processor 400 receives analog signals from the transmission medium 800 and outputs corresponding Digital signals to processor 200. Processor 300 contains registers for storing and transferring data signals between processor 200 and data ports 700. Processor 400 includes an analog-to-digital converter, which in some cases a control circuit for adaptive gain adjustment is connected upstream, furthermore a digital-to-analog converter, followed by a analog low-pass filter and buffer register for the digital-to-analog and the analog-to-digital converter. In addition to the digital processor 300 Line control processor 500 provides a signaling and control interface between the data ports 700 and the data devices of FIG. 1. For example, the processor 500 accepts "send request" signals of all data connections in block 700, informs the cyclic processor 100 of such requests

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and sends on command from processor 500 (this command is generated on the basis of corresponding signals from data connections 700) "Ready-to-send" signals to the requesting data ports. In a corresponding manner, processor 500 takes indications of data connections at block 700 to be ready for incoming data and responds with "ready" signals going back to the requesting party Data connections are given.

The entire timing of the processors 100, 200, 300, 400 and 500 is taken over by the timing device 600. These Facility provides the various synchronization clock signals that are required. All clock signals generated by device 600 are derived in the form of fractions of a single predetermined frequency generated within device 600.

Digital data connections, which are suitable for operation together with existing data devices, generate bit streams with logical "0" and "1 ^!: Signals. These bit streams are sometimes referred to as" digital signal "V" direct current signal "or" baseband signal ". designated. Some data connections generate an in addition to the digital signal

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Synchronization clock and require such a clock for reception of digital signals. It is said that such data connections transmit and receive synchronously. Other data devices send and receive asynchronously.

In most data devices, the incoming digital signal is divided into groups of bits, with each group being a symbol or a Baud defined. The symbols are processed within the data device and transmitted over the transmission medium at a rate which is proportional to the bit stream rate (called "bit rate") and the number of bits per symbol (called "symbol rate" or "baud rate"). Man Note that in connection with the present application the unit Hertz Hz simply denotes the frequency of occurrence, for example means a bit rate of 2,400 Hz 2,400 bits per second.

For digital processing in the data device, the incoming Symbols are sampled before processing. It is expedient to choose a sampling rate or a sampling clock that is an integer Is a multiple of the expected baud rates for the incoming data. In addition, a high-frequency master clock is used for digital processing required to carry out the various basic operations in the cyclic

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Processor and in high-speed digital signal processor too synchronize. This clock must have a much higher frequency than the sampling clock, so that a sufficient number of operations can be carried out. A clock frequency of 12 MHz, for example, is not too high a frequency given the complexity of the required Tasks of the data device and the state of the art in integrated circuits is taken into account.

When designing the time control for a universal data device According to the invention, two basic clock schemes can be used, namely a fixed master clock or a variable master clock. The variable clock can lead to a reduction in the various frequency divider requirements and the possibilities for Increase the handling of different baud rates, but a fixed clock rate offers some basic simplifications. For the one described here Embodiment, therefore, a fixed basic clock MHz is chosen. In addition, in the described embodiment, the universal Data device given the possibility of simultaneously serving eight data connections with an internal "frame" frequency of 7,500 Hz. A "frame" is the period of time in which a sampling

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value can be processed by any of the eight data devices. The frame frequency of 7.500 Hz is intentionally higher than the preferred frame rate at 7,200 Hz (which is an integral multiple of the baud rate) to ensure proper synchronization of the internal operation of the Data device (at the frame frequency) with the sampling frequency, which in turn with the incoming signals of the data connection is synchronous.

Fig. 2 shows the manner in which the frame frequency of 7,500 Hz creates the possibility for the universal data device according to the invention to work together synchronously with a large number of data connections, which have various sampling frequencies and phases. The x-axis in Fig. 2 indicates the processing time and is on the line 60 divided into frames 1 to 10. Line 70 specifies the sampled values of a first data connection, axis 80 the sampled values of a second data connection and the axis 90 the samples of a third data connection. Note that the first and second data ports be sampled at a high frequency, which is only slightly lower than the sampling frequency, and that an arbitrary phase difference between the samples of the first and second data

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Losing is available. Also note that the third data port is sampled at a frequency which is equal to half the sampling frequency for the first data connection, and that an arbitrary one There is a phase difference between the sampled values of the third data connection and those of the other data connections.

In accordance with the principles of the present invention, the Samples 71, 81 and 91 on lines 70, 80 and 90, respectively, are all in frame 1 and are shown in frame 2 as shown in FIG Line 60 processed (samples 71 ', 81' and 91 '). On the line there are no samples in frame 2. Accordingly, only the samples 72 'and 92' in frame 3 are processed. To this The universal data device according to FIG. 1 works with its own internal frame frequency and is nevertheless able to provide a To serve a multitude of data connections which have their own sampling frequencies which are not synchronous with the sampling frequency of the universal data device.

It should be noted, however, that of course, because within the universal data device, the sampled values are not

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vall appear (for example, frame 4 in FIG. 2 does not contain any Sample from first data device), past information operations must be carefully performed. For example, if a recursive filter is provided, the information required to implement the filter must be related to of the past are stored during a frame that is not taking a data sample, so the final result will not is as if a sample with the value 0 has arrived. Accordingly, during a frame with no input sample all counter readings, program positions and short-term arithmetic values are "frozen".

It should also be pointed out that the data samples processed by the universal data device are available at the output of the processor at the frame frequency of the processor 200. The actual data transmission to the data connections 700 or to the transmission medium 800 must, however, take place at the sampling frequency. To achieve this change in synchronization from the frame frequency of 7,500 Hz to the sampling frequency of 7,200 Hz, a delay of one frame is required. In order to explain

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After this operation, the x-axis 60 from FIG. 2 is doubled in FIG. 3 with the signals from the data device as received by the processor 200 (elements 71 'to 78'). In addition, in FIG. 3, line 70 from FIG. 2 is duplicated with the signals which are generated by the first data connection (elements 71-78). By providing the aforementioned delay by one frame, the elements 71 '- 78' can be "clocked" into the delay device by the processor 200 using the frame clock and "clocked out" of the delay device using the clock . This is indicated by the elements 71 ″ -78 ″ and the associated dashed lines.

As shown in connection with the x-axis 60 in FIGS. 2 and 3, each frame in the data device according to FIG. 1 is divided into intervals, called macro-intervals, the number of which is equal to the maximum number of data connections that can be operated by the data device. Each macro interval is one for processing the data Reserved for the data connection. In this way, each data connection is served once per frame, if necessary. With the one described here Embodiment can be in terms of that eight

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Data connections can be served by the data device according to FIG. 1, the sum of the eight macro intervals the duration of 1 / (7,500) or 133.3 ps. not exceed, which corresponds to 1,600 periods of the clock with 12 MHz. Each period of the clock (83.333 ns) is called a "command ^{interval 11} or" micro int ervall ".

From the above explanation it can be seen that only a limited time for processing incoming signals and performing the various functions available for the universal Data device according to the invention are required. Accordingly, the circuit structure of the invention is with a high speed processor 200 and a low-speed cyclic processor 100 are particularly suitable for the present purposes. The cyclical one The processor specifies the order of processing and calculates the necessary further processing operations,

speed processor the required operations

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4, the high-speed processor 200 has a first data bus 210, a second data bus 220, an arithmetic logic unit 230, a multiplier 240,

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a short term memory 250 and read only memory (ROM) with a sine look-up table 260. The aforementioned components of the processor 220 are all responsive to the data buses 210, 220 and provide their output signals on the same data buses 210 or 220. The output signals of the aforementioned components can also from the data buses 210 and 220 are separated. This enables an effective pro-rata use of the data bus lines.

The arithmetic logic unit 230 (ALU) performs all arithmetic and logical operations that use two operands. These operands are derived from data buses 210 and 220 won. An instruction bus 110 provides the instructions that control the various operations of the ALU 230. That means, that the command bus 110 carries out the special operations to be carried out (e.g. adding, subtracting, ANDing, etc.) as well as the destination of the result (e.g. to manifold 210, to manifold 220 or none from both). The ALU unit 230 can be implemented in several ways.

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The multiplier 240 performs the arithmetic multiplication operations for factors obtained from data busses 210 and 220. Since the multiplier 240 is only one type of operation, it is expediently designed so that it always receives the signals appearing on the buses 210 and 220 multiplied. Thus, to obtain a desired product, the multiplier 240 need only be instructed (via command bus 110) to put the product output at the correct one Time to give to the respective data collector.

The short-term memory 250 can be a (dynamic or static) memory or consist of a group of individual storage registers. The memory 240 holds intermediate results (e.g. Counter readings to determine expired intervals), which are used to carry out various functions of the universal data device according to Fig. 4 are required.

The command bus 102 gives the address of the respective memory location in memory 250, the bus involved (210 or 220) and also whether the information transfer from the data bus

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to the memory or vice versa. It should be noted that the practical implementation of the memory 250 using a memory unit with a smaller footprint and lower cost leads. However, the use of individual memory registers enables simultaneous addressing (for read and write processes) from more than one register.

The ROM unit 260 is also a memory. It contains values of the Sine function for the range from 0 to 7T / 2. They are useful Sine values are sequentially stored in the read-only memory 260, the memory addresses corresponding to the angles whose sine value is being sought will. For example, the address 0 can contain the sine for 0 degrees, the address 1 the sine of 90 / 1,024 degrees and the address 1.023 is the sine of (9O) (I.023) / 1024 degrees. With this arrangement leaves win the desired sine value in that the command bus 102 the address of the read-only memory 260 and that Data bus (210 or 220) indicates to which the sine value is to be applied.

Because of the parallel structure of the processor 200, the collective

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line 110 simultaneously commands more than one component of the processor 200 deliver. For example, command bus 110 may instruct ALU 230 to logically OR for perform the signals appearing on data buses 210 and 220, and at the same time command the result to be applied to the Data bus 210 is given. At the same time, the memory 250 can be instructed to put the result on the data bus 210 and to store it in an address A (or in register A). In addition, the processor 200 can concurrently instruct the.Festwertspeicher 260, the sine value of the address

S to be output on the data bus line 220. Because the multiplier 240 requires a certain amount of time to carry out a multiplication operation, it is in fact also possible to obtain a product signal of the To receive signals that have been linked by the ALU unit 230 by an OR function.

The buses 210 and 220 extend from the processor 200 and connect it to the digital buffer processor 300 and to the Analog buffer processor 400.

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In the analog buffer processor 400, a digital-to-analog converter speaks (D / A converter) 410 and an analog-to-digital converter (A / D converter) 420 to data busses 210 and 220. The converter 420 includes a plurality of D / A converters, the number of which is equal to the number of data ports that can be served by the universal data device and an equal number of data registers. Be based on commands on the command bus 110 the data on the manifold 210 respectively. on the bus with the correct sampling frequency in the shift register of the correct D / A converter clocked and converted there into an analog format. The analog output signals of the D / A converter block 410 v / ground is applied to a low pass filter block 430. Block 430 contains a low pass filter for each D / A converter in block 410. Accordingly the analog output signal of each D / A converter is filtered and then transmitted to the medium 800 (e.g. a plurality of telephone lines, the number of which is equal to the number of data connections that are served by the universal data device can).

For signals traveling in the opposite direction will be

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the analog signals transmitted to the universal data device according to FIG the medium 800 are fed to the AGC unit 440 for the automatic gain control. Unit 440 includes how the blocks 410 and 430 a large number of components for the automatic gain control, the number of which equals the number of data connections that can be operated by the universal data device. Based on commands on the command bus 110 controls each gain control unit determines the strength of the incoming signal. The output signals of the gain control element in block 440 are given to A / D converter block 420 which has an analog to digital converter and an associated data register for each gain control element in block 40 contains. The signals appearing at the input of the individual A / D converters in block 420 are compared with the respective Sampling frequency is sampled, converted into digital format and then shifted into the respective data register at the sampling frequency. Addicted of instructions on instruction bus 110, the outputs of selected data registers of block 420 become the correct ones Time applied to a selected data bus line (210 or 220).

In digital reef processor 300 are data busses 210 and

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220 each with an input data register 310 and an output data register ;. J connected. The input register 310 contains one Group of registers, the number of which is equal to the number of data connections which can be operated by the data device according to FIG. In the embodiment described here, the data register 310 contains eight registers. Each of these registers takes information from the data connections 700 with the sampling clock frequency of the respectively connected data connection and supplies the clocked Signals the correct time on the correct data bus (210 or 220) based on commands on the command bus 110. The output data register 320 contains similar to the input data register 310 a multiplicity of data registers, each of which gives signals to a different data connection of the data connections 700. In response to commands on command bus 110, the various output registers of register 320 take information from the data bus 210 or 220 with the frame frequency of the data device and pass this data on to the connected data connection.

In addition to their connection to the digital buffer processor 300, the The connections 700 must be connected to a line control processor 500.

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The block 500 in FIG. 4 corresponds of course to the block 500 in FIG. Its function has already been described in connection with FIG.

The processor 100 is the primary control element of the universal data device in Fig. 4. It comprises a modem control component 120, a program control component 130, a program memory 140, a sub-sequence memory 150, a cyclic memory 160 and a jump control component 170

The subsequence memory 150 is a programmed memory which is connected to the command bus 110 and this is the respective Feeds instructions that control processors 200, 300 and 400. The instructions in memory 150 are in groups of instruction sequences or Groups of sub-sequences summarized, which are carried out by the fact that on the instruction bus 110 the contents of successive Storage locations in the subsequence is given, starting with the first instruction of the subsequence and ending with the last instruction the sub-succession. An executed sub-sequence causes processors 200, 300 and 400 to perform a distinguishable function or sub-sequence.

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to execute the function of the data device. Since the memory 150 is the one Component is that gives the commands directly on the bus 110, it must contain all the sub-sequences necessary to achieve the desired Functions of the universal data device are required. Because of the elementary nature of the sub-sequences (for example, a single repetition a unipolar recursive filter), however, any sub-structure can be used in the implementation of a number of functions so that the total number of subsequences required is small.

To fully perform a main function of the universal 4, a number of sub-sequences must be processed in succession (with some sub-sequences possibly multiple times be run through). This selection is made by the program memory 140, which is connected to the sub-sequence memory 150 and delivers the addresses of the initial sub-sequence to this. The program memory 140 contains a multiplicity of programs, each with a list with the start addresses of the desired sub-sequences.

Based on such a realization of the main functions, an addition

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Compilation of programs to create any standard data device to be used. The grouping of programs to define the structure of a data device is carried out in the program control 130 realized. The component 130 is connected to the program memory 140 and is also a memory that contains a sequence of starting addresses supplies, which in this case are the addresses in the program memory 140 in which the programs for the required Main functions of the data device are stored.

As stated above, the universal data device according to the invention Serve a variety of data connections that require different types of data devices. It can also be achieved be that the universal data device according to the invention a different Represents the type of data device for a specific data connection. In the special structure according to the invention, this Adaptability achieved by the modem control component 120, the is connected to the program controller 130. In the embodiment described here, the modem control component 120 contains eight Storage locations. Access occurs during the first macro interval to the first memory, during the second macro interval

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to the second memory location, etc. up to an access to the eighth memory location during the eighth macro interval. Each memory location indicates the type of data device that is being used by the universal data device is to be realized according to the invention during a certain macro interval. This specification takes the form of an address that to program control 130 is given. The ones contained in component 120 Addresses indicate at which point in the program control 130 a specific data device is implemented. According to the basic idea of the invention is the bus 101 with the modem control component 120 connected to allow modification of the data device types, which are realized by the universal data device. The signal for the bus 101 can be accessed by direct access to the universal data device or from a remote location via the transmission medium by connecting the bus 101 via the interface formed by the analog buffer processor will.

For a correct calculation of the various functions of the different Data devices need parameter information (in addition to instructions or data) to processor 200 and on a smaller scale

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to processors 300 and 400. Hence there is in the processor 100 a cyclic memory 160, which is based on signals from the program control 130 and as a function of read-write commands from the sub-sequence memory 150 enables the required storage of and access to the desired constants. The memory 160 provides data to the data buses 210 or 220 and under control of the slave memory 150 records from this data.

To improve the adaptability of the processor 100, the Jump control 170 is provided which provides a means for performing a jump from a memory location within the processing sequence of the universal data device to another storage location in the sequence. This increases the possibility of an "unconditional" jump created that the jump control 170 is connected to the sub-sequence memory, and the possibility of a "conditional" jump through Connect the jump control 170 to the data ammunition line 220 (Line 171 in Fig. 4). The jump control influences the function of signals on the command bus 110 (via the line 172) 170 the program control 130, the program memory 140

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and sub-sequence memory 150. Jump control 170 can be in a simple manner with the aid of gates that are actuated in a corresponding manner via the line 172 to the logic level on data bus 220 or the logic level of signals provided by sub-sequence memory 150

In addition to the busses 110, 120 and 220 are in the data device 4, a timing bus 610 and a timing bus 620 are provided. The timing bus 610 supplies timing signals from timing device 600 to all other components of the universal data device, and timing bus 620 provides basic timing information from selected components of the data device to the timing device 600. Accordingly, the line control processor delivers 500 "Send" clock information of the active data connections of block 700 to time control device 600 (line 621), while the bus 610 supplies the timing device 600 with the "receive" clock information. The modem control component 120 gives the control unit 600 the main timing information for each implemented data unit and the control unit 600 supplies

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to the modem control component 120, the main frame that contains the modem control component 120 indexes through its memory locations. The sub-sequence memory 150 supplies the controller 600 with “reception timing” correction information (for the implementation of synchronous data devices) and receives the main clock information from the timing device 600 for advancing memory 150 through its memory locations. When realizing certain data devices must Timing signals (or their corrections) are calculated. For this purpose, the control unit 600 has a signal path (line 622) to receive information from data bus 220. Finally, the control device 600 delivers via the manifold 610 timing information to the D / A and A / D converters of the processor 400, to the ALU unit 230, to the multiplier 240, to the memory 250 and to the sine read-only memory 260 of the processor 200 and to the input and output data registers of processor 300.

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Claims (3)

BLUMBACH-WESER-BERGEN-KRAMER ZWIRNER · HIRSCH 26q3 / 1 Q PATENT LAWYERS IN MÖNCHEN AND WIESBADEN Postal address Munich: Patentconsult 8 Munich 60 Radeckestrasse 43 Telephone (089) 883603/883604 Telex 05-212313 Postal address Wiesbaden: Patenlconsull 62 Wiesbaden Sonnenbergei Strasse 43 Teielon (06121) 562943/561998 Telex 04-186 Claims _1. Arrangement for the transmission of data between an analog transmission medium and a variety of digital data connections with a digital signal processor for performing all functions of a data transmission arrangement of a first type and circuits for sequentially connecting the processor to each of the data connections,
characterized, that the processor (10) also for performing all functions of at least the data transmission arrangement of a second type is designed that the on certain data connections. ^ 700) occurring Data signals processing by the data transmission 709822 / 094S Kramer ■ Dr. Weser Hirsch - Wiesbaden: Blumbach Dr. Bergen · Zwirner ORIGINAL! NSPlCTED require the first type of arrangement, and that the data signals appearing at other data connections (700) require processing by the data transmission arrangement of the second type. 2. Arrangement for the transmission of data according to claim 1, characterized in that that the digital signal processor is a cyclic processor (100), which is designed to store the operating characteristics of each particular type of transmission arrangement, as well as an arithmetic one Processor (200) which is restructured by coming from the cyclic processor control signals so that it corresponds to a selected type of data transmission system and is able to transfer data between the analog transmission medium (800) and one of the digital data connections (700), which requires the selected type of data transmission arrangement. 3. Arrangement for the transmission of data according to claim 2, characterized in that that the arithmetic processor (200) a plurality of. Logic- 709822/0946 , 3- Components (230, 240, 250, 260) each having certain operations with data signals arriving in parallel on data bus lines (210, 22.), depending on commands arriving from the cyclic processor (100) over an instruction bus (110). 7 0 9 8 7. ? / 0 9 U β