DE2653128C2 - Charge-coupled device - Google Patents

Description

The invention relates to a charge-coupled device for converting an electromagnetic radiation pattern in a certain wavelength range, in particular but not exclusively an infrared radiation pattern, into electrical signals.

Charge-coupled devices for imaging purposes are now well known and are already used as image sensors in experimental television cameras.

Charge coupled devices of the type first proposed were based on the storage in depletion regions and transport near the surface of a semiconductor layer of one conductivity type of discrete charge packets in the form of minority carriers. Thus, when an n-type layer is used, holes are stored and transported. Such devices are generally referred to as surface channel CCD's. In a later stage of development, improved efficiency of charge transfer between adjacent storage locations is obtained in a structure in which majority carriers are stored and transported, this transport taking place via the interior of the semiconductor layer. These devices, sometimes referred to as "bulk" or "buried channel" CCD's, are described in British Patent Specification No. 14 14 183. Such an arrangement comprises a semiconductor body with a semiconductor layer of one conductivity type, means being provided for electrically isolating the semiconductor layer from its surroundings at least during operation, said layer having a thickness and doping concentration such that a depletion zone can be obtained over the entire thickness of the semiconductor layer by means of an electric field while avoiding breakdown. The arrangement further comprises means for locally introducing information in the form of charge consisting of majority charge carriers into the semiconductor layer and means for reading this information elsewhere in the layer, an electrode system being provided on at least one side of the layer, by means of which electric fields are capacitively generated in the semiconductor layer, through which the charge can be transported to the readout means via the interior of the semiconductor layer in a direction parallel to the layer. Such an arrangement can be designed for imaging purposes, the local introduction of information in the form of majority charge carriers comprising the generation of electron-hole pairs by the absorption of incident radiation in the vicinity of a depletion zone formed in the semiconductor layer close to the electrode system.

In order to use the known charge-coupled devices for imaging purposes, it is necessary that the photon energy of the incident radiation is greater than the band gap of the semiconductor material. This allows, for example, visible radiation with an energy exceeding 1.1 eV to be detected using a silicon CCD, with both the surface channel and the "bulk" or "buried channel" configurations being suitable for this purpose.

Charge-coupled devices in many different forms have been proposed for imaging an infrared radiation pattern, as already described in the article "Application of Charge-Coupled Devices to Infrared Detection and Imaging" by A.J. Steckl et al, published in CCD 74, International Conference, Technology and Application of Charge Coupled Devices, September '74, pg. 256/279. In a so-called "hybrid" design, the detection and signal processing operations are carried out in separate but integrable parts by means of a matrix of infrared detection elements, each of which is individually connected to a silicon CCD shift register. In this case, the silicon CCD serves as a signal processing device which performs appropriate operations. In another so-called "monolithic" design, the detection and signal processing operations are carried out in the same part of the semiconductor body. In a proposed design of a "monolithic" CCD for infrared imaging, the action and structure are essentially similar to those of a silicon surface channel CCD and are based on the creation of depletion regions near the semiconductor surface where photogenerated minority carriers are trapped. The arrangement differs from conventional silicon imaging CCDs with respect to the material of the semiconductor layer. This material must be chosen such that the absorption peak lies in the infrared region, the band gap of the semiconductor material being smaller than the energy of the infrared photons. Therefore, the choice of material is limited to certain narrow band gap semiconductor materials of the binary and ternary III-V, II-VI and IV-VI compounds. This is to some extent disadvantageous because the processing technology in these materials is not as advanced as in silicon, and it is clear that although the basic charge storage and transfer of a CCD may not depend on the presence of a pn junction, it is nevertheless necessary in many practical embodiments to incorporate regions whose conductivity type is opposite to that of the layer in which charge storage and transport take place.

In another proposed "monolithic" design of an infrared CCD imaging device, the effect is based on the accumulation of majority charge carriers (electrons) at the surface of an n-type silicon layer and their transfer near the surface, these electrons being released from deep donor levels maintained throughout an n-type silicon layer. The operation of this arrangement requires cooling to a low temperature to minimize the thermal generation of majority carriers, while the disadvantages in terms of charge transfer efficiency and operating speed inherent in a conventional surface channel device are strongly felt.

The invention is based on the object of creating a monolithic design of an infrared CCD imaging device made of silicon, in which the charge transfer takes place in the volume of the silicon body instead of in a surface channel.

According to the invention, a charge-coupled device for converting an electromagnetic radiation pattern in a certain wavelength range into electrical signals comprises a semiconductor body with a semiconductor layer of one conductivity type and is characterized in that the device belongs to the type of charge-coupled device in which pattern information in the form of discrete packets of majority charge carriers can be generated and transported via the interior of the semiconductor layer to means for reading out the charge, the layer having a concentration of at least one doping impurity determining the one conductivity type and a concentration of at least one deep-level impurity of the type defined here, by means of which centers for capturing majority charge carriers are obtained which can be released after excitation by radiation in the said wavelength range, the doping impurity concentration and the deep-level impurity concentration being arranged in such a way that depletion zones can be formed which extend over the thickness of the layer, whereby breakdown is avoided, which is only due to the fact that almost all deep-level centers are within the Depletion zones are fully occupied with the majority charge carriers that determine a conduction type.

The term "low-level impurity" is used here to mean an impurity which is in thermal equilibrium in the bulk of the semiconductor material in a given charge state and whose charge state changes to a constant state in a depleted region. This means that the energy level of a low-level impurity in n-type material must be below the Fermi level (of the semiconductor material in equilibrium) in the upper half of the band gap and the energy level of a low-level impurity in p-type material must be above the Fermi level (of the semiconductor material in equilibrium) in the lower half of the band gap.

Such an arrangement, in which the charge transport takes place across the interior of the semiconductor layer and in which the generation of the charge packets is based on excitation of majority charge carriers trapped in the deep level centers and on their release to the potential minima in the layer rather than on the normal generation of electron-hole pairs by absorption of radiation, has significant advantages when it is desired to form a monolithic charge-coupled device for converting a radiation pattern in a given wavelength range into electrical signals. Although cooling of the semiconductor body is thus required in most cases, it is no longer absolutely necessary to use a semiconductor material with an energy band gap smaller than the photon energy of the incident radiation to which the device is to be sensitive. In particular, there is the advantage that silicon with its inherent advanced technology can be used for an infrared imaging CCD, the low level impurity concentration being selected such that sensitivity to infrared radiation in a certain wavelength range is obtained.

In a device according to the invention the deep level impurity concentration in the layer will be higher than the value which, for a layer of the same semiconductor material and of the same thickness with only one doping impurity concentration determining the one conductivity type, corresponds to the value with which the highest attainable magnitude of the net charge in the bulk of the layer is obtained with which it is still possible in a steady state to form depletion zones which extend over the whole thickness of the semiconductor layer while avoiding breakdown. It should be noted that at least in this respect the device structure differs from previously proposed charge-coupled devices in which the charge transport takes place via the interior of the semiconductor layer, which layer contains more than one impurity concentration.

In practice, the highest achievable magnitude of net charge which can exist in the bulk of the layer will depend on the particular material of the one-charge type layer. However, for a silicon layer in an array structure in which the layer can be depleted from opposite major surfaces, the magnitude of the net charge must be less than 4 x 10 ¹² /cm ² . As will be described in detail below, in order to efficiently convert incident radiation, the value of the deep level concentration is chosen such that the magnitude of the net charge in a steady state considerably exceeds the said limit, that is, in the described example of an array having such a silicon layer which can be depleted from opposite major surfaces, the value of the deep level concentration is chosen such that a net charge in a steady state is obtained which is considerably greater than 4 x 10 ¹² /cm ² .

The effect of a device according to an invention is based, inter alia, on the ability to completely deplete the semiconductor layer during a radiation integration period without avalanche breakdown occurring, which therefore means that during a radiation integration period a non-equilibrium state exists and the net charge within the depletion zones must be kept below the said highest achievable value. Of course, the case can be considered, which does not lie within the scope of the invention, in which the total number of impurities, i.e. the sum of the doping and deep level impurities, is limited in such a way that in a steady state the said highest achievable value of the net charge cannot be exceeded; such a structure would, however, not be particularly sensitive and would have a low response speed.

The device structure according to the invention is based, inter alia, on the recognition that the quantum yield of the device depends on the number of majority charge carriers which are trapped in deep level centers built into the layer, and that by forming a very large number of said deep level centers and integrating them during operation over a sufficiently short period so that the number of such centers which trigger a trapped majority charge carrier and therefore increase the net charge in the depletion regions does not result in the said highest achievable size of the net charge in the depletion regions being exceeded, a high sensitivity compatible with "bulk" or "buried channel" CCD operation can be obtained. In theory, if the number of deep level centers were limited, as already mentioned, in such a way that, even in a steady state, the said highest achievable size of the net charge could not be exceeded, a very long integration period would be possible. However, with such a relatively small number of low-level centers to intercept the radiation, most of the input radiation would be lost, i.e. would not be intercepted by the low-level centers.

The operation of a device according to the invention is also based on the requirement that thermally induced changes in the charge state of the low-level centers take place at a lower rate than the optically induced changes, i.e. that the generation of free majority charge carriers within the depletion zones by radiation excitation must take place at a significantly higher rate than in the case of thermal excitation. This depends to some extent on the choice of the particular low-level impurity and the operating temperature, as will be described in detail below.

There are various possibilities for applying the doping impurity concentration and the low-level impurity concentration. In one embodiment, the low-level impurity concentration is greater than the doping impurity concentration. In such an embodiment, the low-level impurity concentration will comprise a low-level donor in an n-type layer or a low-level acceptor in a p-type layer. In this embodiment, the charge state of the low-level centers in the depletion zones is neutral in equilibrium, i.e. a donor center with a single trapped electron or an acceptor center with a single trapped hole is in a neutral state and can change to a positive or negative charge state by optical excitation, respectively. It is also possible to use centers that can capture two carriers, while the optical excitation can be such that only one carrier of the center is lost, these centers being so-called double-negative or double-positive centers.

In another embodiment according to the invention, the doping impurity concentration is greater than the low-level impurity concentration, which is applied as a balancing impurity. In such an embodiment, the low-level impurity concentration may comprise a low-level acceptor in an n-type layer or a low-level donor in a p-type layer. In this embodiment, the charge state of the low-level centers in the depletion zone is negative or positive in equilibrium, i.e. an acceptor center with a single trapped electron is in a negative charge state and a donor center with a single trapped hole is in a positive charge state and can be converted to a neutral state by optical excitation. In this embodiment, it may also be possible to use impurities with which so-called double-negative or double-positive centers are obtained.

In certain embodiments of the device, the low level impurity concentration is formed by at least one low level impurity element introduced into the crystal lattice of at least a portion of the one conduction type layer. Various elements may be used depending on the semiconductor material and the wavelength range of the radiation, but the sensitivity will by definition be limited to a wavelength range corresponding to energy values below the energy band gap of the semiconductor material.

In other embodiments of the device, the low-level impurity concentration is formed by impurities introduced into the crystal lattice of at least a portion of the layer of one conductivity type. Such impurities, which produce low-level centers, can be formed by damage caused by radiation, e.g. by proton or electron bombardment. The impurities can act as equalizing centers.

The layer of one conductivity type can contain a first part in which the transport of free majority charge carriers can take place and a second part in which the generation of free majority charge carriers by radiation in the wavelength range mentioned can take place, the low-level impurity concentration being almost limited to the second part of the layer. In such an embodiment, the charge carrier transport takes place via an inner part of the layer which is almost separated from the part of the layer in which the free charge carriers are generated by radiation excitation. However, the invention also includes arrangements in which the low-level impurity concentration is not localized in the manner mentioned and the charge transport takes place via an inner part of the layer in which the low-level impurity concentration is present.

When the low level impurity concentration is limited to substantially a portion of the layer, namely the second portion in the embodiment described above, and when such low level impurity concentration is appropriate as a compensating impurity concentration, the doping impurity concentration in the remaining portion of the layer of one conductivity type, i.e. in the first portion in the embodiment described above, must have a sufficiently low value so that the said maximum value of the net charge is not exceeded.

Various configurations of an electrode system forming part of the arrangement with respect to the position of the layer part or parts with the deep-level impurity concentration are possible. Thus, in a first embodiment, an electrode system for capacitive generation of electric fields in the Semiconductor layer by means of which discrete majority charge carrier packets triggered by exciting radiation are introduced into depletion regions and transported to the charge reading means, on one main side of the layer, while said second layer part with the deep level impurity concentration is adjacent to the layer surface on said one main side. This structure can be easily implemented during manufacture and various alternative methods for applying the deep level impurity concentration can be used, as will be described below.

In a second embodiment, an electrode system for capacitively generating electric fields in the semiconductor layer, by means of which discrete majority charge carrier packets triggered by exciting radiation are introduced into depletion regions and transported to the charge reading means, is present on one main side of the layer, while the second layer part containing the low level impurity concentration adjoins the layer surface on the opposite main side of the layer. In this embodiment, by positioning the electrode system and the second layer part on opposite main sides of the layer, other features relating to the structure and the manufacture can be used to advantage.

In an example of the second embodiment mentioned, an increased charge handling capacity of the device is obtained with a structure in which the layer of one conductivity type includes a more heavily doped surface region extending adjacent to the one major side, this more heavily doped surface region extending over only a portion of the thickness of the layer and being located some distance from the portion containing the deep level impurity concentration. For further explanation of the mechanism by which the charge handling capacity of a buried channel or bulk CCD is increased by the provision of such a more heavily doped surface layer, reference is made to British Patent Application No. 24 624/73 relating to the same subject matter.

In said first as well as in said second embodiment of this arrangement, the layer of one conductivity type can adjoin a surface region of the opposite conductivity type, wherein the electrode system is located on the main side of the layer which faces away from the region of the opposite conductivity type.

Said region of opposite conductivity type forming a pn junction with the layer of one conductivity type providing at least part of the insulation of the layer from its environment during operation of the device may be present as a substrate of said opposite conductivity type on which said layer of one conductivity type is present. However, in an example of said second embodiment of the device, the region of opposite conductivity type is present as a surface layer, e.g. a diffused surface layer, on said main side, which in this case forms the semiconductor body. In this embodiment, the deep level impurity concentration can be provided in a part extending over a substantial part of the thickness of the layer and, due to the large number of deep level impurity trapping centers thereby created, allows a high detection capability to be obtained.

In one example of a charge coupled device according to the invention, in which the low level impurity concentration is greater than the dopant impurity concentration, the layer is made of p-type silicon, the low level impurity concentration contains at least one of the elements indium and thallium and a sensitivity to infrared radiation in the wavelength range between 3 and 5 µm is obtained. In another example, in which the low level impurity concentration exceeds the dopant impurity concentration, the layer is made of p-type silicon and the low level impurity concentration is formed by gallium and provides a sensitivity to infrared radiation in the wavelength range between 8 and 14 µm. When an n-type silicon layer is used in a device in which the low level impurity concentration exceeds the dopant impurity concentration, the low level impurity is such as to give rise to donor states. One such example is sulfur.

Reference has already been made to devices according to the invention in which the dopant impurity concentration is greater than the low level impurity concentration which is appropriate as a compensating impurity concentration. Such a compensating impurity concentration can be obtained by acceptors in the upper half of the band gap or donors in the lower half of the band gap. These impurities can be doping impurities or impurities but must have energy levels which are at an appropriate distance from the edge of the band, namely the edge of the conduction band in n-type silicon and the edge of the valence band in p-type silicon, in order to obtain the desired sensitivity to radiation in the particular wavelength range in which the device is to be operated. When a silicon layer is used, a suitable balancing impurity is gold, which has a balancing level of 9.35 eV from the edge of the valence band in p-type silicon and provides sensitivity to radiation of wavelengths between 1.1 and about 3.5 µm. Gold also provides a balancing level of 0.55 eV from the edge of the conduction band in n-type silicon and gives sensitivity to radiation of wavelengths between 1.1 and about 2.25 µm. Balancing centers can also be obtained from impurity levels induced by radiation damage. For example, protons can create balancing centers in n-type silicon with a level of nearly 0.4 eV from the edge of the conduction band and provide sensitivity to radiation of wavelengths between 1.1 and about 3 µm.

The low level impurity concentration may be present as an ion implanted concentration. The use of ion implantation to obtain the low level impurity concentration is advantageous because it allows an impurity element or elements to be placed in a uniform distribution over a given area, which is particularly desirable in an imaging device, while allowing these elements to be placed precisely at the desired part of the layer, whereby at the same time a sufficient number of majority charge carrier capture centers can be provided. This limitation can be of importance in those embodiments of the arrangement whose effect can be impaired by the presence of any charge capture centers in the inner part of the layer in which the charge transport takes place.

In addition, ion implantation allows the introduction of impurity elements with a normally relatively low solubility in the solid semiconductor material.

Since the optical cross section of deep level centers will be small in order to obtain the majority free carriers by radiation excitation, it is desirable that the value per square centimeter of the deep level impurity centers be at least 5 x 10 ¹² and even 10 ¹⁶ /cm ² . In practice, such a concentration is difficult to obtain in a thin layer because of the limitations of the solubility of the deep level impurities in the solid semiconductor material concerned. However, if high concentrations are used, the problem arises that if the charge state of a substantial fraction of the deep level impurities in the depletion regions is changed, it would not be possible to completely deplete the semiconductor layer without causing breakdown, and such layer depletion is a fundamental requirement for the satisfactory charge transfer performance of the charge coupled device. In practice, this problem is avoided when using such high concentrations by controlling the integration period, ie the period in which the radiation can impinge on a particular imaging part of the layer between successive refreshment steps in which the low-level centers are supplemented with majority charge carriers, in such a way that in said period at maximum radiation intensity not more than a certain number of the centers, eg not more than 10 ¹² centers/cm ² , will change their charge state.

Thus, when operating a charge-coupled device according to the invention, it is necessary to periodically refresh the semiconductor layer portion with the low-level impurity concentration by supplementing the low-level centers with majority charge carriers.

The semiconductor layer may further comprise electrode means by which the deep level centers can be supplemented with majority charge carriers. In other embodiments, as described below, the supplementation may be carried out by a suitable configuration of the circuit used to operate the device.

In a further development of the arrangement, the semiconductor layer contains an input stage for generating majority charge carrier packets which can be transported in a direction parallel to the layer, while the circuit for periodically replenishing the deep-level centers with majority charge carriers contains means by means of which signals are fed to the input stage for periodically introducing refreshing charge packets of majority charge carriers of such a size that, during their transport through the layer, they reach at least as far as the part of the layer with the deep-level impurity concentration.

Some embodiments of the invention are shown in the drawings and are described in more detail below. It shows

Fig. 1 is a plan view of a charge-coupled device according to the invention for imaging an infrared radiation pattern,

Fig. 2 is a section through the arrangement according to Fig. 1 along the line II-II of Fig. 1,

Fig. 3 is a section through the arrangement according to Fig. 1 along the line III-III of Fig. 1,

Fig. 4 is a cross-sectional view of another charge-coupled device according to the invention for imaging an infrared radiation pattern,

Fig. 5 is a cross-section through the arrangement according to Fig. 4 along the line VV of Fig. 4, and

Fig. 6 is a graphical representation of the waveforms of the potential applied to the electrodes of the arrangement of Figs. 4 and 5 when operating to image an infrared radiation pattern.

Fig. 1 to 3 show a simplified embodiment of a charge-coupled infrared imaging device, the elementary imaging parts of which have the form of a linear matrix. Of course, the invention also includes devices in which the elementary imaging parts have the form of a two-dimensional matrix (so-called area imaging devices), but for the sake of clarity in the illustration and description of the device structure according to the invention, the embodiment according to Fig. 1 to 3 with a linear matrix will be described.

The device comprises a semiconductor body 1 made of silicon with a p-type semiconductor layer 2 adjacent to the surface 3 and located on an n-type substrate 4. The substrate 4 has a thickness of 200 µm and a resistivity of 10 Ω cm. The layer 2 has a thickness of 6 µm and includes a portion 5 adjacent to the surface in which there is an ion-implanted indium concentration. The layer 2 is doped with boron in a nearly uniform concentration of 10 ¹⁵ atoms/cm ^-3 , that is, nearly equal to 6 10 ¹¹ impurities/cm ² in each area of the layer. The ion-implanted indium concentration extends to a depth from the surface 3 of 2 µm and the peak concentration is at a depth of 0.25 µm from the surface. The dose used to form the ion-implanted indium concentration is 5 · 10 ¹⁴ /cm ² .

The n-conducting substrate 4, together with the pn junction between the substrate 4 and the layer 2, forms part of means for isolating the semiconductor 2 from its environment, at least during operation of the device. The said insulating means also comprise an insulating layer 7 of silicon oxide on the surface 3 and an n-conducting surface region 8 which, as shown in the plan view of Fig. 1, laterally surrounds the p-conducting layer 2. In the present embodiment, the region 8 is an n+ diffused region which extends over the entire thickness of the layer 2 into the substrate 4. For the electrical insulation of the layer 2, the pn junction between the region 8 and the layer 2 is advantageously biased in the reverse direction, the connection to the region 8 being made via a connection to the substrate 4 . In other embodiments, a recessed insulating layer may be used instead of the region 8 or an n-conducting region may be provided which extends from the surface 3 of the layer over only a part of the thickness of the layer 2 In the latter case, the device is operated with such applied potentials that the depletion regions associated with the substrate/layer pn junction between the n-conducting surface region and the p-conducting layer 2 complete the insulation.

The thickness and the boron doping of the p-conductive layer 2 are such that a depletion region can be created by means of an electric field which extends over the entire thickness of the layer 2 , whereby breakdown is avoided. By using such a layer 2 , which can be insulated from the environment during operation, charge in the form of majority charge carriers can be transported mainly (in particular the last fractions of charge packets to be transferred between storage locations) over the inner part of the layer.

The charge forming the pattern information is introduced into depletion regions created in the part of layer 2 underlying surface portion 5 from deep acceptor levels formed by the ion-implanted indium impurity concentration. At the operating temperature, almost all of these impurities are deionized and said deep acceptor levels form trapping centers for holes which can be triggered upon excitation by infrared radiation in the wavelength range between 3 and 5 µm. The extent of surface portion 5 and the applied potentials at different parts of the device, as described below, are such that the potential minima in the depletion regions created in layer 2 are located at locations separated from surface portion 5 . Thus, provided that the size of a charge packet representing pattern information does not exceed a certain value determined by other features of the process, as described below, the transport of the charge packets representing pattern information can take place over an inner part of the layer without the charge packets reaching the surface part 5 containing the capture centers formed by the implanted indium concentration. Thus, pattern information in the form of discrete majority charge carrier packets can be generated in storage locations in the layer 2 when incident infrared radiation in the wavelength range mentioned penetrates into the surface part 5. In the present embodiment, in which the layer 2 is doped with acceptor impurities, both in the bulk of the layer and in the surface part 5 , this means that the pattern information generated via the deep level centers, which is introduced into storage locations in the layer and then transported through the layer, has the form of holes.

At one end of the layer there is a more heavily doped p-type surface region 10 on which there is an input lead 9. At the other end of the layer there is a more heavily doped p-type surface region 12 on which there is an output lead 11. The input lead 9 and surface region 10 allow further introduction of holes into the layer 2 , this introduction and subsequent transport through the layer, as described below, being such that holes are periodically added to the deep acceptor levels formed by the ion-implanted indium concentration. The output lead 11 and surface region 12 are used as part of means for reading out the extent of the charge packets and removing the charge packets from the layer, but this part of the operation will not be described in detail because it can be carried out in a conventional manner.

On the surface of the layer 2 there is an electrode system for capacitively generating electric fields in the layer 2 , with the aid of which charge packets representing pattern information can be captured and then transported to the readout means ( 11, 12 ) in a direction parallel to the layer. The electrode system contains a plurality of electrodes 13 in the form of conductive layers which are separated from the semiconductor layer 2 by the silicon oxide layer on the surface 3. The arrangement structure is arranged in a suitable manner with respect to the relevant direction of incidence of the radiation pattern. Thus, if, for example, the infrared radiation pattern to be recorded is to be directed onto the upper surface, the material and thickness of the electrodes are selected such that transmission of the said radiation is enabled; the electrodes can, for example, consist of polycrystalline silicon. Also, when using a silicon body with the dimensions mentioned, the radiation pattern can be directed to the underside of the body because infrared radiation in the wavelength range mentioned is transmitted through the substrate 4 and the layer 2 and reaches the part 5 with low-level impurity centers.

In a direction perpendicular to the relevant charge transport direction, the electrodes extend over the entire width of the semiconductor layer 2 , as shown in Fig. 1 and 3. The arrangement according to Figs. 1 to 3 is operated as a three-phase CCD in which the electrodes 13 are connected in three groups to clock lines Φ ₁ , Φ ₂ and Φ ₃ for applying clock voltages.

It will be appreciated, however, that the electrode configuration in an arrangement according to the invention may be different from the configuration of the arrangement shown; for example, the polycrystalline silicon electrodes may be formed at different levels and in mutual overlap; the electrodes may be mounted on insulating layer portions of different thicknesses; and other known means may be used. In addition, the arrangement may be designed for two-phase or four-phase operation.

For a full description of the charge transfer effect of a charge coupled device in which the transport takes place via the interior of the semiconductor layer, reference is made to British Patent Specification 14 14 183. The operation of the device according to Figs. 1 to 3 as regards the formation of electrical signals representing an infrared radiation pattern will now be described.

The substrate 4 is connected to a reference potential, e.g. earth potential, while a voltage of almost -10 V is applied to the layer 2 , e.g. via the input contact 9. The clock voltages applied to the lines Φ ₁ , Φ ₂ and Φ ₃ vary, e.g. between +2 ⁰ V and +5 V. Starting from the situation in which the free majority charge carriers, i.e. uncaptured holes, are removed from the layer 2 , it can be calculated that potential minima for holes are obtained in the depleted parts of the semiconductor layer under the electrodes 13 at a depth of almost 5 µm. 3 , to which the lowest voltage is applied. By suitable choice of the clock voltages subsequently applied to the electrodes, said charge packets collected, for example, under the electrodes connected to the line Φ 3 , can be transported to a region under the next electrodes, and so on. In this way, the charge packets initially deposited under the electrodes connected to the line Φ ₃ can _be concentrated . ₃ connected electrodes are transferred one after the other to the reading means ( 11, 12 ) where they are eliminated. The charge transport of the last fractions of the charge packets can take place at a relatively large distance from the electrodes 13 and also from the surface part 5 .

The device is operated in a cyclic mode in which, at the beginning of an image period, the low-level centers are first supplemented with majority charge carriers. Then, in said period, an image integration period follows in which pattern information is converted into discrete charge packets present in depletion regions formed under the electrodes 13 and in each bit collected in the depletion regions under the electrodes connected to the clock line φ ₃ , these charge packets having a size which is dependent on the total local intensity during the integration period of the incident infrared radiation in the relevant surface part 5 of the layer under the electrodes 13 of this image bit. Then, in said image period, the charge packets representing pattern information are transferred one after the other to the readout means and removed from the layer before the beginning of the next image period.

The first stage, namely the supplementation of the deep level centers in the surface part 5 with holes, is carried out in this embodiment by introducing excessively large charge packets at the entrance ( 9, 10 ) and transferring them to the exit. The expression "excessively large charge packets" is to be understood here as charge packets of such a size that, when they pass through the layer, they partially reach the surface part 5 and there release holes to the unoccupied deep levels.

In another embodiment, the deep levels are supplemented by simultaneously connecting all electrodes 13 to ground potential in order to discharge the depletion regions, including the parts thereof formed in the surface part 5 .

Since the high photon flux occurs in the infrared region of the spectrum, in many cases the frame period can be relatively short; e.g. in the case of a linear matrix of 100 bits the frame period may be 100 µsec and of this period the integration period is 95 µsec. The actual frame period is determined by a number of factors for each individual case, including the type and concentration of the deep level contamination. For example, the frame period may be a maximum of 40 msec and a minimum of 10 µsec.

In any special case where a silicon layer is used, the net charge within the depletion regions cannot exceed nearly 4 x 10 ¹² /cm ² because then the breakdown field would be exceeded. The duration of the image integration period forming part of the image period is chosen in connection with the concentration of the low level impurity such that when infrared radiation of maximum intensity in this whole period is incident on each elementary image part under a group of electrodes 13 forming a bit, the charge packet generated in the part of the layer under the surface part 5 will be confined to this part and will not reach the surface part 5 containing the capture centers during the subsequent transport to the readout means.

A further embodiment of the invention will now be described with reference to Figs. 4 to 6. In this arrangement, parts corresponding to those in Figs. 1 to 3 are designated by the same reference numerals. The main difference is that the p-type epitaxial silicon layer 2 has a much greater thickness and different impurity distributions. Thus, layer 2 has a total thickness of 35 µm and contains boron throughout its thickness at a background concentration of 10 ¹⁴ atoms/cm ^-3 . Layer 2 contains a first portion 16 with a thickness of almost 25 µm which borders on substrate 4 and contains as a low level impurity an indium concentration of 5 x 10 ¹⁶ cm ^-3 which corresponds to a value of 1.25 x 10 ¹⁴ impurities/cm ² . Adjacent to the surface 3 of layer 2 and separated from the indium-containing portion 16 by a portion 17 containing almost only the background boron concentration, there is a more heavily doped portion 18 with a thickness of almost 1 µm containing an additional diffused concentration of a suitable acceptor, e.g. boron, in a concentration of 5 x 10 ¹⁵ cm ^-3 . In this arrangement, the isolation is obtained in part by means of the n+ surface region 19 which extends only partially through layer 2 , by applying a suitable reverse bias across the pn junction between region 19 and layer 2 so that the depletion region associated with this junction extends at least as far as the depletion region associated with the reverse biased pn junction between the n-type substrate 4 and the p-type layer 2 .

This arrangement can be operated in a similar manner to the previous embodiment. In this embodiment, the electrode structure is advantageously designed such that infrared radiation in the wavelength range between 3 and 5 µm can be transmitted. However, the arrangement structure can easily be modified to obtain a structure in which the radiation pattern is directed away from the substrate side.

Fig. 6 shows the waveform diagrams of the voltages applied to the lines Φ ₁ , Φ ₂ , Φ ₃ and the input electrode voltage V _in . In this mode of operation, the potential applied to the p+ region 10 normally determines the potential applied to the layer 2 and is -50 V with respect to the grounded substrate. To supplement the deep level impurity centers with majority carriers, the potential V _in is temporarily brought to the substrate potential. During this period, designated t _ri , the deep level centers formed by the indium concentration are replenished with holes, which is due to the depletion zones in the layer being completely discharged. After the period t _{ri ,} the CCP is reset for a period designated t _rs , during which almost all free majority charge carriers are removed from the layer. At the end of the period t _rs , the voltages on the lines Φ ₁ , Φ ₂ and Φ ₃ are maintained at constant levels during a period t _im , during which the imaging of the infrared pattern takes place and the charge packets consisting of holes, generated by the exciting radiation as described above, are collected under the electrodes connected to Φ 3 in each part. Then, in a readout period t ro , these charge packets are transported to the output electrode 12 and read out by means not shown. The clock voltages on the lines Φ 1 , Φ 2 and Φ 3 are maintained at constant levels during a period t im , during which the imaging of the infrared pattern takes place and the charge packets consisting of holes, which are generated by the exciting radiation as described above, are collected under the electrodes connected to Φ ₃ in each part. Then, in a readout period t _ro , these charge packets are transported to the output electrode 12 and read out by means not shown. ₁ , Φ ₂ , Φ ₃ are chosen according to a number of different factors and may vary in one example between 5 and 25 V. If it is desired to bring the charge packets closer to the surface 3 , lower clock voltages may be used and in another example these voltages are negative with respect to the substrate.

It will be appreciated that various manufacturing techniques known to those skilled in the art may be used in forming the embodiments described so far and in other modifications to be described below. In producing the embodiment described with reference to Figs. 4 and 5, the p-type layer comprising the layer portions 16, 17 and 18 may be provided in two stages. Thus, the layer portion in which the deep-level impurity is to be provided may first be epitaxially deposited on the substrate 4 and then the deep-level impurity may be provided in this layer portion by ion implantation or diffusion, after which the remaining layer portion is provided by a second epitaxial deposition step, the more heavily doped surface portion 18 being provided, for example, by a subsequent diffusion step. Also, instead of providing the deep-level impurity by ion implantation or diffusion, the epitaxial step may be carried out in such a way that the deep-level impurity is provided at the same time as, for example, the deep-level impurity. B. the background impurity element which determines the conductivity of said layer part.

It will be appreciated that for the desired operation of the device described it will be necessary to cool the semiconductor body. The actual operating temperature will be determined by the nature of the low level impurity. It is essential that the thermal excitation rate of the low level centers be much lower than the optical excitation rate. Thus for a silicon infrared imaging device for operation in the 3 to 5 µm range, acceptable operation is obtained by cooling to 77°K when using a p-channel CCD with thallium as the low level impurity. The alternative element indium already described may require further cooling. For a silicon device for operation in the 8 to 14 µm wavelength range, cooling to a low temperature, e.g. 20°K, may be necessary for satisfactory operation. Such cooling is, however, considered to be quite acceptable in view of the fact that by employing the device structure according to the invention in which an intrinsically doped semiconductor layer of some material, e.g. B. silicon, the sensitivity of the device is effectively extended to a wavelength range in which the photon energy is significantly lower than the band gap of the semiconductor material.

Although the embodiments described are elementary linear arrays, it will be appreciated that an arrangement according to the invention may have a more complex configuration. Thus, a so-called area imaging device may be formed and various means for reading out the charge of the type used in conventional imaging CCDs may be used; e.g. a sensor may also include a masked array of elements corresponding in number to the elements used in the imaging part of the sensor, the masked array being connected to the imaging array and serving as a memory which is read out via a series/parallel CCD conversion stage.

Two further embodiments of the invention will now be described which are modifications of the embodiment described with reference to Figs. 1 to 3. In the first of said further embodiments the low level impurity is applied as a compensating low level donor impurity throughout the layer 2 which is more heavily doped with boron in a concentration of 5 x 10 ¹⁶ atoms/cm ^-3 , which corresponds almost to 2 x 10 ¹³ atoms cm ² , than in the embodiment described with reference to Figs. 1 to 3. The layer thickness in this embodiment is less, namely 4 µm. The low level impurity concentration is formed by gold which has been introduced into the layer by ion implantation in an amount almost equal to the boron concentration. In other respects the structure is similar to that of Figs. 1 to 3. However, the mode of operation differs at least in that the transport of free majority charge carriers generated by radiation takes place through a part of the silicon layer in which the deep-level capture centers formed by the gold are present.

In this embodiment, the compensating deep level centers formed by the gold provide sensitivity to infrared radiation in a wavelength range between 1.1 and almost 3.5 µm.

In a second further embodiment, which is a further development of the embodiment described with reference to Figs. 1 to 3, the conduction types are all reversed, so that the substrate 4 consists of p-conductive silicon and the layer 2 of n-conductive silicon and the insulating zone 8 is of the p-type. The n-conductive layer, which in this embodiment has a thickness of 4 µm, is almost uniformly doped with phosphorus in a concentration corresponding to 4 x 10 ¹³ atoms/cm ² . The low-level impurity concentration is formed by compensating impurities which are generated in the crystal lattice of the layer by proton bombardment. The proton bombardment is optimized in such a way that an impurity density is obtained which changes with the depth in the layer and has a peak concentration near the phosphorus concentration, the part of the n-conductive layer lying next to the surface 3 immediately below the insulating layer 7 having a much lower impurity density, such that the phosphorus concentration in this region, and is relatively uncompensated over a distance of almost 0.1 µm from the surface 3. In this embodiment, the low-level centers generated by the impurities result in a sensitivity to infrared radiation in a wavelength range between 1.1 and almost 3 µm.

In this structure, the relatively uncompensated surface area provides nearly the same benefits of higher charge handling capacity as the more heavily doped surface 18 in the embodiment described with reference to Figs. 4 to 6.

In any of the embodiments described, it is also possible to provide the low level contamination in the form of a number of discrete portions extending at the same level in the layer instead of one continuous layer portion, said discrete portions extending locally flush with the electrodes provided on the main surface of the layer.

Claims (18)

1. Charge-coupled device for converting an electromagnetic radiation pattern in the infrared wavelength range into electrical signals, which device comprises a semiconductor body with a semiconductor layer of one conductivity type, characterized in that the device belongs to the type of charge-coupled device in which pattern information in the form of discrete packets of majority charge carriers can be generated and transported via the interior of the semiconductor layer to means for reading out the charge, the layer having a concentration of at least one doping impurity which determines the one conductivity type and a concentration of at least one deep-level impurity of the type defined here, with the aid of which centers for capturing majority charge carriers are obtained which can be released after excitation by radiation in the said wavelength range, the doping impurity concentration and the deep-level impurity concentration being arranged in such a way that depletion zones can be formed which extend over the thickness of the layer, whereby breakdown is avoided, which is only due to the fact that almost all deep-level centers within the depletion zones are filled with the majority charge carriers determining a conduction type are fully occupied. 2. A charge coupled device according to claim 1, characterized in that the low level impurity concentration is greater than the doping impurity concentration. 3. A charge coupled device according to claim 1, characterized in that the dopant impurity concentration is greater than the deep level impurity concentration which is appropriate as a compensating impurity concentration. 4. A charge-coupled device according to any one of claims 1 to 3, characterized in that the low level impurity concentration is formed by at least one impurity element which is introduced into the crystal lattice of at least a portion of the layer of one conduction type. 5. A charge-coupled device according to any one of claims 1 to 3, characterized in that the low-level impurity concentration is formed by impurities introduced into the crystal lattice of at least a portion of the layer of one conduction type. 6. Charge-coupled device according to one of claims 1 to 5, characterized in that the layer of one conduction type contains a first part in which transport of free majority charge carriers can take place and a second part in which the generation of free majority charge carriers by radiation in the said wavelength range can take place, the low-level impurity concentration being almost limited to the second part of the layer. 7. A charge coupled device according to claim 6, characterized in that an electrode system for capacitively generating electric fields in the semiconductor layer, by means of which discrete majority charge carrier packets triggered by exciting radiation are introduced into depletion zones and transported to the charge reading means, is present on a main side of the layer, while said second part containing the low level impurity concentration adjoins the layer surface on said one main side. 8. Charge-coupled device according to claim 6, characterized in that an electrode system for capacitively generating electric fields in the semiconductor layer, by means of which discrete majority charge carrier packets triggered by exciting radiation are introduced into depletion zones and transported to the charge reading means, is present on one main side of the layer, while the second part containing the low-level impurity concentration borders on the layer surface on the opposite main side of the layer. 9. A charge coupled device according to claim 8, characterized in that the layer of one conductivity type includes a more heavily doped surface region extending adjacent to the one major side, said more heavily doped surface region extending over only a portion of the thickness of the layer and spaced from the portion containing the low level impurity concentration. 10. Charge-coupled device according to one of claims 7 to 9, characterized in that the layer of one conduction type borders on a semiconductor region of the opposite conduction type, the electrode system being located on the main side of the layer which faces away from the region of the opposite conduction type. 11. A charge-coupled device according to any one of claims 1 to 10, characterized in that the semiconductor layer consists of silicon and the low-level impurity concentration is selected such that a sensitivity to infrared radiation in a certain wavelength range is obtained. 12. A charge-coupled device according to claims 2 and 11, characterized in that the layer consists of p-type silicon and the low level impurity concentration contains at least one of the elements indium and thallium and provides a sensitivity to infrared radiation in the wavelength range between 3 and 5 µm. 13. A charge coupled device according to claim 11 in direct or indirect connection with claim 2, characterized in that the layer consists of p-type silicon and the low level impurity concentration is formed by gallium and provides a sensitivity to infrared radiation in the wavelength range between 8 and 14 µm. 14. A charge coupled device according to claim 11, in direct or indirect connection with claim 3, characterized in that the layer consists of p-type silicon and the low level impurity concentration is formed by gold and provides a sensitivity to infrared radiation in the wavelength range between 1.1 and 3.5 µm. 15. Charge-coupled device according to claim 11, in direct or indirect connection with claim 5, characterized in that the layer consists of n-type silicon and the low level impurity concentration is formed by defects in the crystal lattice induced by proton bombardment and results in a sensitivity to infrared radiation in the wavelength range between 1.1 and 3.0 µm. 16. A charge coupled device according to any one of claims 1 to 13, characterized in that the low level impurity concentration is present as an ion implanted concentration. 17. A charge coupled device according to any one of claims 1 to 14, characterized in that the low level impurity concentration is in the range of 5 · 10 ¹² impurities/cm ² to 10 ¹⁶ impurities/cm ² . 18. Charge-coupled device according to one of claims 1 to 17, characterized in that the semiconductor layer further contains electrode means with the aid of which the centers formed by the deep-level impurity are periodically supplemented with majority charge carriers.