DE2637081A1 - Auxiliary test memory for dedicated micro-computers - has read-write memory used for development with facility for entry of programme routine into programmed PROM - Google Patents

Abstract

An auxiliary test memory is used in micro computer systems for establishing programme routines in read-write memory before entering into read only memory. As such the unit is used as a development aid. The unit consists of an address converter a memory selection circuit, a read-write memory and a programme read only memory. The supply line, address bus and control bus are coupled directly to the microcomputer system. Data from the computer is entered into appropriate memory dependent upon the control and modified address signals processed over the converter.

Description

Test auxiliary memory block for task-specific microcomputers

The invention relates to an auxiliary test memory block which has a read-write memory, a read-only memory as a load program memory, a memory selection module, a Address converter, a group of potential lines for feeding its electrical Building blocks and a group of electrical signal lines for connection to and for the Messaging with a microcomputer, which is stored in its loader memory contains a program with the help of which a connected microcomputer can control the Can load read / write memory of the test auxiliary memory block and its address converter is able to assign the address values generated by the microcomputer to the read / write memory and to the load program memory of the test auxiliary memory block in response to a control signal to change.

The test auxiliary memory block becomes a task-specific microcomputer is connected to this microcomputer and is used for loading and for deletable and overwritable storage of those programs, which after the test phase completely removes the operational read-only memory of the microcomputer or partially fill out. The read-write memory of the test auxiliary memory block represents during the test phase the operational read-only memory of the microcomputer, its Still in use because of the numerous program changes that occurred at that time does not make sense. The read / write memory of the test auxiliary memory block has the same memory addresses as the operational read-only memory during the test runs of the microcomputer, it thus makes an address-based testing of those programs possible that later in the operational read-only memory of the microcomputer stand.

The use of read / write memories instead of fixed-value memories with microcomputers during the testing phase is known. You will be in the too temporarily inserted into the testing microcomputers, or they are integral parts a second microcomputer, which with the microcomputer to be tested during the trial phase is interconnected.

Provided a read / write memory in the usual way in a microcomputer to be tested is temporarily inserted, however, is not him the same amount of address values is assigned as the later use read-only memory. Because apart from the temporarily inserted read-write memory is during the test phase an initial read-only memory is available, which is decisive for the start of the program run Includes initial address and a loading program for loading the Programs. However, the later use fixed value memory must contain the initial address and does not need the loading program in many applications. This becomes a Program testing that is true to the address is prevented.

If a second microcomputer is used for the testing provides the necessary read-write memory and the loading which takes over the programs to be tested, this means that a program test that is true to the address is established made possible, but the effort involved in the addition of the second microcomputer is considerable elevated.

The invention is based on the object of a test auxiliary memory block for microcomputers to be specified during the testing phase in a to be tested Microcomputer can be inserted, which enables the loading of the programs to be tested into its read-write memory makes, which after the respective program load on Control signal the exact same amount of address values towards the read / write memory assigned, which the later use read-only memory of the microcomputer has, the thus an address-based testing of the programs to be used later in the same Microcomputer enables and the addition of a second microcomputer during the trial phase is unnecessary.

According to the invention, this object is achieved by an auxiliary test memory block solved, which has a read / write memory, a read-only memory as a load program memory, a memory selection module, an address converter, potential lines for supply its electrical components, signal lines for connection to and for the exchange of messages with a microcomputer, which includes a program in its loader program memory includes, with the help of which a connected microcomputer reads-write memory of the auxiliary test memory block and whose address converter is able to in response to control signals, optionally the assignment of the address values generated by the microcomputer to the read / write memory and to the loader program memory of the test auxiliary memory block so set that once the read / write memory has exactly the same address value set receives the initial address like the later use fixed value memory and thus itself for program runs in this address value set and that on the other hand the initial address for program runs is assigned to the loader program memory.

The signal lines of the auxiliary test memory block are subdivided into outer address lines, inner address lines, data lines and control signal lines. When the test auxiliary memory block is connected to a microcomputer, the outer ones are available Address lines, the data lines and the control signal lines of the test auxiliary memory block in conductive connection with the corresponding address lines, data lines and Control signal lines of the microcomputer.

To read data from the test auxiliary memory block or to write data to the To write test auxiliary memory block, the microcomputer sets address signals to its Address lines and control signals on its control signal lines, in the case of data writing also data signals on its data lines. The ones coming from the microcomputer Address signals are sent via the external address lines of the auxiliary test memory block fed to the address converter. This converts them according to an address transformation function and converts the transformed address signals to the inner address lines of the Test auxiliary storage blocks.

From here the transformed address signals reach the memory selection module, in the read / write memory and in the loader program memory. The memory selection module takes control signals from the control signal lines and generates them from and out the transformed address signals switch-on signals which it sends to the read-write memory or the loader memory. Transformed ones get into the read / write memory Address signals, switch-on signals and control signals from the control signal lines.

On the basis of these input signals, the read / write memory is set on the one hand In the event of data signals on the data lines via which they reach the microcomputer, in the other case, the read / write memory takes data signals from the microcomputer via the data lines.

Transformed address signals and switch-on signals are sent to the loader program memory on the basis of which it puts data signals on the data lines, from where these get into the microcomputer.

The address converter is able to respond to control signals transmitted to it Control signal lines are fed, each with a different selectable address transformation function to bring to use. This defines the assignment of the read / write memory and the load program memory to the address values sent out by the microcomputer.

The test auxiliary memory block is an advantageous tool for the testing of task-specific microcomputers by running it with little The effort made possible for the use of fixed-value memories of these microcomputers To test programs true to the address and, if necessary, to modify them during the test phase. Microcomputers and programs can thus be used under largely realistic conditions to be tried out. The programs that have matured in the trial can then be used without any change in the fixed value memory provided for the respective microcomputer to be written. This option is a major benefit for task-specific Microcomputers, which are mostly part of task-specific controls and whose configuration and program set differ from case to case.

The test auxiliary memory block saves when testing a microcomputer adding a second microcomputer or using a larger one Computer on which the configuration to be tested could be simulated.

The test auxiliary memory block can also be connected to a microcomputer Location and is therefore a simple tool for subsequent program modifications or later program changes.

An embodiment of the invention is described below with reference to the drawing explained in more detail.

1 shows the essential components of a test auxiliary memory block.

We see in Fig. 1 as essential components of a test auxiliary memory block the address converter AW, the memory selection module SPW, the read-write memory TRAM, the load program memory LROM, the potential supply rail POT, the outer one with address bar A connected to the microcomputer, which is connected to the microcomputer in connection standing control signal rail C connected to the microcomputer related data rail D, the inner address rail B, the switch-on signal rails ERAM and EROM.

The address signals generated by the microcomputer are sent to the address converter AW via the outer address rail A supplied and converted, the transformed address signals are routed to the inner address rail B.

The simple address converter AW shown in Fig. 1 has two Address transformation functions that use a #Flipflop DFF and two signal locks S1, S2 can be implemented with three-valued outputs.

The one address transformation function in which the address signal from the outer line A15 via the lock S2 to the inner line B15 transforms the address signals sent by the microcomputer identically, thus does not change any of them.

The other address transformation function that uses the address signal from the outer line A15 passed through the lock S1 to the inner line B15 is, negates signal A15 and leaves all other address signals unchanged. That #Flipflop DFF makes one of the two signal locks S1 or S2 permeable and puts the exit of the others in the uninvolved state. Since the negated Output of the flip-flop DFF is connected to its data input, causes an in Rising voltage edge reaching its clock input causes a change of state of the Flip-flops and thus a change in the address transformation function of the address converter.

The clock input of the flip-flop DFF is connected to a line of the control signal rail C connected.

Provided that the read-write memory is used for the identical address transformation TRAM the signal value A15 = 0 and the load program memory LROM the signal value A15 = 1 is assigned, the other address transformation assigns the read / write memory TRAM the signal value A15 = 1 and the load program memory LROM the signal value A15 I O too.

Each transformed according to one of the two functions Address signals reach the memory selection module SPW via the inner address rail B. This decodes the address signals, takes control signals from the control signal rail C. and generates switch-on signals at the right time for the respective addressed memory and places this on the signal rail ERAM or EROM. The memories TRAM and LROM transformed address signals are supplied from the inner address rail B, the read-write memory TRAM and control signals from rail C.

Both memories are connected to the data rail D.

In the case of memory reading, the user sets the memory selection module activated memory transfers its addressed memory content to the data rail D, which feeds it to the microcomputer. In the case of memory writing, what through If a control signal is defined on C, the one activated by the memory selection module takes Read / write memory the data set on the data rail D by the microcomputer into its addressed memory location.

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Claims (4)

PATENT CLAIMS W test auxiliary memory block for microcomputers thereby not shown, udli it is operated electrically and connected to a microcomputer can be connected that it receives address signals from the connected microcomputer and can receive control signals that it has a read-write memory, which can store data signals received from the connected microcomputer and which can send stored data signals to the connected microcomputer, that it has a read-only memory which is able to save program data to the connected microcomputer, with the help of which the microcomputer reads write memory of the test auxiliary memory block can load that it has an address converter with which it converts the address signals received from the connected microcomputer before they act on his memory that he is responsible for the address conversion in his address converter has a lot of address transformation functions available, with control signals it can be determined which address transformation function is used, that by exchanging the effective address transformation function, the assignment the address signals sent by the microcomputer to its read-write memory and can change to its read-only memory. 2. Auxiliary test memory block according to claim 1, characterized in that g e k e n n z E i c h n e t that it has a memory selection module, the converted address signals and control signals are supplied and switch-on signals are supplied to the signals supplied from these generated for the memories of the test auxiliary memory block. 3. Test auxiliary storage block according to claim 1, characterized in that g e k e n n z e i c h n e t that it has a signal buffer module, with the help of which the connected Microcomputer can accept data from a peripheral data reader. 4. Auxiliary test memory block according to claim 1, characterized in that g e k e n n z e i c h n e t that it has a signal buffer module, with the help of which the connected Microcomputer can send data to a peripheral data input device.