DE2631285C2 - Static semiconductor memory cell - Google Patents

Abstract

The object of the present invention is to provide a static memory element that can only be implemented with a simple MOS process and an additional full-area implantation. The memory element according to the invention essentially consists of a voltage-controlled negative differential resistor, a load element and a selection transistor. The negative resistance consists of a MOS transistor, a bipolar transistor, a PN junction and two resistors. The essential advantage of the memory element according to the invention is that it consists essentially of only one transistor and one selection transistor, since the bipolar transistor is given by the distance between two diffusion regions. Another advantage of the invention is that power is only consumed in one logical state. With a corresponding control, a large readout stroke can advantageously be achieved. ...ETC

Description

a) that the negative differential resistance (5) is formed by

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- That a high-resistance semiconducting substrate (4) is provided on the upper part of which is area is arranged a region (40) which is highly doped with respect to the substrate and which in the same way but more highly doped is ti j the substrate (4),

- That on the surface of the highly doped area (40) three opposite to the highly doped region (40) doped wells (17, 18, 21) are provided which extend through the highly doped area (40) to the substrate (4),

- That a first (17) of these wells the drain region (17) and a second (18) these wells represent the source region of a MOS transistor (1), with between the drain region and the Source area is the channel zone of the MOS transistor (Ϊ) is arranged,

- That above the channel zone by an electrically insulating layer (19) of the highly doped area (40) separated a gate electrode (11) of the MOS transistor (1) is provided,

- That the drain region (17) has a drain electrode (12) with a node (14) in Is connected and that the source region (18) via a source electrode (43) to a first terminal (16) in Connected,

- That the source region (18) of the MOS transistor (1) simultaneously represents the emitter area of a bipolar transistor (2),

- That the third (21) of said tubs is the collector area of this bipolar Represents a transistor, the collector region (21) being replaced by a base region (25) is separated from the emitter region (18),

- That the collector area (21) is provided with a Koliektorelectrode (22) which is connected to the gate electrode (11) of the MOS transistor (1) via a conductor track (15),

- That the collector electrode (22) has a resistor (3) with a second connection (31) is connected,

- That the base region (25) via the substrate (4) and a substrate electrode (23) with a substrate connection (24) is connected,

c) that via the load element (7) the node (14) of the negative differential resistance (5) is connected to the second connection (31),

d) that via the selection transistor (6,63). whose Gate electrode is connected to a word line (61, 64), either the node (14) of the negative differential resistance (5) or the gate electrode (11) of the MOS transistor (1) of the negative differential resistance (5) is connected to a bit line (62).

2. Static semiconductor memory cell according to claim 1, characterized in that the substrate (4) is a high-resistance p- (n +) -conductive substrate, that the highly doped region (40) is a p ⁺ (n ⁺ ) -conductive region and that the drain region (17), the source region (18) and the collector region (21) are n ⁺ (p ⁺ ) -diffused wells.

3. Static semiconductor memory cell according to claim 1 or 2, characterized in that the high-resistance substrate (4) is a 20 ohm · cm substrate with a charge carrier concentration of about 8 × 10 ¹⁴ cm ^-3 .

4. Static semiconductor memory cell according to one of claims 1 to 3, characterized in that the highly doped region (40) has a charge carrier ^{concentration} of 5 x 10 16 cm ^-3 .

5. Static semiconductor memory cell according to one of claims 1 to 4, characterized in that the highly doped region (40) by ion implantation, by diffusion or by applying a highly doped epitaxial layer is made.

6. Static semiconductor memory cell according to claim 5, characterized in that the highly doped Area (40) by means of an ion implantation step by introducing boron or Phosphorus is made.

7. Static semi-conductor memory after a of Claims 1 to 6, characterized in that the load element (7) is a MOS field effect transistor is of the enhancement type, the gate terminal (72) being connected to the drain terminal.

8. Static semiconductor memory cell according to one of claims 1 to 6, characterized in that the load element (7) is a MOS field effect transistor of the depletion type, the gate terminal (72) is connected to the source terminal, and wherein the channel area is counter-doped.

9. Static semiconductor memory cell according to one of claims 1 to 6, characterized in that the load element (7) consists of an implanted resistance track.

b) that the negative differential resistance (5) between a selection transistor (6, 63) and a load element (7) is connected.

65 The invention relates to a static semiconductor memory cell according to the preamble of claim 1.

Such a semiconductor memory cell is known from DE-OS 2043065.

A negative differential resistor produced using integrated circuit technology, consisting of an in a semiconductor substrate provided vertical bipolar transistor and a MOS transistor, is from IBM Techn. Disclosure Bulletin, Vol. 17, No. 4, Sept. 1974, p. 1041. It is in the Base region of the bipolar transistor next to the

Emitter region inserted a further semiconductor region that has the same conductivity type as the emitter region. The emitter region simultaneously forms the source region of the MOS transistor, the further semiconductor region the drainage area. The part of the base region lying between the source and drain regions is from covered by an insulated gate connected to a collector terminal. The other semiconductor area is connected to a base connection of the bipolar transistor.

A pnpn four-layer semiconductor memory cell with a negative resistance characteristic is described in DE-OS 2149761. It has a semiconductor body on, on the surface of which the two pn junctions between the first three layers pass through one from the surface through one diffused in Charge carrier capture centers provided insulating layer separated gate electrode are covered together. A gate voltage applied to the gate electrode causes a corresponding amount of Load carriers from the second shift are found in the trapping centers is being held. Even after the applied gate voltage has changed, a current begins to flow between two electrodes applied to the first and fourth layer only at such a value as that applied to them the latter applied voltage that a threshold value determined by the amount of stored in the insulating layer Load carrier is determined is exceeded. Thus, when a gate voltage is applied resulting threshold value saved by the properties of the insulating layer.

The object of the present invention is to provide a static semiconductor memory cell of the initially mentioned Specify mentioned type, which only with a simple MOS process and an additional full-area Implantation is feasible.

This object is achieved by the features listed in the characterizing part of claim 1 solved.

In addition to their: simple manufacturability stands out the semiconductor memory cell according to the invention also characterized in that only in a logical state power is consumed.

With a corresponding control, a large readout stroke can advantageously be achieved.

In the following the invention is based on the drawing explained in more detail.

Fig. 1 shows the circuit diagram of a static memory element according to the invention.

F i g. 2 shows a schematic representation of a cross section by the negative resistance of the memory element according to FIG. 1.

Fig. 3 shows a schematic representation of the circuit diagram of a further static according to the invention Storage element.

4 shows the characteristics of an inventive Storage element.

FIG. 5 shows a schematic representation of a cross section through the storage element according to FIG Fig. 1.

The F i g. 6 shows the layout of an inventive one Storage element according to FIG. 1.

As can be seen from Fig. 1, the memory element according to the invention consists essentially of a voltage-controlled negative differential resistor 5, a load element 7 and a selection transistor 6. The negative resistor 5 consists of a MOS transistor 1, a bipolar transistor 2, a pn junction 42 and resistors 3 and 41, which are connected together in the manner shown in FIG. The voltage-controlled negative differential resistance is measured between points 14 and 16. The drain connection 12 of the MOS transistor 1 is connected to the point 14. The source connection 13 of the MOS transistor 1 is connected to the connection 16, the potential of which corresponds approximately to the potential at the connection 24. The gate of the MOS transistor 1 can be controlled via a resistor 3 which for this purpose is arranged between the gate terminal 11 of the MOS transistor 1 and a terminal 31. The gate terminal 11 of the MOS transistor 1 is connected to the terminal 16 via the collector-emitter circuit of the bipolar transistor 2. The base connection of the bipolar transistor 2 is connected to the point 14 via a diode 42. The base 25 of the bipolar transistor 2 can be controlled via the resistor 43 which is connected on the one hand to the base 25 of the bipolar transistor 2 and on the other hand to the terminal TA.

In FIG. 2 shows a cross section through a negative resistor 5. This is built up on a semiconducting substrate, preferably on a silicon substrate 4. For example, this silicon substrate 4 is a high-resistance base material with doping ρ = 8 × 10 ¹⁴ cm ^-3 . On the surface of the substrate 4, the p-doping in the region 40 is increased, for example to / j ⁺ = 5 10 ¹⁶ cm ^-3 , preferably by means of an ion implantation step, for example by introducing boron ions. The -doped wells 17, 18 and 21 are now introduced into the substrate 4 and into the region 40 by means of a diffusion process. The diffusion region 17 serves as the drain region of the MOS transistor 1. A drain electrode 12, which is connected to the point 14, is arranged on the surface of this drain region. The source region 18 of the MOS transistor 1 is at a distance from the drain region 17, which forms the channel region. The gate electrode 11 of the MOS transistor 1 is arranged above the channel zone of the MOS transistor 1 through an electrically insulating layer 19, which is preferably an S1O2 layer. The source region 18 of the MOS transistor 1 also serves as the emitter region of the bipolar npn transistor 2. The diffusion region 21 serves as the collector region of the bipolar npn transistor 2. It is provided with an electrode 22 which is connected to the gate electrode 11 of the via a connection 15 MOS transistor 1 is electrically connected. The base 25 of the bipolar transistor is located between the collector region 21 and the emitter region 18 or the source region. The resistor 3 already described in connection with FIG. 1 is connected to the collector electrode 22. The substrate 4 has an electrode 23 with a connection 24. Between this electrode 23 and the base 25 of the bipolar npn transistor 2 there is the resistor 41 (FIG. 1), which is formed by the high-impedance p-substrate. The diode 42 shown in FIG. 1 is formed by the pn junction between the regions 40 and 4 and the drain region 17 of the MOS transistor 1.

The function of the negative resistance in connection with FIG. 4 will be explained below. At the other connection ZX , the voltage Uc, is applied to the connection 24, the voltage U ^ b and to the connection 14, the voltage Lb. The current I ₀ flows from connection 14 to connection 16 . In Fig. 4 is

a // ri / o characteristic curve for a given substrate voltage U ^ of, for example, + 0.23 V and for a given gate voltage Ua of, for example, 4 V is shown. Up to a certain drain voltage U ₀ <Ubd, which depends on the doping of the silicon in the region 40, the arrangement behaves like a normal MOS transistor, at the gate of which the voltage Ug is applied. In the family of characteristics in FIG. 4, this area corresponds to the area labeled A there. From a drain voltage of Ud > Ubd (area B in FIG. 4), a current path is formed between the drain region 17 and the substrate 4, which is generated, for example, by an avalanche breakdown in the drain region. As a result of the voltage drop in the high-resistance substrate, that is to say at the resistor 41, the potential in the vicinity of the switching arrangement increases. The diffused source region 18 begins

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15 wise n-channel enhancement type MOS transistors are used. In this case, the gate electrode of each of these transistors is connected to the drain terminal. When using transistors of the depletion type, the gate electrode is connected to the source terminal. In FIG. 5, the cross section through a memory element consisting of the negative resistor 5, the load element 7 and the selection transistor 6 is shown. The resistor 3 and the load element 7 are field effect transistors of the enhancement type. Details of FIG. 5, which have already been described in connection with FIGS. 1 and 2, have the corresponding reference numerals. Implanted resistance tracks can also serve as load elements.

The potential at the terminal 16 (Fig. 1) is advantageously chosen so that it is about the substrate potential

, ie to inject electrons tisl ents ⁿ Richt dss z. B. - 5 V betr2 ° sri can. This

which are captured by the collector area and connected to the terminal 31 via the resistor 3 Voltage source are dissipated. In this way, the potential at the electrode 11 is lowered and the MOS transistor blocked.

By connecting a load element 7 and a selection transistor 6 to the negative resistor 5 described in more detail above, one arrives at the static storage element according to the invention (FIG. 1). The selection transistor 6, which is preferably one. MOS transistor is on the one hand connected to the point 14 of the negative resistor 5 and on the other hand to a bit line 62. The gate electrode of the selection transistor 6 is connected to a word line 61. The load element 7, which is connected on the one hand to the point 14, on the other hand is advantageously connected to the terminal 31 and thus to the voltage Ug . As can be seen from FIG. 4, the characteristic curve Kl results for the load element. This characteristic curve Kl intersects the already described characteristic curve λ "5 of the negative resistance at points S1, L and 52. The points S1 and S2 represent stable states and the point L represents an unstable state.

As shown in FIG. 3, the bit line 62 also be connected to point 11 via a selection transistor 63. The selection transistor then becomes 63 controlled via word line 64. Details of FIG. 3, which have already been used in connection with 1 have been described with the corresponding reference numerals.

The memory element according to the invention according to the Fig. 1 is selected in that a potential is applied to the word line 6J, which the selection transistor 6 opens. A potential corresponding to the information to be written is applied via the bit line 62 applied, which sets the storage element either in the stable point S1 or in the stable point S2. When reading out, the selection transistor 6 is again in the conductive state via the word line 61 switched. By means of a regeneration circuit 8 connected to the bit line 62, the at the Point 14 evaluates the applied potential or evaluates the state of conductivity of transistor 1.

Advantageously, the resistor 3 and the load element 7 are also MOS transistors of the enrichment type or the depletion type or around implanted resistors. In connection with the example given above for the construction of the negative resistance are preferred Circuits then retain their properties, whereby it is also ensured that the potential at terminal 16 and point 25 is approximately the same. 6 shows a plan view of the arrangement according to FIG. 5. Details of the F i g. 6, which have already been described in connection with FIG. 5, bear the corresponding reference symbols. As can be seen from FIG. 5, the field effect transistors are the form the resistor 3 and the load element 7, also built up in the layer 40 and in the substrate 4. Resistors 3 and 7 are depletion type transistors. The memory element is advantageously ' 6 constructed in an Al gate technology with self-aligning gates. It mean hatched areas diffusion areas, areas outlined by dashed lines aluminum conductor tracks or Electrodes, areas bordered with continuous lines, gate oxide layers and areas with diagonals Contact hole etchings. The areas outlined by dash-dotted lines represent thin oxide areas.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: 1. Static semiconductor memory line with negative differential resistance, which by means of a Voltage control between a low-resistance state and a high-resistance state switchable or downshiftable, characterized in that