DE2534397A1 - Verfahren zum herstellen von festwertspeicher enthaltenden integrierten schaltungen - Google Patents

Verfahren zum herstellen von festwertspeicher enthaltenden integrierten schaltungen

Info

Publication number
DE2534397A1
DE2534397A1 DE19752534397 DE2534397A DE2534397A1 DE 2534397 A1 DE2534397 A1 DE 2534397A1 DE 19752534397 DE19752534397 DE 19752534397 DE 2534397 A DE2534397 A DE 2534397A DE 2534397 A1 DE2534397 A1 DE 2534397A1
Authority
DE
Germany
Prior art keywords
circuits
connections
passivating layer
layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752534397
Other languages
German (de)
English (en)
Inventor
Gene Stoddard Alberts
Paul Alden Farrar
Robert Lee Hallen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2534397A1 publication Critical patent/DE2534397A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H10W20/493—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H10P95/00—
    • H10W74/47—

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
DE19752534397 1974-09-30 1975-08-01 Verfahren zum herstellen von festwertspeicher enthaltenden integrierten schaltungen Withdrawn DE2534397A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/510,667 US3959047A (en) 1974-09-30 1974-09-30 Method for constructing a rom for redundancy and other applications

Publications (1)

Publication Number Publication Date
DE2534397A1 true DE2534397A1 (de) 1976-04-22

Family

ID=24031678

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752534397 Withdrawn DE2534397A1 (de) 1974-09-30 1975-08-01 Verfahren zum herstellen von festwertspeicher enthaltenden integrierten schaltungen

Country Status (5)

Country Link
US (1) US3959047A (enExample)
JP (1) JPS5151294A (enExample)
DE (1) DE2534397A1 (enExample)
FR (1) FR2286505A1 (enExample)
GB (1) GB1517050A (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568659A (en) * 1978-11-20 1980-05-23 Hitachi Ltd Semiconductor device and manufacturing method thereof
US4229248A (en) * 1979-04-06 1980-10-21 Intel Magnetics, Inc. Process for forming bonding pads on magnetic bubble devices
US4589028A (en) * 1983-11-29 1986-05-13 Fuji Photo Film Co., Ltd. Defect concealing image sensing device
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
US5223735A (en) * 1988-09-30 1993-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same
US5200922A (en) * 1990-10-24 1993-04-06 Rao Kameswara K Redundancy circuit for high speed EPROM and flash memory devices
EP0563852A1 (en) * 1992-04-02 1993-10-06 Siemens Aktiengesellschaft Zag fuse for reduced blow-current applications
US5589706A (en) * 1995-05-31 1996-12-31 International Business Machines Corp. Fuse link structures through the addition of dummy structures
US6057221A (en) * 1997-04-03 2000-05-02 Massachusetts Institute Of Technology Laser-induced cutting of metal interconnect
ES2144946B1 (es) * 1998-03-10 2001-01-01 Mecanismos Aux Es Ind S L Unos perfeccionamientos en la proteccion de fets mediante pistas de pcb.
US6008523A (en) * 1998-08-26 1999-12-28 Siemens Aktiengesellschaft Electrical fuses with tight pitches and method of fabrication in semiconductors
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6219237B1 (en) 1998-08-31 2001-04-17 Micron Technology, Inc. Structure and method for an electronic assembly
US6424034B1 (en) 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
US6392296B1 (en) 1998-08-31 2002-05-21 Micron Technology, Inc. Silicon interposer with optical connections
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
US6255852B1 (en) 1999-02-09 2001-07-03 Micron Technology, Inc. Current mode signal interconnects and CMOS amplifier
US6844253B2 (en) 1999-02-19 2005-01-18 Micron Technology, Inc. Selective deposition of solder ball contacts
US7554829B2 (en) * 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6435396B1 (en) * 2000-04-10 2002-08-20 Micron Technology, Inc. Print head for ejecting liquid droplets
US6878396B2 (en) 2000-04-10 2005-04-12 Micron Technology, Inc. Micro C-4 semiconductor die and method for depositing connection sites thereon
US6635960B2 (en) 2001-08-30 2003-10-21 Micron Technology, Inc. Angled edge connections for multichip structures
US7101770B2 (en) * 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections
US7235457B2 (en) * 2002-03-13 2007-06-26 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects
US6828652B2 (en) 2002-05-07 2004-12-07 Infineon Technologies Ag Fuse structure for semiconductor device
US7347349B2 (en) * 2003-06-24 2008-03-25 Micron Technology, Inc. Apparatus and method for printing micro metal structures
US6960978B2 (en) * 2003-07-16 2005-11-01 Hewlett-Packard Development Company, L.P. Fuse structure
KR20060108662A (ko) * 2003-10-07 2006-10-18 주식회사 아도반테스토 테스트 프로그램 디버그 장치, 반도체 시험 장치, 테스트프로그램 디버그 방법, 및 시험 방법
US7485944B2 (en) * 2004-10-21 2009-02-03 International Business Machines Corporation Programmable electronic fuse
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE670213A (enExample) * 1964-09-30 1900-01-01
US3697318A (en) * 1967-05-23 1972-10-10 Ibm Monolithic integrated structure including fabrication thereof
GB1230421A (enExample) * 1967-09-15 1971-05-05
JPS4835778A (enExample) * 1971-09-09 1973-05-26
US3780320A (en) * 1971-12-20 1973-12-18 Ibm Schottky barrier diode read-only memory
US3740523A (en) * 1971-12-30 1973-06-19 Bell Telephone Labor Inc Encoding of read only memory by laser vaporization

Also Published As

Publication number Publication date
JPS5151294A (en) 1976-05-06
US3959047A (en) 1976-05-25
GB1517050A (en) 1978-07-05
FR2286505B1 (enExample) 1977-12-16
FR2286505A1 (fr) 1976-04-23

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee