DE2529448C2 - Circuit arrangement for converting NRZ signals into RZ signals, in particular for synchronous time division multiplexing - Google Patents

Description

When processing digital signals, the information is generally available as NRZ signals at the output of a circuit, since it is mostly used as an output stage a flip-flop is used as a buffer to maintain a fixed relationship between information bits and To ensure clock pulses. For some applications it is necessary to use the NRZ signals to convert further processing into data center signals.

From Electronics 1971.11. October, page 85 are NRZ- and RZ formats known for signals

One possible case of converting NRZ signals into RZ signals is e.g. B. the combination of two synchronous information flows of speed v, to a resulting information flow Φ2 according to

v ₂ = 2v ,.

If the time division multiplexing with bit-by-bit interleaving is used for the combination, an OR gate with two inputs is sufficient as a multiplexer with existing RZ signals if the RZ signals have a phase shift of π to one another.

Previously known methods for producing the RZ signals use AND gates to convert the NRZ signals into RZ signals, at one input of which the NRZ signals and at the second input either the clock or the inverse clock are applied. In this way, it is possible to produce two information flows with the same bit rate with N RZ signals, two information flows with RZ signals, whereby the phase shift of st results from the use of clock and inverted clock the data center signals cannot be easily established without further ado. As a result of the scatter with regard to the delay times of the components used, it cannot be ensured that the edges of the NRZ signals coincide exactly with clock edges. As a result, in addition to the desired RZ signals, false pulses occur which can only be avoided if the NRZ signals are corrected by suitable measures, e.g. B. via an adjustable delay line, can be shifted in time against the clock pulses (The TTL Data Book, 2nd edition, Texas Instruments Deutschland GmbH, Fig. 157 L 157 on page 318uhd Fig. S 157 on page 319).

In DE-OS 19 48 533 a circuit arrangement is for converting a first pulse train into a second pulse train in the B-code and with the double Bit repetition rate described. The code conversion and the doubling of the bit repetition rate at the The second pulse train takes place by means of clocked AND gates.

There is another possibility of generating two pulse trains with RZ signals shifted by π

therein, the NRZ signals initially with AND gates below Use of the information clock to convert into in-phase RZ signals and the required phase shift by delaying one signal. Because this delay is generally due to digital circuits is achieved, the above-mentioned difficulties arise due to the Scattering of the components. Even when using passive components for the delay are Temperature influences, & h. Term changes, not too avoid that there is always the risk of false pulses consists

In the TTL Cookbook, Texas Instruments, 1973 is on On pages 162-164 it is stated that the delay times of components vary and are therefore special Measures, e.g. B. Delays in clock and data lines are to be met when in switchgear Malfunctions due to different delay times of individual components can be avoided should.

In Valvo reports, Volume VIII, Issue 5, December 1967, Page 152 indicates that e.g. B. by chain-shaped successive logical operations run-time differences between several signals occur that can be achieved by synchronizing clock pulses and subsequent storage of so-called catch flip fiops let catch.

The invention largely avoids the aforementioned disadvantages, without any more effort in terms of To require circuit realization.

The circuit arrangement according to the invention is characterized according to the main claim that on second input of the AND or NAND gate is the NRZ information to be converted and that the The clock input of the D flip-flop to a working clock is the frequency of the clock compared to that of the NRZ information to be converted is doubled

This has the advantage that the pulse width of the received RZ signals is defined by the period of the working cycle Γ and that its phase position no longer has to be adapted to the phase position of the NRZ signals to be processed, as in the prior art. For error-free processing of NRZ signals, it is sufficient that the switching edge of the working cycle T lies within each NRZ pulse to be processed. This is given by the fact that the frequency of the working cycle T is doubled compared to that of the NRZ signals.

For the acceptance of the data center information there are different versions depending on the gate used. When using a NAND gate, its first input is connected to the non-inverted output of the D flip-flops connected and the RZ information is on inverted output of the D flip-flop removable (claim 2, Fig. 3).

When using a NAND gate, its first input is connected to the inverted output of the D flip-flop connected and the RZ information can be removed from the non-inverted output of the D flip-flop (claim J).

A preferred development of the invention F ⁷ IiT. 4. flinsprucn 5; ;: e-, tatet. during operation

process this is to be generated with a simple output bit rate.

In the following, with reference to FIG. 1 to 4 three circuit arrangements according to the invention in more detail explained it shows

Fig. 1 shows a circuit arrangement for generating RZ signals from NRZ signals,

F i g. 2 timing diagrams to explain the mode of operation the circuit arrangement according to FIG. 1,

F i g. 3 shows a circuit arrangement for generating two pulse sequences which are phase-shifted by π with respect to one another and with RZ signals from two synchronous NRZ signals π and

4 shows a circuit arrangement for combining two pulse trains phase-shifted by π with RZ signals to form an NRZ signal which allows a simple switchover between half and the full output bit rate of a multiplexer

The in F i g. 1 illustrated circuit arrangement is used for converting NRZ signals into RZ signals. It consists essentially of a D flip-flop 1 as Memory and a NAND gate. In addition to clocked feedback D-flip-flops, the memory is also used clocked JK flip-flops into consideration, which if suitable Wiring then work like D flip-flops.

A D flip-flop is known to be a delay or delay flip-flop with only one input. The information supplied to this input is transferred to the D flip-flop and appears with a delay of a maximum of one clock period at the non- inverted output Q or inverted at the output Q. The function of a feedback D flip-flop can be used to solve the present problem If the inputs are wired accordingly, they can also be achieved with a so-called JK flip-flop, as can be seen from the following truth table

time K (η + 1) η L. Q J H Q _n 1. L. L. L. 2. L. H H 3. H 4th H

.. ' i * \ <i \' ■■: ■. . ■ ·; Tä.-fjen wabi "·»? '^ To convert: in the development two syncivone NRZ signals / 1 »ι one. ^ N,.;..> KZ-aignalfnlgy j' -.//2 with

g j

• erccu.euer Aüigar.g> i unite to nest 'the ci: -. R. if only t me NRZ signal sequence 71 / u To achieve the desired function, the NRZ information must be applied to one input, while the other input K is constantly at H potential. With this connection, the JK flip-flop can only assume states 2 or 4 of the truth table, which correspond exactly to the function of the feedback D flip-flop described below. In the following, the description of the circuit arrangement is therefore based on a feedback DF! Ip flop. A working cycle T of twice the frequency of the cycle belonging to the NRZ signal is to be applied to its clock input.

D ^ an output Q of the D flip-flop 1 is via the

an input of the NAND gate is coupled to input D. The ^ wide entrance of the NAND gate ■ / ground the NRZ information JNRZ offered; at the inverted output Q of the D flip-flop 1 are then

the data center information JRZ is available.

The mode of operation of the circuit arrangement according to FIG. 1 explained in more detail It is known that a D-rip-flop can be used as a divider if the output Q is fed back to the input D. At the other output Q there is then a cycle of half the frequency compared to the working cycle at the cycle input (Motorola: MECL Integrated Circuits Data Book p. 5 -101).

In the circuit arrangement according to FIG. 1 is fed back from the output because of the use of a NAND gate in the feedback branch. As long as the NRZ information JNRZ is "L" , the output of the NAND gate is held at "! -!" Potential and thus output Q is held at "L" potential. If the NRZ information changes to "! -!" Potential, the D flip-flop 1 acts as a coaster counter. Since the frequency of the work cycle T is twice as high as that of the. The clock belonging to the NRZ information is obtained at the output Q of the D flip-flop 1 for this case the clock of the NRZ information, which at the same time represents the RZ information JRZ . The ideal case therefore applies to the temporal position of the switching working cycle edge in relation to an edge of the information

15th

20th

t =

4 / '

25th

if / is used to denote the pulse sequence frequency of the NRZ information. The circuit still works properly in the event of deviations δ from this setpoint of

so that results for /

2 /

35

40

Even if this condition is not met, there are still no errors in the conversion. There is only a permissible phase shift of π in the RZ information.

3 shows a further development of the invention for converting two mutually synchronous NRZ items of information into two RZ items of information that are phase shifted by π with respect to one another. To convert the two NRZ signals into RZ signals, two identical circuit arrangements as shown in FIG. 1 provided. The phase shift by π is generated according to claim 3 by a further memory 3 in a branch of the circuit (shift register). This further memory can preferably also be a D flip-flop again.

F i g. 4 shows a circuit arrangement which can optionally be switched to two operating states by means of a switch S and which serves to either combine the two synchronous NRZ signals / 1 and / 2 to be processed at the output into a single new NRZ signal sequence Ji / J2 with doubled output bit rate, ie nesting, or in the second operating state, if only a single NRZ signal sequence Ji is to be processed, only to generate a new NRZ signal sequence / 1 corresponding to this with a single output bit rate at the same output as in the first operating state.

In order to generate the required delay of exactly the same amount in each case, ie the phase shift of the NRZ signal / 2 in the first operating case or the first half of each NRZ signal JX in the second operating case, in each case by π according to FIG. 4 two further memories 4 and 3 designed as D flip-flops are provided, of which only one memory 3 or 4 assigned to this is enabled in each operating state, while the other further memory remains permanently set. For this purpose, each additional memory 3, 4 has a set input pr .

According to FIG. 4, the NRZ signals Ji and / 2 to be processed in the first operating state are converted into negated RZ signals Ji, / 2 in the manner previously described; in the first further memory 3, the RZ signal / 2 is then converted to the RZ signal Ji each phase shifted and thus appears as signal J 2 *. Via the inputs 2, 3 of a NAND gate LJ, which acts as an OR gate for the two negated RZ signals Jl and J 2 *, which are phase-shifted by π , these are linked to one another, namely interleaved in time. The input LJi of the NAND- Gate t / is held at "H" potential for this purpose, in that the second additional memory 4 connected upstream of it remains permanently set by its set input pr by means of switch 5 which switches through "L" potential. At the same time, the first additional memory 3 is received at its set input pr via an inverter 6 "H" potential and is thus enabled.

If, on the other hand, only a single NRZ signal Ji is to be processed in the second operating state, the second memory 4 is released by disabling the switch S and, at the same time, the first memory 3 is permanently set via the inverter 6 NAND gate i / “H” potential, since the first further memory 3 connected upstream of this input LJ 3 is now held. The inputs Ui and LJ2 of the NAND gate LJ thus receive the negated RZ signal / 1 or a negated RZ signal Ji * which is phase shifted by π , so that a complete NRZ information / 1 is again present at the output of the gate LJ simple output bit rate results

The negated RZ signals / 1 * in the second operating state and / 2 * in the first operating state have the same phase position, which is phase shifted by π, so that the circuit arrangement according to FIG. 4 can also be switched from one state to the other during operation if necessary

In this way it is possible to automatically adapt the output bit rates to the capacity required in each case, if necessary. In particular, new NRZ information / HJ 2 with a doubled output bit rate is received in the first operating state.

A D flip-flop 5 at the output of the circuit arrangement is used to free the NRZ signal occurring at the output of the NAND gate U on the one hand from so- _{called T} spikes and on the other hand to clock it and thus a clear connection between the output information and the Work cycle to restore.

1 sheet of drawings

Claims (6)

Patent claims: - 1. Circuit arrangement for converting N RZ signals into RZ signals, especially for synchronous time division multiplexing, with a D flip-flop (1) and an AND or NAND gate, the first input of which with one of the two outputs of the D-flip-flops (1) and the output of which is connected to the input of the D-flip-flop (1), characterized in that at the second input of the AND or NAND gate the NRZ information to be converted ( JNRZ) and that the clock input of the D flip-flop (1) is connected to a working clock (T) , the frequency of which is doubled compared to that of the clock of the NRZ information to be converted. 2. Circuit arrangement according to claim 1, characterized in that when a NAND gate is used, its first input is connected to the non-inverted output (Q) of the D flip-flop (1), and that the JIZ information (JRZ) is connected to the inverted one Output (Q) of the D flip-flop (1) can be removed (FIG. 1). 3. Circuit arrangement according to claim 1, characterized in that when using a AND gate whose first input is connected to the inverted output of the D-FIip-flop and that the RZ information can be removed from the non-inverted output of the D-FIip-flop. 4. Circuit arrangement according to claim 2 or 3 for the conversion of two NRZ information into two RZ information which is phase-shifted by π with respect to one another, characterized in that at the output (Q) of one (2) of two together on the working cycle (T) lying D-flip-flops (1,2) a memory (3) lying on the same working cycle (T) , preferably a further D-FJip-flop, is connected, at whose output (Q) the compared to the first RZ information η phase-shifted «o second data center information (JRZ) can be removed (Fig. 3). 5. Circuit arrangement according to claim 4, characterized in that to combine two mutually by π phase-shifted RZ-Si- «5 signals (J \ and J2 *) to a new NRZ signal (Jt / J 2 or Jl) optionally doubled in first or single output bit rate in the second operating state at the output (Q) of each D flip-flop (1,2) a further memory (4, 3), preferably designed as a D-flip-flop, is connected that in the first or in the second operating state either the first (3) or the second by a corresponding through-switching or blocking switch (S) (4) further memories can be released and at the same time the other further memory can be permanently set so that an output (Q) of each further memory (3, 4) is connected to an input (Ul, t / 3) of a further NAND gate (U) is set, the average input (U2) on the feedback training ⁶ <> output (Q) of the first D-flip-flop (1), and that the output of the NAND gate (U) to one another on the same working cycle ( 7} lying memory (5) is connected, at whose output (Q) be \ switched- through switch (S) the NRZ information (Ji, / 2) with double the bit rate (Jl, Jl), on the other hand, when the switch (S) is blocked NRZ information (Jl) with a single output bit rate decreases is bar (Fig. 4). 6. Circuit arrangement according to claim 5, characterized in that in the first operating state the switch (S) "L" potential switches through directly to the set input (pr) of the second further memory (4), which thus remains permanently set, while at the same time the set input (pr) of the other - ie the first - further memory (3) is connected to "H" potential via an inverter (6), so that the first further memory (3) is enabled