DE2523372A1 - INPUT / OUTPUT PORT CONTROL DEVICE - Google Patents

Description

Böblingen, May 23, 19 ru-fe

Applicant: International Business Machines

; Corporation, Armonk, N.Y. 10504

Official file number: New registration
File number of the applicant: YO 973 040

Input / output port controller

The device relates to an input / output port control device according to the preamble of claim 1.

In computer systems in general and in small systems In particular, it is desirable to reduce the overall machine overhead required by the system at a given level the machine performance is required. The external units such as data entry stations, video terminals or Data lines connecting card readers to a central processor typically require separate I / O connector connections for each data line. In modern computers with

With their highly integrated circuit technology, these switching modules are known to lead to the outside world in number

Limited circuit connections or pins that can be attached to such a module. By using the same Data lines for input and output could be the

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Number of connections required can be reduced by half. at However, until now it has generally not been possible in large and very fast computer systems to use the same data lines both for reading in To use data in the system as well as for reading out from the system, since then many operations are held up until one is currently running Operation is finished. Although such a wait is necessary with a central memory or other shared functional unit, it is not so critical within the central unit, since modern computers have very fast memory circuits which carry out the required operations can perform in extremely short times. For smaller and slower computers, however, where the cost and manufacturing capabilities If the main factors are, and time may be a secondary factor, it is possible to use bi-directional data lines or half-duplex operation to consider.

Thanks to modern integrated circuits and microelectronic technology the construction of relatively small and inexpensive computers became possible, the considerably higher operating speeds without any substantial increase allow the construction costs. Previously, such computers required two busses however, a large number of connectors to connect the computer with both the data input and the data output lines

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connect to. This point poses serious problems when the highly integrated circuit technology is used in the computer will. This problem is to be solved by the present invention.

It is therefore the object of the present invention to provide an input / To provide output port control means which allow the connection of a bidirectional data input / output bus a central computer system which internally has separate source and destination busses.

The solution consists in the characterizing part of the claim.

An embodiment of the invention is shown in the drawings and is described in more detail below. Show it:

1 shows the arrangement in a functional block diagram

the I / O connection device with several connected to a bidirectional I / O bus Adapters, with several external units connected to each such adapter,

2 shows the composition of FIGS. 2A and 2B and

Pign. 2A and 2B a combined logic diagram and function block ! diagram with details of the input /

i output port control device necessary

'' Machine equipments.

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The object of the invention is generally achieved by a data processing system solved, which contains a plurality of input / output units that are connected to a central processing unit by means of one of a plurality of bidirectional Data lines and control lines existing bus and are connected to facilities that enable the bidirectional operation of the aforementioned Data lines between selected input / output units and the control unit through a controllable assignment of the data function of the aforementioned Effect data lines for addressing and for the transmission of commands and data. The device includes a first controlled driver gate for the optional connection of the I / O data lines with a processor-internal central source busbar for the delivery of selected ones Inputs to internal functional units. A second controlled driver gate circuit is provided for the optional connection of a processor-internal central destination bus with I / O data lines, with the outputs internal functional units can optionally be connected to the destination manifold. An input / output control subsystem is also provided in the said processor, which on I / O -programmed instructions or is responsive to program interruptions caused by an external entity or to priority-controlled cycle allocation requests, and which said driver gate circuits and the selection of inputs to the functional units and of outputs to these units of the system and

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and actuated to the external units and all desired I / O operations performs.

The concept of the input / output boundary point control subsystem can be found in a central computer system with at least two data collecting lines can be installed. There will only be those individual parts of the general components of the central system, which are absolutely necessary. These include one used as a microprogram memory in the exemplary embodiment Read-only memory and the associated decoding circuit, as well as the central one System memory from and into which I / O data is read, as well as the internal source manifold and internal destination manifold.

The exemplary embodiment described shows one operated by a data station System. In such a system, the various data stations such as key input devices or credit card readers or the like are practically in control Facilities the operation of the system by signaling interruptions or by requests for a priority-controlled cycle assignment at predetermined priority levels.

The present I / O connection control device works under program control or in priority-controlled cycle assignment, whereby it is through devices

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in the external units controlled, which the memory faster than usual can use normally programmed I / O devices.

In Fig. 1, the central memory 10 is connected to the central processor 12, the one system with two internal data busses, namely a separate source manifold and a separate destination manifold forms. In the lower part of block 12, the I / O limit point control 14 is shown as part of the central processor, since the I / O limit point control also uses the system microprogram memory, which in the exemplary embodiment shown is a read-only memory (ROS). The output signals from the read-only memory decoder and the control unit sets the necessary control and hold circuits of the I / O connection control device. They serve the different To lock license plate lines, which lead to the adapter units 16 of the external devices, by means of which the external devices 18 with the bidirectional Main data bus line 2 0 are connected. In addition, there is a control bus line 22 between the I / O limit control unit 14 and the Adapter 16 switched. In the present exemplary embodiment, there are fixed, parallel lines to the adapters, which are not like the data bus line 20 can be operated bidirectionally.

Using the system described, it enables I / O boundary control the central processor, in connection with certain units

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occur, and certain units can connect to the central processor through the necessary control circuits via the I / O data bus on the source bus or communicated from the destination bus to the data bus as needed, as required by the current operation. Also included are the controls that prevent conflicts from, for example, one unit or the processor from concurrently with another Tried to send unit.

Before the detailed description of the operation of the specifically described Plant parts, which are shown in the block diagram of Fig. 2, first follows a general description of the operation of the device .

The present I / O connection control device is intended to have several functions. to be fulfilled. On the one hand, the input and the output should be controlled asynchronously. Second, the I / O control mechanism and the I / O bus can be used jointly based on control signals from both the programmed input / output and the priority-controlled Cycle assignment as well as from the program interrupt signals.

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Figures 2, 2A and 2B show the I / O terminal control circuit of the Central processor and the I / O bus with one connected Adapter. The I / O bus contains 16 bidirectional lines, one high byte and a low byte, each 8 bits wide. When the system does not have a priority cycle assignment or a programmed I / O operation executes, the low byte of the I / O bus is used to Send interrupt requests from the adapter to the central processor. When the I / O bus is polled by the system for interrupts then the TD indicator is used to switch the interruption ε request holding circuits prevented during the query interval. To a programmed I / O instruction or a priority-controlled cycle assignment To begin with, the I / O flag is raised early in these operations as a signal voltage on the appropriate line to the I / O bus to free (i.e. the interrupt requests are blocked).

The central processor is micro-program controlled. Every operation has one Start address (instruction decoding) in read-only memory, which can only be followed by a fixed number of concatenated instruction words until the instruction is ready is executed. The ROS register output sends control signals over the tag lines within the machine for fixed time intervals off, off

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however, take I / O operations and priority-controlled cycle assignments. For these operations, the ROS is locked REG remote turn-on to the exit of the ^Ti ihaltes of ROS register to prevent long, until certain conditions are met by the adapter. This allows faster adapters to perform these operations and slower adapters to slower adapters. There is a limit to how long the system waits for a response to an adapter, and when this time limit is reached the central processor goes into the machine control sequence (MCK). The hold indicator is raised to indicate this operation to the adapter. It is a troubleshooting routine that detects and responds to some type of malfunction, for example by attempting to retry the last operation.

The central processor can operate with either one or two bytes of data over the I / O bus, depending on the type of device and / or operation. There are two programmed I / O instructions: IO and IOH. With IO, data bytes can be read or written in connection with a byte or half-word unit (HW), while IOH can only be used with a half-word unit. A Έ / h write operation takes data from memory and sends it to the adapter over the I / O bus. An I / O read operation takes data from the I / O bus and stores it

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them in memory.

In both instructions TO and IOH, the address of the unit and the Koirimando (read or write) must be sent to the external unit before data can be read or written. The address and the command are each byte information and must therefore be sent individually to byte units, whereas they can be sent simultaneously for HW units. As an example, assume that an IO write instruction is required for a byte unit. The instruction decoder sends the first command word from the read-only memory for the ΙΟ instruction. During these initial signals, the I / O flag and byte flag lines are activated to clear the I / O bus and the gate to the I / O bus from the buffer output is opened. The memory word in the location in memory specified by the instruction is sent from memory to the buffer and the output of the buffer is connected to the I / O bus. The memory word contains the address of the unit in the high byte (bits 0 to 7) and the command in the low byte (bits 8 to 15). The adapter responds to the I / O flag by dropping VB (valid byte-byte adapter), indicating that program interrupts are being kept away from the I / O bus and that the adapter is a byte adapter. The central processor then raises the TA flag to

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'44.

tell the adapter that the address of a unit is on the high byte the I / O bus (and in the same way that the command for a HW adapter is on the low byte). The adapter then responds by raising VB to indicate that a valid address was sent from the central processor. This return of the validity signal resets the TA identifier and now the command is transferred to the high byte from the buffer and onto the I / O bus. Of the Adapter must also switch off VB because the TA indicator has been reset. When VB is turned off, the TC flag is raised to notify the adapter that the command is on the high byte of the I / O bus lies. VB is energized to inform the central processor that the command has been stored in the command register and the TC identifier can be reset. Bit 15 from the buffer is checked whether it is a read or a write command so that the correct microcode pattern is decoded.

Due to the resetting of the TC indicator, VB is switched off. now becomes data from a memory location specified by instruction decoding read and through the buffer to the high byte of the I / O bus sent out. The TD license plate can be raised after the shutdown from VB to let the adapter know that the data is on the

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high byte of the I / O bus. If the data in the data input register stored by the adapter, VB is shut down to indicate to the central processor that the adapter has the data. as next the I / O identifier and the byte identifier are reset, to indicate that the I / O instruction has been completed and the IRP line is switched off if it was used to indicate that interruption signals are back on the bus.

The TC label is not required for HW units as the unit can read the address and the command at the same time. A timeout can only occur while the central processor is responding to a response from the VB indicator, VH license plate, IRP license plate or EOC license plate is waiting. the Exception line is used to prevent the timeout during the priority-controlled Cycle assignment used.

The only additional ones required for the priority-controlled cycle assignment Cables are CS requirements, CSG marks and EOC marks. The priority-controlled cycle assignment is initiated by the adapter and therefore does not need an address. Instead it is a control word sent from the adapter to the central processor. This control word contains Information that tells the central processor whether it has been read or written

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and a start address for address control and for the direct byte transfer, with which byte the reading or writing should begin. With the priority-controlled cycle allocation, many bytes or data half-words are to be read or written at high speed will. The request line for the priority-controlled Cycle assignment can be activated at any time. However, it is ignored until the instruction currently being processed in the central processor is finished. Then the central processor is ready with the priority-controlled one To begin cycle assignment and the first command word provided for this from the read-only memory activates the I / O flag. Through this the I / O bus is released and an identifier for a valid one Byte or half-word must switch off. To indicate this process. Then the central processor raises the signal for the granting of the priority-controlled Cycle assignment (CSG flag) to indicate that it is ready to receive the control word. The validity indicator (VB or VH) must be returned to indicate that the control word is on the bus.

After the start address has been saved in the address control, the address for byte data transfers by 1 or by 2 for half-word data transfers, brought up to date until the EOC

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Identifier (end of chain) indicates that the adapter has assigned the cycle has finished. Previously, the TD label was used in the same way as with programmed data input / output. The end of the priority-controlled Cycle assignment is similar to the end of programmed input / output. Another priority cycle allocation request can follow this operation or the central processor returns to its next instruction.

With the AC holding circuits for the input tags from the adapter to the central processor the latter is prevented from responding to interference pulses that may appear on these lines.

The individual blocks are shown in context with the aid of FIGS. 2, 2A and 2B with the functions they perform. In the upper part of FIG. 2A, the source and destination buses of the computer system appear. The central memory 10 is the same as that shown in FIG. 1. The address controller 30 takes over the conventional addressing routines and contains the memory address register and also has facilities for performing index operations. The CW buffer 32 is conventional Control word memory into which the control word is transferred from the CW buffer 62 in the adapter and used to control cycle allocation operations.

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The buffer 34 is a conventional memory buffer for receiving data from memory 10 and for storing data in this memory. Interruptor 36 receives and analyzes interrupt requests and contains the necessary logic controls to select the interruption requirements with the highest priority. Of the numerous interruption systems available in the computer field, in the exemplary embodiment a simple pre-wired priority circuit was chosen, in which the raising of a signal on certain data lines during an interrupt call Displays priority assignments of certain external devices connected to the data trunk via their specific adapter.

The gates 38 and 40 are the essential gate circuits for data transmission from the destination manifold to the I / O manifold or from the I / O manifold to the source manifold. The instruction decoder 42 is a device of a conventional type which is connected to the instruction register (not shown). Only those will be here Functions related to the present invention are shown. The one from the instruction sdecoder 42 is line running to ROS address decoder 44 active when a programmed I / O operation is called. This will a certain start address in read-only memory 46 (ROS) is addressed and subsequent commands are read out until the one called

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I / O operation is complete. The ROS address decoder 44 is on similar way activated when a priority controlled. Cycle assignment is requested. The read-only memory 46 is constructed in a conventional manner and reads into the ROS register 48. The output of this register is angry ROS decoder 50, the output lines of which are connected to the holding circuits or latches 52 shown as a block, which hold the signals raise or lower one or more output flag lines from this block. Take over the two output lines drawn from block 5 0 the functions "switch on" and reset "for all holding circuits, whereas the middle lines, represented by dashed lines, switch on selected identifier lines which are used for adapter control 54 to run. The adapter control works in a conventional manner and takes over the usual connection operations between the external units and the Central processor. It also contains the controls for switching on the priority-controlled Cycle allocation operation in the embodiment shown here. In other words, if one of the license plate lines is from the Holding circles of the interlocks 52 carries a high signal, the adapter control signals that a certain operation is being carried out by the external unit is to be carried out. When this operation has been completed, the unit informs the adapter control, the flag VH or VB is raised and this indicates that the operation has been performed. So that will

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the ROS control 56 is notified that the next instruction is needed. The adapter control essentially consists of holding circles or interlocks and from a timing circuit which accepts the various control signals from the control system and the units, forwards, and automatically provides the time needed to complete the called operations. The two blocks 58 and 6 0 below in Fig. 2A serve as AC latches to get their output signals on the to hold the upper value when a certain signal is received on one of the four label lines running into these blocks from the adapter control will. The interlocks are designed so that appearing on these lines arbitrary disturbances cannot trigger an erroneous operation of the ROS controller 56.

The system described here contains a priority-controlled cycle assignment, in which a certain unit requests a fairly long data chain from memory at consecutive address locations not every data word transferred from the memory has to go through a complete access request, but instead the complete Data series are either read into or out of memory until the series is completed. At this point, the priority cycle allocation operation also occurs terminates and the system preferably returns to the programmed standard input / output. The CW buffer 62 includes one

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Part of the priority cycle allocator and is used during the corresponding assignment operation is used,

The address decoder 64 stores an address and decodes it for identification of the unit addressed by the system. An output line goes from the address decoder to each individual unit and indicates that she was elected. The command register 66 is used to store a specific one Commands for the units. The command can be a specific read / write command and goes through the adapter control 54 and on to the data input and data output registers 68 and 70, which can either be in the individual external units or in the adapter can be arranged. However, a pair of such registers could also be used with a corresponding one Circuitry can be used in conjunction with the address decoder so that any given unit can use these data registers and so on a doubling of the switching effort is avoided. The command can also contain a number of other unit-dependent operations, which May or may not include data transfers as such. To explain the overall operation of the I / O port controller is the read / write operation however, the most general form of surgery. The dashed block 72 comprises the interrupt request facility where it is determined that the gates 74 are energized when a certain external unit is a sub-

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requesting break from the system. There are as many gates 74 as there are units. The gates 74 feed the interrupt request locks 76, to keep the signal voltage on the lines high for a specified time. There can be multiple interrupt request locks at the same time be locked and then there will be a particular data line on the I / O bus excited. In this way, the system decides which external units will be served at a certain point in time.

The operating principle of the system and the control line table are then described shows more clearly the interrupt operation and the "priority cycle assignment sequences" contained therein.

The following table shows the functions of each control line, which connects the adapter units directly to the central processor. In the exemplary embodiment shown, these lines are in one direction of transmission assigned, although they have additional corresponding program support and machine controls can also be designed to be bidirectional. The direction of the signal flow on these lines is shown in the table specified.

The adapter controls are designed in a conventional manner so that

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different operations on either the rise or the fall side of the tax code signal can take place. You can achieve that, for example by tapping the control either from the switch-on or from the reset side of a flip-flop.

CONTROL LINE FUNCTIONS TABLEEM

cables

I / O TAG (central processor to adapter)

BYTE TAG (central processor to adapter)

TA TAG (central processor to adapter)

Functions served

Frees the I / O bus from interrupt request interlocks. Opens gate from destination s manifold to I / O manifold for writing. Indicates completed Έ, / h instruction. Indicates the beginning of a CS instruction.

Indicates byte operation

Tells the adapter that the high data byte contains an address and the command for a HW adapter

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(Central processor to adapter)

TD DAY

(Central processor to adapter)

is on the low data byte. Indicates that the command for a byte adapter is moved onto the data lines for the high byte.

Indicates that the command is on derri high byte. Indicates that the command is saved (for HW adapter, the address and command can read on the same line, not required).

Prevents switching from interruption requests to interlocks in the adapter during the interrogation of interrupt lines. Indicates that data is on the high byte, With priority-controlled cycle assignment, display for data on the bus.

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INSPECTtD

STOP DAY

(Central processor to adapter)

IRP TAG

(Adapter to central processor)

VH DAY

(Adapter to central processor)

VB DAY
(Adapter to central processor)

Xl .

Informs the adapter that the count limit has been exceeded for VB or VH or IRP or EOC response from the adapter or internal interlock (a machine test that triggers an interruption level)

Indicates that there are interrupt requests on the bus.

The same as VB for half-word unit,

Indicates that interruption requests are kept free and the unit is a byte unit. Indicates receipt of a valid address. Indicates that the command is in the command register 66 is stored. Indicates that adapter is saving data

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Has. In the case of the priority-controlled cycle assignment, this indicates that the Control word on the I / O bus lies.

CS REQ

(Adapter to central processor) Indicates a request for a priority-controlled Cycle assignment. (Introduced by the adapter - will be ignored until the instruction is in progress is finished).

CSG DAY

(Central processor to adapter) Indicates that the processor is to receive a priority-controlled Cycle assignment s control words s is ready (CSCW).

EOC DAY

(Adapter to central processor) Indicates end of priority-controlled Cycle assignment chain.

EXC

(Adapter to central processor) Prevents timeout during CS.

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TABLE OF DATA LINE FUNCTIONS (I / O collective line)

cables

HIGH 0-7 "data" (central processor to adapter)

HIGH 0-7 "data" (adapter to central processor)

LOW 8-15 "data" (central processor to adapter)

LOW 8-15 "Data" (adapter to the central processor) B edi duck func nen

High byte "write data" for HW adapter. Unit address for byte operation. Byte data to byte adapter.

High byte "read data" from HW adapter. Byte data from byte adapter.

Low byte "write data" to the HW adapter, command for byte operation .

Interrupt requests from the adapter (if not in CS or I / O mode). Low byte "write data" from the HW adapter.

An interruption system for operating the requesting external units and the cycle start operation itself

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ben that reading relatively long series of data into or out of the system System allows without individual transfer operations between the Memory cycles are required.

I / O interrupt

The following description takes a possibly hard-wired interrupt priority scheme where the lifting of a certain data line automatically indicates the interruption level. This I / O interruption scheme works in two steps, assuming that multiple units are at a given interruption level. First is the I / O bus then examines which levels have a high signal. Multiple units can request service at a given level. The highest requesting level is determined in a conventional one Decoding circuit. A program routine is then called to process the the highest level to find out which units want to be served at this level. (If more than one unit is on the same level, these units must work with special adapters that also use the I / O bus Use interva read during a call to indicate that they want to be served). For example, if a 4 is the highest requesting level, then the program is switched to level 4 I / O and an instruction executed on the data lines. One of the adapters can

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to put an adapter identification signal on a single I / O line to indicate that it wants to be served when it is interrupted. The data bus is read out and a further instruction determines which units on level 4 are to be operated. The units will then operate in a predetermined order until all level 4 interrupts have been serviced and then the lower level interrupts are serviced.
Priority cjes controlled cycle allocation (CS)

If an adapter for priority-controlled cycle to order the signal on the If the request line raises, a hold circuit is locked on the output of the instruction currently being processed. This will use the ROS address register the start address of the CS microprogram loaded. The I / O line is raised, indicating to the adapter that the control unit is in a CS routine has arrived. The adapter raises a valid line (VB or VH), which is confirmed by the cycle allocation line (CSG).

The adapter then sets the priority control cycle allocation word (CSCW) on the I / O bus. The CSCW is passed to the CSCW buffer 32 by an appropriate operation.

The CSCW control word indicates whether it is a read or a write

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operation (address bus bit 8) and gives a start address into memory 10. Then read or write cycles are carried out the memory address controller 30 is addressed until the adapter has the desired Number of cycles has finished. At this point he lifts the EOC-Leitunc at. This terminates the microprogram for the priority-controlled cycle assignment. The address of the instruction that was last used before the start of the Cycle allocation operation has ended, is reloaded into the memory address register and a normally programmed input / output can again or another cycle operation can be initiated.

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Claims (4)

.U. PATENT CLAIMS Input / output port controller for optional Connect an internal destination manifold of a central processor to a bidirectional I / O manifold for entering data from one of several external units or for connecting an internal one Source bus with said I / O bus for outputting data to an external unit, thereby characterized in that an I / O boundary point control device (14) is provided within the central processor (12) is, in which a first gate circuit (38) is used for a first data flow direction, the data lines of said destination bus to connect to the I / O bus, and a second gate (40) is used for a second data flow direction, the data lines of said source bus with the To connect I / O bus, and that control circuits (52) for actuating said gate circuits (38, 40) are provided which respond to I / O request signals originating in the central processor or in an external unit (18) connected via an adapter (16). 2. Device according to claim 1, characterized in that in an I / O limit point control device (14) control holding circuits (52) are provided, which are set by received control signals which are determined by decoding of retrieved from a read-only memory (44, 46, 48) - 98 -
YO 973 040 S09833 / O642 Control information is obtained and that the outputs of said control holding circuits (52) via identification lines in a control bus line (22) with a Adapter control (54) in each external unit (18) adapter (16) connected to the I / O bus are connected. 3. Device according to claim 2, characterized in that from each adapter controller (54) token lines to hold circuits (58, 60) in the I / O boundary controller lead, the outputs of which with the control circuit (56) of the read-only memory containing the control information (44, 46, 48) are connected. ι , 4. Device according to claims 1-3, thereby indicates that each adapter (16) has an interrupt request device (72) which contains the associated hold circuits (76), the switching state of which is periodic is scanned by a central interrupt control device (36) in order to control the operation of the connected to control external units (18). YO 973 040 - 29 - 509883/0642 • Sc · Blank page