DE2501714C2 - Digital frequency tracking circuit for continuous measurement of the carrier frequency of pulses - Google Patents

Description

15th

20th

The oscillator (5) is adjustable and its bandwidth is 40 when a new unit pulse is being read in, by means of an up / down counter (19) always a unit pulse at the same bit position can be changed. the

Position of the shift register in which the unit pulse

is, wherein the up / down counter (19), which tv.it is acted upon by the correction pulses, is also connected to the oscillator (5).

3. Digital frequency tracking circuit according to claim 2, characterized in that the bandwidth of the commutative tracking filter (1) by bridging its series resistances with a or several switched field effect transistors can be changed.

is a measure of the ratio of the signal frequency to the shift clock frequency.

There is a correction signal for each direction around the shift clock oscillator constructed as a VCO to adjust to high or low frequencies. This continues until there is a frequency division ratio has regulated, which is determined by the choice of storage locations. The frequency tracking device according to the invention works in a wide frequency range.

In a further expansion of the inventive concept

another disadvantage of previous circuits eliminated, namely that the phase position of the signal voltage in

The invention relates to a digital frequency after switching on in pulse mode to the switching on of the transient process defined in the preamble of claim 1 - · - <- <■ - <- *> ■ - «■■ <><- ^ - ~ ° - ~

named Art.

In Doppler sonars, the carrier frequency must be the pulse trains of echoes can be measured very precisely. This presents difficulties, since the impulses eo are short. During the impulse, it can be interrupted by interference or air bubbles. The frequency is the direct measure of the speed, so that under such circumstances Result in incorrect measurements. 6ί

It is known to measure the frequency of the received signal by using the frequency of a VCO (Voltage Control Oscillator) so that it has a possible influence. This Expansion consists in adding a few flip-flops to the circuit according to the invention. It is achieved that

1. only whole oscillations are analyzed,

2. The beginning and end of each signal oscillation are clocked, that is, with the edge of the shift register to coincide. The shift clock is roughly a multiple of the signal frequency, for example approx. sixteen times,

3. After the end of an impulse train, the "previous history" is "forgotten". At the beginning of a pulse train the edges become unit pulses

25 Ol

read into the shift register. The first correction pulse can be generated after just one oscillation will. The control is therefore "phase-locked" in the steady state.

Since the shift clock is readjusted so that it corresponds to n times the signal frequency, can run in this way with the shift clock or an integer fraction thereof commutative filter can be controlled. This is a simple way of sharply delimiting the band of the Doppler spectrum possible.

The advantages achieved by the invention are in particular that the digitally constructed Frequency tracking circuit according to the invention has a wide capture range, which is increased by increasing the number of digits in the shift register can be expanded as required. The digital sound is still completely drift-free. The circuit according to the invention is phase-locked in the steady state.

Doppler signals fluctuate statistically in their phase position from pulse to pulse. A control process is used to adjust the phase after the start of the pulse. So it is desirable to avoid this control process, since it only contributes to the unrest in the control loop without using the accuracy of the frequency tracking. Are only a few vibrations in pulse mode for frequency analysis before, so Versa μ gen all conventional circuits. Because the phase control process is still in full swing when the signal pulse has already passed.

During the phase control, the frequency must necessarily be adjusted briefly. As a result of the imperfectly completed control process in the relatively long pulse pause, control deviations of the voltage-controlled oscillator then remain, which lead to large statistical errors. w

In the circuit according to the invention, if the number of bits η of the shift register is sufficient, the phase position may vary as desired from pulse to pulse without a correction signal being generated.

The follow-up circuit according to the invention is al- · »> thus adapted to the conditions of the Dopple: Sonar Craters.

Although the transmit pulses are coherent, the receive pulses become essentially incoherent, although coherence drawings are in effect during the pulse. The coherence time is thus in the order of magnitude of the pulse length itself or is significantly less. The follow-up control according to the invention, however, works with the properties of a fast phase discriminator.

Embodiments of the invention are shown in the drawings and are described below described in more detail.

1 block diagram of a frequency tracking circuit, FIG. 2 circuit of a commutative filter,

F i g. 3 Time-pulse plan of the shift register.

1 shows a block diagram of a frequency tracking circuit. The received signal carries the Doppler frequency and is converted to a suitable intermediate frequency. When entering into the circuit's happened .. a commutative filter 1. Then it is amplified in a limiter amplifier. 2 The signal is then brought to a digital standard level in a Schmitt trigger 3. With the help of the | K flip-flop 4, it is synchronized with the shift clock. The shift clock is from the voltage-controlled oscillator 5 with a downstream 2-. 1 divider 6 generated. It is fed from the Q output of the divider 6 to the clock inputs of the flip-flops 4 and 7. The flip-flop 4 is followed by the flip-flop 7. This shifts the signal by one .Schiebetakt. By combining the two signals with an AND, gate 8 generates a negative pulse that coincides with the positive edge of the input signal and is one shift clock wide. This pulse is inverted in gate 9. Another flip-flop 10 suppresses the first pulse generated by the flip-flop 7 and derived from the signal, since this pulse could not be determined in its temporal position by the signal, but by the shift register 12. The time window clock only releases the path f & the received signal for frequency analysis if the signal is disturbing .. -. Side effects is free.

The second pulse generated by the flip-flop 7 can only be generated by the signal itself "Ει-passes through the gate 11 after Q in the mip-flop 10 has opened /.

The second and thus first usable signal pulse at the output of gate 11 is read into shift register 12 as a standard signal. That Shift register is still empty. Therefore, this unit impulse must not yet be used to decide whether a previous pulse is correctly in the register. Rather becomes to For this purpose, the second pulse is again suppressed in the JK flip-flop 13 by the fact that this only occurs at the end of the second pulse The gates 14 and 15 are only activated by the third unit pulse happened. In the meantime, however, the second unit pulse has passed through the shift register 12. Where he The moment the third unit pulse occurs at gate 15, it depends on the sliding cycle. There are three ways of doing this, starting with the letters a). b) and c) are designated ·.

a) the second unit pulse is in one of the last places in the register with the exception of the last,

b) the second unit pulse is in the last place of the register,

c) the second unit pulse is already out of register pushed out.

Kig.3 shows how with each shift clock pulse the stored unit pulse is increased by one Bi; is pushed on. After η- 16 shift clocks, the unit pulse in case b) is in the last memory cell of shift register 12 for Ib. Bit, in case a) in the penultimate saliva cell for the 15th bit and in case c) it is no longer in shift register 12.

As Fig. 1 shows, an OR gate 16 with m = 8 inputs is connected to the outputs of the shift register, which is designed for π = 16 bits, namely with the outputs for the (77 - m) -tc bit to ( n- 1) th bit.

Case a) means, üa -, '3 the sending act in relation for signal frcqucn /. too low isi. At the exit of the OR gate 16 sees a pulse. The AND link in gate 17 makes it a condition that the pulses

of the gate 15 and the OR gate 16 are present at the same time. In this case, a correction pulse is generated, which via a flip-flop 18 an up / down counter 19 adjusted. The counter 19 is followed by a digital-to-analog converter 20. This regulates the voltage-controlled one Oscillator 5 towards higher frequencies.

In case b) the signal frequency and the frequency of the oscillator 5 are in the correct ratio. At the exit of the gate 17 is no correction pulse, since there is no pulse at the output of the OR gate 16 when a Unit pulse passes gate 15.

If cases a) and b) do not exist. so the inverter 22 fulfills the condition that the gate 21 correction pulses to adjust to lower frequencies can deliver. However, there is no correction pulse on in case b) either Output of gate 21 is generated, the inverted output of the shift register for the 16th bit is sent to the third Input of gate 21 connected. In case c), if there is no signal at the output of the OR gate 16 and there is no unit pulse in the memory cell of the shift register for the 16th bit, this gives Gate 21 emits a correction pulse when the next unit pulse appears at the output of gate 15. Via a downstream flip-flop 22 and the counter 19, the voltage-controlled oscillator 5 becomes too low adjusted towards higher frequencies.

If the clock frequency / u is low, then 18 a correction pulse is generated. If the clock frequency is correct, neither in flip-flop 18 nor in flip-flop 22 ;;, which is connected downstream of the gate 21 generates a correction pulse, and if the clock frequency is too high, the Flip-flop 22a generates a correction pulse.

At first glance it appears as if the quantization in, for example, only sixteen shift register locations, the frequency tracking circuit is relatively coarse 3ί and let it work discontinuously. However, it has been shown by practical tests that the cr Not only speed up the device, but also readjust it more precisely without overshooting, until the adjustment is achieved. than you would expect with this number of bits.

The properties of the Doppler leakage control can be significantly improved if the receiving sisinal is filtered. To do this, the center of the filter's transmission curve must follow the center of gravity of the üopplerspek- 4Ί hum. A common filter 1 (Fig. 3) is used for this purpose. The commutative, electrically readjustable filter 1 is followed by a transmitter follower 23. This is followed by a selective bandpass filter 24. which narrows the entire operating frequency band. ₍

The commutative filter 1 is controlled via the input 25 with a reference frequency. This will Derived from the voltage-controlled oscillator 5 or divider 6 via a divider 26. Has the shift register for example Ib Bit. the clock frequency must be 16 times higher than the signal frequency in the adjusted State. The divider 6 must have a division ratio of 1: 4. The commutative filter! then leaves a frequency band which is symmetrical to the signal frequency.

The bandwidth of the Doppler signal increases from physica- t> o Tables reasons mi; higher speed. To this end, it is desirable that the bandwidth be continuous or is continuously switchable. This is achieved according to the invention in that the series resistance is at least two partial resistances 27, 28 is coeviiii. At least> 3 At least one of them, for example 27. is bridged by a field effect transistor 29 by the output voltage of the digital-to-analog converter 20 via the line 30 at a certain level of this output voltage is bridged, which can be adjusted with a potentiometer 31. This will make the OurchlaUbandbrcilc increased.

The commutative filter 1 is partly due to the resistance 32 bridged. This resistance leads the close-up circuit after switching on the device the signal frequency is weakened until the adjustment is completed and the filtered signal via path 27, 28 can happen without being weakened. The output signal is transmitted via a control amplifier in the unbalanced as well as in the balanced state kept constant.

For this purpose 3 sheets of drawings

Claims (2)

25 Ol patent claims: 1.Digital frequency tracking circuit for continuous measurement of the carrier frequency of received pulses, using a shift register for η bits, a linking network generating correction pulses and an oscillator controlled by the latter to generate shift clocks of the shift register, the frequency of which is reduced to n times the carrier frequency by the correction pulses is adjustable, characterized in that the shift register is designed for at least π > 4 bits, that the logic network consists of an OR gate (16) whose inputs with outputs of the shift register (12) for the (n-m> th to (n - l) -th bit are connected, where m> 2, a downstream first gate (17) and a via an inverter gate (22) with the OR gate (16) interconnected second gate (21), which also with the inverted output of the shift register (12) for the n-th bit is interconnected that the shift register (12) and both gates (17.21) with trä gerfrequenten unit pulses obtained from the received signal are applied that at the output of the first gate (17) a correction pulse to increase the frequency of the shift clocks is pending when a signal is pending at the output of the OR gate (16) and the next unit pulse appears, and that at the output of the second gate (21), a correction pulse for decreasing the frequency is present, if the outputs of the shift register of (n-w) -icn until the n th bit at appearance of the avenge unit pulse have no signal. 2. Digital frequency tracking circuit according to claim 1, characterized in that for the received pulses a commutative tracking filter (1) is provided, the center frequency of which by the lent exactly matches the frequency of the received signal From US-PS 33 51 868 a frequency lag circuit is known, with the help of a two-line feedback shift register, an Ex-OR gate and a low-pass filter a frequency correction is obtained. The shift register is at the frequency of the VCO operated. In the Ex-OR gate, standardized input pulses are matched with the first output pulse; Storage cell Checked for coincidence. Pulses are generated with a phase-proportional mean value. With a phase shift of the signals by half a pulse width, the frequency is set correctly, the Ex-OR gate then generates a pulse sequence, the mean value of which at the output of the low-pass filter does not contain any further Correction of the VCO causes brief phase fluctuations to affect the control mechanism not, but the averaging results in a delay in the control process. The invention is based on the object of providing an analog technology that works more precisely than known Circuits to specify working frequency tracking circuit, in contrast to known solutions is drift-free, responds quickly and has a larger capture range than that of the prior art which avoids ambiguity This task is performed with a frequency tracking circuit of the type mentioned in the preamble of claim 1 according to the invention by the features in the characterizing part of claim 1 solved The received signal to be analyzed is first amplified and coupled. The positive rectangular flank is converted into unit pulses by clocked flip-flops. So these unit impulses each have the interval of one period of the signal frequency. They are shifted through the shift register in the shift cycle and the shift register is thereby loaded. Does the signal frequency have a certain value and the Shift clock a certain W-Dt, then stands. 10