DE2437106A1 - CCD ELEMENT WITH ASYMMETRIC POTENTIAL THRESHOLD - Google Patents

Description

CCD element with asymmetrical potential threshold

Priority: August 1, 1973 - V.St.A.

The invention relates to improvements in manufacture of CCD elements (CCD = charge coupled devices), especially improvements that are intended to improve the To reduce the size and complexity of such elements, which consist of two-phase, overlapping gate electrodes are constructed and work with a flow of charge moving in the same direction.

The production of CCD elements is known which have a charge flow moving in one direction work »One such element is in the .Zeitschrift

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Electronics, June 21, 1971, pages 58 and 59. In this element the direction is always the same for charge transport achieved in that each gate electrode has a different capacitance compared to its neighboring gate electrode. These two laterally adjacent Gate electrodes are connected to one another around one phase with an asymmetrical potential threshold to form among themselves. The next two neighboring gate electrodes of different capacities are connected to one another, to form the other phase with an asymmetrical potential threshold among themselves, etc.

In order to create an asymmetrical potential threshold that the Determines the direction of the charge flow, such two-phase CCD elements require a connection between two adjacent ones Gate electrodes. This gives rise to considerable manufacturing problems in the manufacture of a device overlapping gate electrodes, in which two sets of overlapping gate electrodes are at two different heights are arranged on. In order to connect two adjacent gate electrodes, it is necessary to make connections between the to produce electrodes at different heights.

These problems are even greater when memory bits or charge storage elements are arranged in a serpentine manner, since then cross connections between the bit lines are necessary. Because the direction of flow of the charge between the Bits in a given row caused by the interconnection of adjacent gate electrodes, it is to guide the charge along a serpentine path it is necessary to reverse the interconnections in order to thereby a transition from one line to the next

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achieve. As a result, the interconnections cross each other.

According to the invention, a two-phase, overlapping
Gate structure achieved by using a single offset mask to create an asymmetrical potential threshold
under each individual gate electrode. The mask pattern is shifted from each of the overlapping gate electrodes. In addition, at least part of the mask pattern remains as a permanent element on the functional structure. The production stages are set up in such a way. that they cause adverse effects in the adjacent gate regions, so as to ensure the appropriate distribution of the
Potential thresholds, which are necessary to determine the direction of the charge flow, to be achieved.

In one embodiment, the manufacturing steps are as follows
constructed that in each gate region there is a non-uniform capacitance, the non-uniform
Finally, the capacitance is distributed in such a way that the potential thresholds in each gate area all define the same sense of direction for the charges when a voltage is applied to the gate electrodes.

In another embodiment, ion implantations are carried out in order to generate a displacement or opening voltage in
introducing part of the capacitor formed in each gate region. Accordingly, a voltage applied to the gate electrode has a different effect on the surface potential in the region in which the ion implantation has taken place than in the region in which the ion implantation has not taken place.

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The invention will now be explained in more detail with the aid of γόη exemplary embodiments and with the aid of attached, semaphatic representations.

In the figures show:

Figure 1 is a plan view of a CCD element according to the invention;

Figures 2-8

Sectional views successively showing the individual production stages of the element according to FIG illustrate;

Figure 9 is a section along the line 9-9 of the figure 1;

FIG. 9a shows a section through a modification of the element according to Figure 9 »

FIG. 9b shows a diagram which shows the potential threshold distribution in the substrate according to FIG. 9;

Figures 1o and 11 sections through modified, according to the invention Elements.

Referring to Figures 1 and 9, there is a nine-bit CCD in accordance with the present invention shown in which the bits are arranged in a serpentine manner. To simplify the description, are only nine bits shown. It goes without saying that a particular device can have far more bits than is shown here exhibit.

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FIGS. 2 ″ to 9 illustrate the process stages one after the other for the production of the device according to the Pig. 1 and 9- In the following description it is advantageous to to the extent to refer to the finished devices according to FIGS. 1 and 9, in which they are from the process steps illustrated in FIGS. 2-9 are developing.

Reference is now made generally to FIGS. 1 and 9, and more particularly to FIGS. 2-9. Accordingly, there is a substrate 1o made of a suitable semiconductor, e.g. P-type silicon. The first stage of the process is, to grow a thick layer 12 of silicon dioxide on the silicon substrate 1o. The thick silicon dioxide layer 12 can have a thickness of 10000 Å and can be manufactured in accordance with conventional technology by the substrate 1o at a suitable temperature in the WHhe heated from 1ooo ° C until the desired thickness is reached.

In the next stage of the process, the thick silicon dioxide layer is made 12 a channel 14 'is etched out. The channel 14 sets the boundaries of the CCD element, the packing density of the arrangement and, in general, the lines which the electrical charge must flow in the arrangement, fixed. De.r channel 14 can be made by conventional photolithographic masking and etching techniques derived from the technology of microelectronic Schaltkreise'her are known to be produced. In the particular embodiment shown in Fig.1 As illustrated, the channel 14 follows a sinusoidal or serpentine path. 3 and 4 represent the same perpendicular section transversely to the width of the channel 14 ″. The width ¥ of the channel 14 is equal to the distance S between its adjacent parallel guides. The channel 14 has a rectangular cross-section and is so deep that

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it extends to the silicon dioxide layer 12. As will be explained later, there is one for the width W of the channel 14 minimum dimensions I ^ jyp which are up to a few microns allowed.

After the channel 14 has been formed, a thin layer of silicon dioxide 16 of approximately 1,000 Å is left on it Grow up silicon substrate 1o. The thin layer of silicon dioxide 16 serves to define the minimum distance between the electrodes and the surface of the substrate 1o. Thereafter it is possible to carry out a number of process stages with which a large number of memory bits or charge storage elements, in this exemplary embodiment 9 bits are applied in channel 14.

It is now referring to the Pig. 5-9 showing the same horizontal section taken along the length of channel 14, for example along line 9-9 in Pig. 1, represent. Accordingly, a silicon nitride layer 18 is deposited on the thin silicon dioxide layer 16, and with the aid of a mask 20, which is used in connection with photolithographic techniques, the silicon nitride layer 18 is designed so that it forms many separate, checkered or staggered rectangular areas. The rectangular areas of the silicon nitride layer 18 are more clearly shown in Pig. 1 shown. Each rectangular area comprises one half 18A, which is later removed and delimited by the dashed lines, and another half 18B, which remains as a permanent part on the substrate or the thin dioxide layer 16 and is delimited by the more narrowly dashed lines. The pattern of the silicon nitride layer 18 is used to introduce the asymmetry into the arrangement. For the thickness of the silicon nitride layer 18, a value of ' 2ooo A is typical.

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Next, one after the other, a layer 22 of polycrystalline silicon, hereinafter referred to as polysilicon . ■, and a silicon dioxide layer 24 is applied, being with the help of a mask 26 and photolithographic Techniques the two layers 22 and 24 so arranged are that they form several strips which cross the channel 14 at right angles. The strips also have one Width V / and a distance S which are equal to the respective sizes of the channel 14, each dimension being equal to that Minimum dimension Iw-m- is. One half of the polysilicon layer 22 rests on the thin silicon dioxide layer 16 and the other half on the silicon nitride layer. 18 like this is shown in Fig. 6 11t. On the other hand, it covers the polysilicon layer 22 only half of the silicon nitride layer 18, so that the other half silicon nitride layer 18 remains free. The silicon dioxide layer 24 is arranged directly on the polysilicon layer 22. The polysilicon layer 22 can be 500 Å and the silicon dioxide layer 24 can be 30,000 Å be fat. The polysilicon layer 22 is electrically conductive, while the silicon dioxide layer 16 and the silicon nitride layer 18 have an insulating effect.

At this stage of the procedure it is evident that the Part of the polysilicon layer 22, which rests on the thin silicon dioxide layer 16, a smaller distance of silicon substrate 1o as the part of the polysilicon layer 22, which rests on the silicon nitride layer. Accordingly, the capacitance of the polysilicon layer is 22 asymmetrical with respect to the substrate 1o. As the polysilicon layer 22 represents one of the gate electrodes, the asymmetrical capacitance creates an asymmetrical one Potential threshold distribution directly below them in the surface of the silicon substrate 1o. This potential threshold distribution defines, as explained later, the direction of the

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Charge flow fixed.

At this point it should also be pointed out that a second gate electrode must be produced in order to to overlap the areas between the strips or first gate electrodes consisting of the polysilicon layer 22. It is also necessary to carry out certain procedural steps necessary for the formation of a structure under the lead second gate electrode, which generates an asymmetrical potential threshold distribution, the same Has sense of direction for the charges, such as that generated under the polysilicon layer 22 or first electrode Potential threshold distribution. The desired asymmetry can be achieved in two ways, or a combination thereof will. First of all, it can be seen that between the area 27 in which the thin silicon dioxide layer 16 is exposed and the silicon substrate 1o only the thin silicon dioxide layer 16 is located, while all other areas of the silicon substrate 1o are separated by far thicker layers are. Accordingly, ion implantation can be performed in the case 27 undertake to adjust a potential threshold there-in such a way, that 'the desired potential threshold asymmetry is created. In addition, area 27 is also the only one Area in which it is possible to grow a silicon dioxide layer of considerable thickness. That's why she can Silicon dioxide layer can be thickened far more in area 27 than in the other areas. Which achieved in this way Asymmetry in capacitance produces the desired asymmetrical potential threshold. This latter approach will now be described first.

According to FIG. 7, an oxide is left on top of the thin one Silicon dioxide layer 16 and on the vertical planks of the polysilicon layer 22 or the thick silicon dioxide layer 24 growing thermally. This growing up leads

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a thickness is reached that

you go through until / greater than or equal to the thickness of the Silicon nitride layer 18 is. At this point it should be noted that all areas, except for parts of the silicon nitride layer 18, are covered by silicon dioxide. Therefore it is now possible the exposed part of the silicon nitride layer 18, according to Pig. 8, etching away the under the polysilicon Layer 22 located parts of the silicon nitride layer 18 to leave intact.

Finally, put a metal layer 28 over the entire

Arrangement applied. The metal layer 28 according to Pig. 9 ν '" Qnthmlfow ." TU-

can stripes ei »g3? <H £ & eii, the finger-like 'between the Polysilicon layer 22 are arranged. A sufficiently large overlap is provided on the part of the metal, to allow Pehler to align the mask. It It is necessary that the metal layer 28 cover at least all of the space between the strips that are covered by the polysilicon layer 22 are formed, covered. However, the metal layer 28 can also cover the entire area including the Polysilicon layer 22 cover itself, since the polysilicon layer 22 has the effect of the metal gate on areas of the Substrate 1o, which are below the polysilicon layer 22, shields. The arrangement now named is in Pig. . 9a, the metal layer being the reference number 28a is assigned. If the metal is allowed to covers the entire area including the polysilicon layer 22 ', the work performance suffers the disadvantage that the additional capacity between metal and polysilicon gates makes additional control power necessary. the Metal layer 28 can consist of 14 οοό Α thick aluminum and forms the second gate electrode. Apparently is in the area between the polysilicon gate electrodes 22 of left side of the gate electrode 28 From the silicon

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The substrate 10 is separated by the thin silicon layer 16, while the area on the right is additionally separated by the thick silicon dioxide layer 24 is separated from the substrate 10. Similarly, the left part is the polysilicon layer closer to the silicon substrate 10 than its right area.

Accordingly, the capacitances of both electrodes formed from layers 22 and 28 are obviously asymmetrical in the same direction, and the resulting potential threshold distribution accordingly has the correct asymmetry, which allows or causes a charge flow in only one direction.

9b shows a typical potential threshold distribution 30, which is fabricated in silicon substrate 10 below gate electrodes or layers 22 and 28. A potential threshold can be thought of simply as a spatial distribution, an impoverishment layer imagine that formed by applying a suitable voltage to one of the gate electrodes 22 and 28 of the CCD element will. In the case of a P-type substrate, for example, one is applied to the polysilicon layer 22 or first gate electrode positive voltage of about 5 volts an inversion in the surface of the semiconducting silicon substrate 10 below of the excited electrode. In the areas where the polysilicon gate electrode layer is closer to the substrate, i.e. in the areas that are only covered by the thin silicon dioxide layer 16 of the polysilicon layer 22 is separated, is the surface potential and thus the depth of the potential threshold or the degree of Inversion is greater than that in the adjacent area in which the polysilicon layer 22 is additionally covered by the silicon nitride layer 18 is removed from the substrate 10, is the case. A similar potential threshold distribution occurs upon application of a positive potential to the second gate electrode or metal layer 28. The resulting asymmetric Potential threshold distribution is in Fig. 9b under the

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BeKugsziffer 3o shown »

Once the potential threshold distribution in the
Surface of the silicon substrate 1o is made, the CCD element can store charge carriers. The appropriate ones
Charge carriers can be input via a pn junction at the point shown in FIG. 1 with the reference numeral 32 and the
Expression "input interface" is marked. Instead, however, the load carriers can also be used
by irradiating the CCD element toi / t; Light are fed in, with parts of the metal layer 28 being removed
can in order to expose the surface of the semiconductor substrate 1o through the poly-silicon layer 22.

As soon as the load carriers are fed in,
they are stored at the point of a certain potential threshold and remain there until they are made to move to the neighboring potential threshold
or to move. The stored charge carriers can only move from the shallower to the lower potential threshold, ie in the direction of Pig. 9b shown arrows. In order to shift the charge from one place to the other, a larger positive voltage of 10 volts is applied to one of the gate electrodes, for example the polysilicon layer 22, for a period of time, in order to form lower potential thresholds underneath, as described in Pig. 9ΐ> shown with dashed lines under the reference number 31
is. Stored charges that are in any
Potential thresholds located under the second gate electrode are "sucked out" and flow in the direction of the in Pig. 3 ¹ O represented ^; arrows to a lower potential threshold located below the first gate electrode. The polysilicon layer 22 or first gate electrode is then again applied to a positive voltage of 5 volts.

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2A37106

In order to move the charge carriers one more time, the other gate electrode is connected to the corresponding one for a while Voltage applied. That is, a positive voltage of 10 volts is applied to the second gate electrode for a while is applied in order to generate lower potential thresholds at the locations under the metal layer 28 and thereby the stored charge carriers from the locations under the first gate electrode or polysilicon layer 22 to the "adjacent locations under the second gate electrode. The voltage at the second gate electrode then receives its previous positive voltage value of 5 volts again. The procedure for moving cargo can then be repeated continuously by first touching the first gate electrode and then the second gate electrode issued the corresponding voltage pulses in the manner described above.

The charge can also be shifted by alternating the potential thresholds initially established Makes episode flatter. That is, by temporarily reducing the positive voltage of 5 volts to 0 volts on one electrode and then on the other the potential thresholds under the gate electrode with the makes the reduced potential flatter than the neighboring potential thresholds, and that thereby the charge of the shallower potential thresholds flow to the neighboring lower ones.

In the case of an N-type semiconductor, one uses instead positive negative potentials, since in this case the minority carriers are holes instead of electrons.

As mentioned above, it is also possible to change the potential threshold by placing ions in selected areas of the

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Semiconductor substrate 1o implanted. Ghent, for example from the one in Pig. 6 illustrated procedural stage one sees that in the area 27 only the thin silicon dioxide layer 16 covers the substrate To, while it is still covered by additional layers in all other covers will. Accordingly, the region 27 is subject to ion implantation to create an ion implanted region 34. Pur the P-type substrate Io P-type ions are used for implantation and N-ions are used for an N-type substrate. In each pail there is a doping the threshold voltage, or the voltage that is required to cause an inversion in the surface of the substrate 1 o bev / irken and to create the impoverishment layer. For example, in a P-type substrate, the majority carriers are holes. Additional P-doping increases the concentration of holes. Because of this, the threshold voltage used for inversion on the surface of the substrate increases to cause electrons, for example, from a positive voltage of 2 to 4 volts to a positive voltage of for example 5 to 8 volts. An increase in the threshold voltage is equivalent to a decrease the depth of the depletion layer and the potential threshold.

With a P-type ion implantation, boron ions can be accelerated with an implantation energy of 5o to 2oo KV, around the thin silicon dioxide layer 16 but not other areas penetrate and in this way into the distribution to localize the doping near the surface of the silicon substrate 1o. The CCD element can then in a diffusion furnace at a temperature of about 9oo to 1ooo ° C for 10 to 20 minutes, heated for a long time, to facilitate the desired threshold shift.

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After the ion implantation has been carried out, the method can be continued as described above in connection with 7 to 9. In such a method, the limited ion-implanted region 34 and the graded silicon dioxide layer 24 together serve to establish the desired asymmetry of the potential thresholds On the other hand, the region 34 implanted with ions can also be produced under the metal layer 28 on its own can be used to produce the desired asymmetry under the metal layer 28, proceeding as will be described below.

According to FIGS. 1o and 11, the one shown in FIG. 6 is exposed Part of the silicon nitride layer 18 is etched away. The device is then heated - to thermally create an extension of the thick silicon dioxide layer 24 to grow on the vertical edges of the polysilicon layer 22. As soon the polysilicon layer 22 is sufficiently covered by the silicon dioxide for the purpose of electrical insulation, the metal layer 28 can be applied. In the final structure of FIG. 11, the asymmetry arises from the Potential threshold below the polysilicon layer 22 from the asymmetrical or graded insulation of the polysilicon layer 22 with respect to the substrate 1o, which with the help of the thin silicon dioxide layer 16 and the silicon nitride layer 18 is effected. The asymmetry of the potential threshold under the metal layer 28, on the other hand, is due to that the metal layer 28 extends both the implanted area 34 and the non-implanted area overlaps, each area due to the thin silicon dioxide layer 16 being the same distance from the metal layer 28 has.

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The one in Pig. 5 shown, first mask 2ο-, the production the silicon nitride layer 18 is used as an offset mask and the silicon nitride layer 18. can be viewed as the pattern of the offset mask. the first mask 2o and silicon nitride layer 18 are three-dimensional opposite the mask 26, which is the location for the polysilicon layer 24 and the metal layer 28 defines, shifted. The silicon nitride layer 18 itself has a spatially defined one Pattern that serves as a processing mask to establish the appropriate asymmetry in both gate electrodes 22 and 28 bring about. First, it specifies the location of the Step ir. Of the polysilicon layer 22 and causes the step in this layer as well as the one resulting therefrom Second, it lays down the asymmetry depicted in Mg. 6 Area 27, which is the area for the ion implantation and which defines the limited growth of additional silicon dioxide on silicon dioxide layer 24, both of which serve to create the asymmetry for the metal layer 28. After the second mask 26 is used to determine the location of the polysilicon layer 22, the silicon nitride layer 18 itself is used to production as a stationary mask in connection with the superimposed layers and further process stages of the CCD element with the help of the self-regulating property of the stationary mask to complete. Third are the chessboard-like arrangement of the pattern of the offaet mask, which is made of the silicon nitride layer 18, and the rectilinear arrangement of the clock lines consisting of the polysilicon layer 22 and the metal layer 28, from the construction of the serpentine * Resulting arrangement, responsible for the high -bit density in the arrangement.

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Almost all of the critical alignment operations are in the manufacturing process this CCD element because of the self-alignment caused by the overlapping of the gate electrodes Silicon is inherent, has been removed. The alignment line of the displacement of the consisting of the silicon nitride layer 18 However, the pattern versus the pattern composed of the polysilicon layer 22 deteriorates the work efficiency. If the shift is not exactly symmetrical to the Polysilicon roughened runs, then have to have adjacent ones Pairs of storage and transport potential thresholds of different sizes. The charge capacity of the arrangement is then limited by the smallest storage potential threshold. In the worst case, this is the length of the storage potential threshold equal to the target value minus the tolerance for alignment errors the mask. This fact finally determines that the value of the minimum dimension, T-y-τ-χρ, must be greater than the alignment error of the offset mask 2o with respect to the mask 26 for the polysilicon layer 22. What is here has to be understood by larger, depends on the desired noise threshold of the system. The minimum value is to be understood as the smallest line width that can currently be technically produced is. This measure is currently in the range between 1 and 1o yes, the special value being the special Set of the processing stages used and the desired one Production target depends.

The following table summarizes the work performance or the quality of a two-phase high density CCD element with a conventional two-phase CCD element compared with overlapping gates for both serpentine and parallel signal flow, where it is assumed that the amplitudes of the clock • voltages are the same. The table shows:

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the bit area A; the storage area length L; the effective Channel width Vi; the storage area area A ^; the I.oisturigs loss per chip P- .; the signal-to-noise ratio SNR; the relative values for the highest clock frequencies on acceptable quality,? "; and the relative values of the signal reduction with! incomplete charge transport due to charge trappinga in intermediate range states at 'lower: and average clock frequencies E-r »

BATH ORIGINAL

- Bit- 8th 2 Storage TABEL Storage Lei Signal- highest Signal ver— Area A ^L MIN area- Effective area- sturdy Intoxication Cycle rate reduction 16 2 length L Sewer pulp Area A _Q loss Verh.S, NO quence F " at low ^L MIN te W ^P D long cycle U frequency E _L usual two-phased siges CCD element k overlap with T ² donate gate elec to trot 6th Parallel sig ^L MIN ^L MIN ^L MIN ^P D 1 F. ^E L nal river ^L MIN Serpentine ^L MIK ^L MIN ^P D 1 ^F H ^E L low signal flow ^L MIN Two-phase CCD Element higher density V / effective channel ^L MIN
ρ ^{1/2 L} MIN 1/2 P _D 1 > ^{k P} H ^E L width W = L _MIN ^L MIN Effective channel ^L MIN
2 _L 2
MIN ^P D 1 N Il P
'H 1/2 E ₁ ^ J width W = 2 L _MIN ^{2 L} MIN

2 A 3 710 6

.dojr .; Comparing the signal to noise ratio is reasonable r: ou * i:. Ev that the SnII.. is proportional to the square root of the storage area area. Almost all of the noise is d. at tr. input and during the charge storage and charge transport in the CCD element and is proportional to the square root of the area of the gate electrode. !! as entrance noise (thermal or shot noise) and the background s-out (whether thermally, optically or electrically distorted); the noise generated by the circuit tones and thermally generated currents during the storage process; that comes in during transport due to the fluctuation of the charge carriers trapped in intermediate range states and a suppressed transfer loss fluctuation are proportional to the square root of the area of the gate electrodes. Me maximum signal charge TT: ο ng e is directly proportional to Gate electrode area. Because of this, the SNR and the dynamic values are proportional to the square root of the area of the gate electrode.

Γ-ie the highest clock frequency is due to the incomplete Transport of free load carriers determined. See e.g. CJ. Berglund and R.J. Strain, "Fabrication and Performance Considerations of Charge Transfer Dynamic Shift Registers, "Bell System Technical Journal 51, 1972, pp. 655-703. At low and intermediate clock frequencies, the capture in intermediate range states under the edges of the gates limits parallel the work performance or quality of the CCD element for the active channel and the signal reduction E ^ is reversed proportional to the width of the active channel. When CCD elements operated with overlapping gate electrodes with a circulating underground charge is the Trapping in intermediate range states under the carpets of the gate electrodes parallel to the active channel at middle and low clock frequencies predominantly. The parallel edges

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- 2ο -

are the areas parallel to the channel in the boundary layer under the gate electrodes, which are affected by the signal charge not, but covered by the underground charge. Therefore are the parallel edges remaining areas of the duct, which does not reach the underground charge. The resulting signal reduction is inversely proportional to the channel width and depends on the information content of the signal. See for example: A.M. Mohsen, T.C. McGiIl and Y. Darman, "The Influence of Interface States on Incomplete Charge Transfer in Overlapping Gates Charge Coupled Devices", IEEE Journal of Solid State Circuits, No. April 2, 1973.

Because of the reduction in the lengths of the storage and transport areas and because of the resulting increase in the fringing fields, the highest clock frequency for a high-density CCD element is more than four times that of a conventional two-phase CCD element. Because of the smaller storage capacity, the performance loss is reduced. The reduction in the SNR in the case of the high-density CCD element due to the smaller storage areas can be compensated for by increasing the active channel width ¥. In addition, this reduces the signal reduction at low clock frequencies E _x . In this package, the bit area of a high-density CCD element is still smaller than the bit area of a conventional two-phase CCD element.

Means for achieving a very high density and excellent performance characteristics have been described in the foregoing. The advantages of the disclosed CCD element can with a standardized manufacturing process of an overlapping gate electrode made of polysilicon using standard mask tolerances. Furthermore, they are used to manufacture of the CCD element used process steps compatible

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with those that are used in the 'MOS technology, so that CCD and MOS elements simultaneously in the same substrate

can be produced. With the help of the invention is

a bit area of ^ (k _MIN ) has been reached, namely

for both parallel and serpentine two-phase CCD elements. By way of contrast, it should be pointed out that the previous objectives were to

2 ·

areas of 8 ( ^L _MIN ) ^for parallel signal flow and 16

(L) for serpentine signal flow.

In the case of gate electrodes with a minimum width L _MIN of approximately 7.78 μ (ο, 3 mil), the CCD according to the invention leads

' H

Element with a packing density of more than 4.7 X io ³ bits / cm (3 X Io bits / in). The determination of the direction of the charge flow is better achieved in a single gate of minimum width than in a pair of adjacent gate electrodes or within a single gate electrode, the width of which is twice the minimum width.

Patent claims:

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Claims (1)

Claims: J CCD element constructed on a conductive substrate, characterized in that it consists of at least one pair of adjacent, self-aligned and overlapping gate electrodes of minimal size, spaced from one another and from the surface of the substrate (io) are arranged insulated, and layers or regions (18, 22, 24, 34) which are assigned to each of the gate electrodes and are arranged in corresponding regions of the gate electrodes in order to provide an asymmetry in the potential threshold distribution in the corresponding regions of the gate electrodes, the asymmetry defining the direction of the charge flow in the substrate (lo) after two predetermined clock voltages have been applied to adjacent gate electrodes. 2. CCD element according to claim 1, characterized in that the layers and regions (18, - 22; 24, 34) which are used to build up the asymmetry, an insulating layer (18; 24) comprise at least one of the gate Keeps electrodes at a distance from the substrate (lo) that a part of the gate electrodes has a greater distance from the substrate (1o) than their other part. 3r CCD element according to claim 1, characterized in that the layers and regions (i8, 22, 24, 34) for producing the asymmetry comprise an ion-implanted region (34) which is arranged in the substrate (lo) and has the threshold potential therein Area changed. 5ϋ9θ30 / 0823 4. CCD element according to claim 1, characterized in that at least one of the gate electrodes consists of an arrangement of parallel strips of minimum width (! "-"), the strips being at a distance from one another which is equal to the minimum width · Iw-nt is, have and are electrically connected to one another. 5. CCD-Eleraent according to claim 4, characterized in that the other electrode has sections which overlap at least the space between the strips. 6. CCD element according to claim 5, characterized in that the other electrode consists of an arrangement of parallel strips which are arranged like fingers between the strips of one electrode. 7. CCD element according to one of claims 1 to 6, characterized in that it has a relatively thick, on the substrate (1o) resting insulating layer (12) "'and a serpentine channel (14) formed therein, which is substantially rectangular to the strips of one electrode, a width which is equal to the minimum dimension (L -, - ^), and a depth which is more than half but less than the total thickness of the insulating layer (.12), so that a thin insulating layer (16) remains in the bottom of the channel (14) 8. CCD element according to one of claims 1 to 7, characterized in that it has several additional rectangular insulating areas in the channel (14) which are on the thin insulating layer (16) are arranged along the channel (14) and thereby form rows, the additional rectangular insulating areas arranged in one of the rows being offset from those arranged in the adjacent row 509830 / 082.3 and at least one n form part of the layers and regions (18, 22, 24, 34) for producing the asymmetrical potential thresholds. 9. CCD element according to claim 8, characterized in that the additional insulation area is approximately half as wide as the strips of a gate electrode, and the strips of the gate electrode are arranged in relation to the insulation areas that each strip is in each row covers only one insulation area (18B). · 1o. CCD element according to Claim 9, characterized in that the edges of the strips of the gate electrode are essentially aligned with the edges of the insulation regions (18B). 1.1. CCD element according to one of Claims 1 to 1o, characterized in that it essentially has the following: a) with a first number of electrode elements the minimum dimension L ·, ^, which are common along of the channel (H) arranged at a mutual distance equal to the minimum dimension Ivrjw are, each of the electrode elements substantially with a first half on the thin insulating layer (16) lies; b) a first group of additional isolation areas (18B) in the channel (14) and between the thin insulation layer (16) · and the remaining 509830/0823 second half of each of the electrode elements arranged are, the second half of the electrode elements has a greater distance from the substrate (To) than its first half; c) electrical connections between the first electrode elements; d) a second number of electrode elements which are electrically connected to one another and which Bridge gaps (27) between the first electrode elements; e) a wide group of additional isolation areas (24), which are arranged between the first and second electrode elements and these against each other isolate, each isolation area (24) of the second group including a portion, on the thin insulation layer (16) directly on the corresponding first half of the first electrode element and a distance opposite the corresponding isolation region (18B ') of the first group; and f) a first section in each of the second number of electrode elements which rests on the thin insulation layer (16) and a second section which second number of electrode elements., on the insulation area (24) of the second group rests, said second section being at a greater distance from the substrate (io), than the said first section. 50 98 307 08 2 3 12. CCD element according to one of claims 7, 8 and 11, characterized in that the channel (14) has a plurality of parallel channel sections. 13. CCD element according to claim 12, characterized in that that the first and second numbers of electrode elements consist of two sets of strips which are at right angles run along the canal and arranged like fingers inside one another are. 14. CCD element "according to claim 12, characterized in that that the first group of insulation areas (18B) in the channel (14) are arranged offset from one another in a checkerboard manner are. 15. CCD element according to one of claims 3 or ff., Characterized characterized in that it is in a region of the substrate (io) which is below each of the to the second. group belonging insulation areas (24) in the thin insulation layer (16) is arranged, - has a region (34) implanted with ions. 16. CCD element according to one of the preceding claims, characterized in that the second number of electrically interconnected electrode elements is arranged on the thin insulation layer (16) in the spaces (27) between the first number of electrode elements and insulated therefrom , the ion-implanted B _P - vei ch (34) is adjacent to the area of the substrate (io) which is below the first half of each electrode element belonging to the first number of electrode elements and approximately midway between adjacent electrode elements of the first number 509830/0823 Electrode elements ends with the implanted with ions Area (34) is used to increase the threshold voltage in the area of the surface of the substrate (io) raise. MTBtANWALTE 011.-INO-KHMCKE ₁ DIPL-INo-KBOHR WPLMNe. LSTABOER 5 0 9 8 30/0823