DE2358253C2 - Method for operating a data memory containing an insulator layer with a semiconductor layer arranged thereon, and a data memory of this type - Google Patents

Description

Irradiation of the data location over its area of diameter D is achieved by moving the electron beam by focusing, or by moving it in a circle around the area of the data location by placing the data location at a distance L of about 20 microns where L is greater than D, which is about 10 microns, and when the diameter d of the electron beam is about 5 microns, a network of positive electrical charges is obtained in the insulator which surrounds all data locations at the insulator-semiconductor interface Reticulated pattern of positive charges creates a correspondingly connected reticulated layer of strong inversion and good conductivity in the semiconductor zone next to the insulator-semiconductor interface. This net-like layer surrounds all data points, with positively charged points, i.e. points representing a one, being charged in the same way as the network-like layer, and the uncharged points, i.e. points representing a binary zero, thus being the only uncharged points in an otherwise uniformly positively charged insulator layer prove.

When reading out, an electron beam of such energy scans the points to be read that it can penetrate into the area of the semiconductor layer. The electron beam has a diameter d which is smaller than D, which in turn is smaller than L At the same time, the potential over the entire layer package is kept essentially at zero or made slightly negative

When scanning a charged digit, i.e. a digit representing a binary one, an electron is formed from each and a defect electron existing carrier pairs and the two parts of the pair are in the electrical The space charge separates those due to the positive charges present in the insulator in the field Semiconductor layer is induced. The electrons of this electron / hole stream are reticulated by the Layer in the semiconductor, which surrounds all data points, conducted; this causes the emergence of a relatively large one Charge current for the capacitor itself, which in turn supplies a large output signal for the charged state, that is, the binary one of the scanned position is characteristic

When the reading beam! The electron-defect electron pairs, which were generated by the electron beam in the semiconductor, recombine in the uncharged area of diameter D before these charge carriers reach the highly inversed and highly conductive reticulated network Reaching the layer in the semiconductor: This results in an extremely small charging current for the capacitor, which can be distinguished without any difficulty from the output current that arises when a charged point is scanned, i.e. a binary one

The invention is explained in more detail below with reference to the drawing

F i g. I highly schematically shows a functional diagram for a known data memory with a representation of the Writing and reading system;

2 is a greatly enlarged plan view of the Surface of a data storage element to explain some critical dimensions;

F i g. 3 is a model-type circuit diagram illustrating the physical phenomena used by the invention;
F i g. 4 shows a memory system for a computer in which the invention is used;

F i g. 5 some in the appendix according to FIG. 4 occurring electrical quantities in their time course; and

F i g. 6 is a highly schematic representation of the arrangement of many storage elements according to FIG. 1 or 4.

F i g. 1 shows a partial section through a sandwich-like “capacitor” 10 which is used here will. It should be noted that the sectioned part of FIG. 1 is only part of a whole represents such a capacitor. For example, a complete capacitor could be a flat package of about 0.25 mm thick and 0.5 χ 0.5 cm base. The component has four layers, namely a metal layer, this is followed by an insulating layer, then a semiconductor layer and then another metal layer The in F i g. The section of the section through such a “capacitor” 10 shown in FIG. 1 corresponds to FIG of reality only a part with an extension of a few microns corresponding to the order of magnitude some diameter of a finely focused electron beam.

The component 10 according to FIG. 1 consists first of a conductive back layer 11, a semiconductor layer 12, an insulator layer 13 and a front conductive layer 15 in this order; the semiconductor layer 12 and the insulator layer 13 form an interface 16 between them, to which we shall come back several times. Different materials can be used for the individual layers: For example, the semiconductor layer can consist of Si, Ge, InSb, InAs, GaAs, the insulator 13 can consist of SiO ₂ or SiO, a ferroelectric material such as e.g. B. BaTiO3 or another material with comparable properties. In the present case, the semiconductor layer consists of a p-type silicon and the insulator layer consists of SiO ₂ , ie silicon dioxide. The metal layers 11 and 15 can for example consist of aluminum or silver or nickel or gold or another conductive material.

The component 10 is switched into a polarization circuit 21 around a positive or negative potential to be placed on the component while it is being stored or read, which will be discussed in detail below. the Energy bands of the semiconductor layer 12 are indicated by the lines 32 and 33, the line 32 being the Represents the lower edge of the conductivity band, and line 33 represents the upper edge of the valence band. Further provides line 34 is the lower edge of the conductivity band and line 35 is the upper edge of the valence band in the insulator 13. Assuming that the semiconductor material 12 is p-type, the Fermi edge becomes of the isolator cooperating with the semiconductor represented by the dashed line 36 Where in the Insulator layer no charges are present, which is indicated by the plus sign 55 are the energy and ligament boundaries 32-35 formed substantially horizontally similar to Fermi level 36 but if so Charges are present at a storage location, for example due to an impinging electron beam 51 from a corresponding source 52 and at the same time a positive polarization potential with the switch closed 23 is applied from point 24, the component is acted upon positively and the edges of the conductivity and the valence band (lines 32-35) are shown in FIG. 1 noticeably bent downwards.

If the storage capacitor is in the manner just described at a certain point for a

Bit is applied, an electron beam 51 is directed onto the insulator layer 13. For more details concerning the different charge states and the mechanisms by which positive charges arise at the memory locations, reference is made to the literature mentioned above, which this in Describes all the details.

In order to read out the data stored in the "capacitor", an electron beam 51 is used, the has such a strong penetrating force that it reaches the space charge region 17 in the semiconductor layer 12, or hits him. Assuming that the semiconductor 12 is a p-type semiconductor, the in the depletion region under the charged data locations generated by the read beam separated and the holes are moved into the depletion region by the prevailing electric field 17 driven. This creates a stream of holes of considerable size, which covers the area of the "capacitor" charges under the memory location and a signal output voltage is generated across a load resistor 56 leaves, which is connected in parallel with the memory element. This output voltage can then be sent to a Amplifier 57 or the like, in particular a computer, are placed. As will be explained below, becomes that hole current that is created by the impact of the reading beam within the depletion region 17, several orders of magnitude larger than the current that arises when there is no space charge region in the area of the interface 16 in the insulator layer 13 is present. The reading can be done with little or no bias on the memory element can be carried out: Preferably, a small negative bias is applied by that the movable switch part 23 is placed at the contact point 25 or the central contact point 27.

If, however, there are no positive charges 55 in the isolator 13 at a specific storage location, then the energy bands within the component 10 are essentially straight and there is no significant depletion zone 17 in the semiconductor layer next to the interface between the semiconductor and the insulator before. Since there is also no electric field that would otherwise prevail in the depletion zone, this is Efficiency of separating electrons and holes and collecting charge carriers among the non charged storage locations are considerably reduced Current in this case is considerably smaller than when the load current is from a charged storage location would go out.

The above with reference to F i g. 1 explained storage device in the form of a "capacitor" of multilayer design works satisfactorily when the Have a distance of at least 200 μΐη in the middle of two adjacent storage locations. if but on the other hand, the center-to-center distance between two storage locations lying next to one another, this physically required Has value, the storage element as such is economically uninteresting because it is used for storage one bit required space is relatively large and incidentally considerable for reasons not of interest here Circuit effort required

The phenomenon known per se and described in detail above, also from an economic point of view To be able to use it sensibly, the invention proposes a novel method of storing and novel Circuit means before, with the help of which this center distance between two adjacent Reduce memory locations to 20 or even less μπι can. To better understand the detailed discussion below, let us begin with another Analysis of the movement of those charge carriers carried out by the reading beam when reading out are generated in the semiconductor layer.

The invention is based on the knowledge that the theory explained in detail above regarding the The emergence of the various output pulses requires modification. To explain this, the Quiescent state properties of a capacitor-like storage element under different bias voltages the control electrode and under different charge conditions in the insulator.

The memory element to which the following discussion relates is initially 500 angstroms thick Layer of aluminum on top of that, in turn, to a 1700 angstroms thick SiOr layer is vapor-deposited, which in turn is thermally drawn on a p-type silicon substrate which has a conductivity in the range of 0.2 to 20 ohm cm and an ohmic contact in Has the shape of a conductor on the back. It should be noted that such a memory element in is in no way limiting as to the present presentation; this is especially true for just example explained layer thicknesses.

It is now assumed that the binary number one or L is represented by a positive charge state at the memory location. If this charge is now saturated or at least almost saturated, ie has about 10 ¹³ positive charges per cm ² , and that the potential between the electrode (gate) and the base is more positive than -30 volts: then force those inscribed in the insulator «Positive charges invers the surface of the semiconductor at its interface with the insulator. This means that the surface layer of the p-type semiconductor at the oxide-silicon interface becomes highly η-conductive and has a low resistance in the ohmic sense is essentially free of charge carriers. This depletion layer is assigned a strong electric field perpendicular to the interface between insulator and semiconductor. The extent of this area perpendicular to the interface is only determined by the conductivity of the semiconductor; below the depletion zone lies a relatively massive, field-free p-type silicon semiconductor.

Let us now consider the charge ratios at the non-charged locations that store a zero, at which not all positive charges stored at the interface between insulator and semiconductor can be removed by negatively biasing the element during irradiation by the write beam. ^{About 10 12} positive charges per cm ² of the order of magnitude will remain at the uncharged storage locations. With readout potentials in the range from 0 to -10 volts, the surface of the silicon semiconductor at the boundary to the insulator can be slightly inverted, weakly depleted or weakly enriched, depending on the magnitude of the applied bias voltage and the "history" the charge of the insulator in the sense of what happened before. A weak inversion means that the surface becomes weak η-conductive and therefore not very conductive. The concept of impoverishment has already been explained above; a weak enrichment means

tet that the surface becomes somewhat more p-conductive than the massive silicon base and therefore has a somewhat lower ohmic resistance. Here is special It is important that in the uncharged state the surface of the semiconductor at the interface with the insulator is not strongly inverted (or strongly enriched) and is therefore not very conductive.

Now the movements of the charge carriers that are generated by the reading beam in the semiconductor must and thus the current released from the storage unit to the outside under the two above-mentioned states, namely in the charged state and in the uncharged state are discussed. It must be taken into account that although an electron beam with an initial energy of about 5 to 10 kV and about 50 nanoamps Electricity consumes a considerable part of its energy when penetrating the metal layer and the oxide-insulating layer loses the electrons still have so much energy to create a multitude of electron-hole pairs in the silicon semiconductor substrate. It could then if all electron-hole-carrier pairs to contribute to the current supplied by the storage element to an external circuit, output currents arise, which are possibly several orders of magnitude larger than the impressed electron beam current.

If the entire insulator layer is charged at one point of charge, ie if the charge is a saturation charge or is ^{almost charged with about 10 13} positive charges per cm ² , then the p-silicon at the interface between oxide and silicon is in a strong state Inversion. Electron-defect electron pairs generated by the reading beam in the inversion zone and in the depletion zone of the silicon semiconductor separate in the electric field: the holes or holes go into the solid silicon and the electrons are drawn to the interface. Any charge carriers generated in the bulk silicon, which is essentially field-free, would not contribute to an output current. If the electrons now reach the highly conductive inversion layer at the boundary layer, then they are easily distributed from the actual storage location at which the electron beam is directed, due to the high conductivity of the inversion layer surrounding all data parts or storage locations like a network or perforated plate. that these electrons do not only accumulate at the point where the electron beam itself appears; rather, they will accumulate on the entire capacitor surface, which is connected to the highly conductive, net-like inversion layer, so that not only the part of the capacitor surface bombarded by the electron beam, but the entire capacitor surface is charged. The storage “capacitor” is charged until charge carrier recombinations prevent further charging. Thus, the current observed on the outer plates of the "capacitor" will be a spiked function that carries about 50 microamps of current when the electron beam carries about 50 nanoamps of current.

The readout result is now a position that has not been loaded, that is, a position corresponding to a binary zero consider that has the properties described above; so there is no highly conductive inversion layer in of the silicon surface immediately below the uncharged area. Because of the absence Such an inversion layer, which is a very good conductor, can contain electrons that are present in silicon semiconductors generated by the reading beam, does not affect a significant surface of the component 10 in the way distribute, as was found above for the positions that represent a binary one and are therefore loaded. On the contrary: under the uncharged storage locations generated by the electron beam are on the Area limited to the surface of the silicon rectifier, which is only slightly larger than the actual one Cross section of the electron beam. These

ίο electron concentration quickly dissipates anything Depletion layer field that could exist and the charge carrier pairs generated by the electron beam cannot be separated in the way that this is for the reference cited in the opening paragraph Relationship was not quite correctly assumed. Typical output signals from unloaded, i.e. one Binary zeros are approximately 0 to 10 microamps for an electron beam current of 50 nanoamps. The exact size of the output signal depends on the bias voltage of the control electrode and how much residual charge is present in the oxide isolator due to previous processes. Particularly It is important that the output current of such a unit is not charged, i.e. one that represents a binary zero Digit is at most a fifth of the current that is obtained from a storage location of the storage element, in which a stored one is sampled.

F i g. 3 schematically shows a model circuit of the storage element with the layer sequence metal-insulator-semiconductor-metal for operation with very slow electrons in the electron beam. The circuit symbols in this equivalent circuit diagram have the following meaning:

is = electron-hole current flowing through generates the beam in the depletion layer

will;

CO = capacity of the oxide under the area bombarded by the beam;

Cw = capacity of the depletion layer under the bombarded area;

G't = recombination conductivity below that of

Beam bombarded area;
Gn = conductivity of the inversion layer;
C ₀ - capacitance of the oxide layer without the area bombarded by the electron beam;

C _w = capacity of the depletion layer without the

area bombarded by the beam;
Gt = recombination conductivity with the exception of the area hit by the electron beam.

In the case of the replacement shield according to FIG. 3, the generator U only makes sense if there is a depletion layer that separates those electron-hole-carrier pairs which in turn arise from the impact of the electrons of the beam in the semiconductor layer. As indicated above, the depletion layer - if there were a storage location under a non-charged storage location - would be quickly destroyed in the non-charged state by the carriers generated, or if the element were in the storage state during reading or if it were weak would be inverted - no depletion layer. This would be important in distinguishing between binary ones and binary zeros, ie

when distinguishing the charged state from the uncharged state. The latter condition continues explained below using a multilayer storage capacitor which has an η-conducting semiconductor Im

For the moment it is enough to keep in mind that a p-type semiconductor is being discussed in which a depletion zone arises under the charged storage locations representing a binary one. That component of the equivalent image circuit according to FIG. 1, which changes its properties for these two different charge states, is precisely the generator / * If the corresponding memory locations are positively charged for the binary one, then i _{5 is} relatively large. In the unloaded state, ie in this case with the stored binary zero, / Vkiein.

If one tries now to use a storage element according to the aforementioned reference with data-storing locations of less than about 200 μm center-to-center spacing, then the output current can either or not indicate the state of charge of the insulator at the actual data-storing location. It is assumed for this purpose that the imaginary memory element has a p-conducting semiconductor and a SiO 2 insulator. Positive charges are then generated at certain points for binary ones in the SiC) 2 layer and the charge is removed from the oxide layers at the points determined for the binary zeros. It is further assumed that the locations selected for storage for the respective data do not overlap in the oxide layer and that the state of charge remains indeterminate at other locations on the oxide layer. If the memory locations are large, namely more than 200 microns in diameter, then the output current pulses that arise when the positions corresponding to the binary ones are bombarded with a reading beam with a diameter d of about 200 μηπ are larger than the current pulses that then occur arise when bombarding such places, which correspond to binary zeros. This phenomenon is based on that described above and with reference to FIG. 3 explained mechanism. But if now the effectively storing places have a smaller diameter, z. B. a diameter of 30 or less microns, then the amplitude of the current pulses generated during reading with a similar reading beam does not have a strong correlation with the state of charge in the oxide insulator at the storage locations: This results - in other words - little or not at all characteristic reading.

If you proceed under the conditions described in the previous paragraph, then you are scanning the output current regardless of whether a (so small!) storing point is positively charged or is not loaded, about always the same size, because the large areas outside the relatively small memory locations are always positively charged, so an indication always appears as if the entire surface was charged and therefore would correspond to a positive one. On the other hand, if a point of this size is scanned, its Surrounding the oxide has little or no positive charge, then one always receives signals that are practical correspond to the presence of a zero, regardless of whether there is a small positive charge in the relative large area is present or not. So if there are storage locations, their center-to-center spacing is only about 20 microns or less, then the output current delivered by such a point during interrogation does not depend depends on the charge of the insulator immediately under the reading beam, but rather on the state of charge the surrounding area. This is due to the fact that when the oxide charge of the surrounding area is essentially positive, the reading beam generates charge carrier pairs under conditions in which the electrons run into a relatively large area of a highly conductive inversion layer can, which just results in a large output current of the capacitor. On the other hand, if the surrounding If the surface is primarily non-conductive, the electrons induced by the reading beam have no access to some highly conductive inversion layer, resulting in little or no capacitor current results.

While the above explanation applies to such a memory element with p-type semiconductor, are the conditions for a storage element with n-conducting Semiconductor vice versa: When using an η-conducting semiconductor, one has to do the reading out a relatively high negative voltage of about minus 30-40 volts across the device in such a direction place that the insulator layer is negative with respect to the semiconductor. A weak one forms in the process Charge layer under the positively charged storage locations in the insulator; the highly inverted, conductive one Layer and the corresponding depletion zones are formed under the uncharged areas of the insulator. When reading out, the reverse is true when using an η-conducting semiconductor one described above; storing, d. H. "Writing" in the form of the creation of charged and uncharged storage locations in the insulator layer are the same for both types the conductivity of the semiconductor.

With reference to FIGS. 2 and 4-6, a special operating method of the novel memory element and a circuit developed for this purpose will be described. When proceeding according to the method to be described with the aid of the device, which is also to be discussed in detail, a memory element with p-conducting semiconductors is used. An electrical charge is applied uniformly over the entire surface of the insulator at the interface between insulator and semiconductor. In other words, binary ones are written everywhere, provided that such a binary one corresponds to the presence of a positive charge in the insulator layer at the corresponding point. At selected points that have a minimum distance L of, for example, 20 μm from one another, the positive charge is now removed on areas that correspond to circles of approximately diameter D , where - see above discussion - D is smaller than L and is approximately 10 μm . According to the above assumption, these locations with diameter D represent locations at which binary zeros are or are stored. The charges at the positions corresponding to the binary zeros are removed in the manner described in the reference cited at the beginning i g. 1, schematically indicated switching means 53 is changed or manipulated in order to generate the enlarged points of approximately the diameter D , while at the same time a negative bias is applied to the element in such a polarization that the metallized insulator is negative with respect to the semiconductor layer z. B. be made by defocusing the beam so that

instead of the normal beam thickness of 5 microns those of 10 microns in a practical embodiment however, according to the invention, the writing beam itself is left at its normal thickness of 5 microns and makes him describe a circular path around the center of each such place, so that the place even in the easily recognizable together with FIG Way is discharged. The invention is not restricted to this, as in the exemplary embodiments described here to discharge a larger area with the help of the electron beam, which is actually too thin a

From the above it follows - see again FIG. 2 - that a contiguous insulator surface, which is positively charged overall, surrounds the various data points like a network, since L (about 20 μπι) is greater than D (about 10 μπι) as a prerequisite. At those data locations where ones are written by positive charging, the total area is positively biased in the sense that the insulator is positive with respect to the semiconductor embed themselves in the positively charged »network«. These positive charges now again result in a strong inversion, ie a highly conductive point at each data point, which in turn are connected to the previously generated, highly conductive, reticulated layer that exists on the surface of the semiconductor at the boundary layer of the same to the insulator positively charged locations, therefore ones representing ones, the uncharged, ie binary zeros representing memory locations are relatively free of charge and have a diameter of D, which is chosen so large that it is equal to or greater than a few electron path diffusion lengths in the semiconductor layer and thus ensures that electrons generated during reading recombine before the highly conductive and lattice-like or reticulated and inverted layer is reached. D can therefore be orders of magnitude smaller than in the prior art, the size of D being limited only by the condition that this value must be equal to or greater than a few free paths of the electrons in this material. This latter measure ensures that any electrons that are released recombine before they can reach the positively charged lattice layer, where they could then neutralize the overall charge.

From the above it follows that the mean free path of an electron in a semiconductor is as follows It should be as small as possible to allow recombination of electrons in the uncharged areas is reinforced. To achieve or promote this, the silicon semiconductor can be doped with gold, that gold is allowed to diffuse in from the back of the silicon after the SiOj layer has been formed but before the conductive aluminum layer was evaporated onto the front of the insulator. That Doping in such a manner is a prior art method to increase the lifetime or the free Reduce the path length of electrons in semiconductors. There is another possibility, the free path lengths to decrease the electrons on the surface of the silicon semiconductor: one brings in the oxide insulator layer a multitude of recombination centers at the interface between the oxide and the silicon a. For this purpose, the oxidized silicon platelets are tempered for several hours in an oxygen atmosphere at temperatures in the region of 800 degrees C. Also this basic process for the creation of recombination centers is state of the art.

F i g. FIG. 2 is a top plan view of a corner of a memory element as described with reference to FIG. 1 explained and that was treated in the manner described above when saving. The surface of the insulator 13 at the interface with the semiconductor was positively charged uniformly over its entire surface, so that a state of saturation was reached by

κι about 10 ¹³ positive charges per cm ^{2 was} marked. This could e.g. B. have been achieved by letting the writing beam describe the entire area ζ. B. in a raster process or by allowing the beam to travel over the entire surface

is and at the same time a positive DC voltage on the order of a few volts above the "capacitor receives" upright Thereafter, an electron beam with a beam diameter d of about 5 μΐη successively on each data point addressed, with two data

2 (i represent each other always Miitenabstand L have. G In the arrangement according to F i. 2, the data points in rows and columns, each with a distance of L arranged During writing, that is, when storing the data of the electron beam is described in the above-

2f. Way "manipulated" in order to process the data location with about a diameter D , with D being of the order of magnitude between d and L connected positively charged surfaces receives; At those points where binary zeros are to be stored, the capacitor is negatively biased while the write beam is directed at the corresponding point, and at the same time the corresponding point of diameter D is processed by the write beam in the manner described above. It can be seen that in the embodiment according to FIG. 2 in the top line the binary

• to one-zero, in the second line the binary number zero-zero and the binary number one-one-zero is stored in the third line.

The procedure for reading out the memory element described in this way is as follows: The bias

Ί5 of the metallized insulator against the semiconductor substrate is set to a value between 0 and -10 volts, so that the silicon surface under the positively charged oxide insulator surfaces go into strong inversion and the remaining uncharged places where the binary zeros are located , are quite weakly inverted, but do not conduct strongly. The reading beam of diameter d is then directed onto the locations that store the data. If the reading beam is directed at a positively charged storage location, a large output current of typically around 50 microamps is generated across the storage element, which is connected as a capacitor. If, however, the reading beam hits the center of one of the uncharged areas, i.e. areas representing binary zeros, from which the oxide-insulator charge has been removed, the resulting output current is considerably lower, typically less than 10 microamps. This enables an unambiguous differentiation of the charge state of the oxide insulator at the queried point to be recognized.

Theoretically, the following happens: Only then can a large charging current be applied to the capacitor occur when the reading beam covers an area of the oxide

isolator meets, which is surrounded by a large and contiguous area of the insulator, which in turn is positively charged by uniformly distributing or applying positive charges over the entire surface of the insulator and removing this positive charge only in those places where the zeros are stored should, a large charging current is generated at the positively charged storage locations siq; in this way one obtains an unambiguous, & h. Readout of the digits storing a binary one that can be reliably identified at any time. Since the diameter D of the binary zero digits is smaller than the smallest distance L between the corresponding zero-storing locations, there is always a grid-like area of positively charged insulator layers, regardless of how many data locations with stored zeros are in the recorded data . These conditions ensure that when the reading beam hits a positively charged data location in the oxide insulator, the carrier current induced under the storage location can flow without significant resistance into the large area of the highly conductive and inverted silicon semiconductor, which is located under the corresponding reticulated area of the positively charged oxide insulator lies. A large area of the storage element is therefore touched, which leads to the generation of a large output current which is characteristic of the positively charged storage locations which correspond to the binary ones.

If the reading beam hits a data location approximately in the middle that is not charged and thus represents a zero, electrons that are formed in the silicon semiconductor under the action of the reading beam cannot reach the edge of the uncharged, zero-representing areas with a diameter of D. where they would have the opportunity to interact with the highly inverted and highly conductive grid. This is due to the fact that the extent D of the uncharged data locations representing zeros is chosen so that it is several path lengths of the electrons in the material greater than the diameter d of the reading beam. In this way, electrons generated by the electron beam recombine in the semiconductor before they can diffuse into the highly conductive inversion layer. When the electrons have recombined, they are no longer available as charge carriers. The electrons generated by the reading beam can only charge that area of the interface between the oxide insulator and the semiconductor that is hit directly by the reading beam. As a result, there is at most a very small output current from one plate of the "capacitor" to the other. It should be pointed out that in the practical case some electrons generated at uncharged storage locations can reach the inversion layer, where they then contribute to charging large areas in the entire storage element. The ratio of the reading beam diameter d to the diameter D of the storage locations is chosen so that a sufficient number of these electrons recombine before they reach the strongly or highly conductive inversion layer. The result of these relationships is that the amplitude of the charging current is considerably different, depending on whether a charged memory location (binary one) or an uncharged memory location (binary zero) is scanned. By doping with gold or heating in an oxygen atmosphere at high temperatures, the diffusion of electrons generated by the write beam from the uncharged storage locations into the highly conductive inversion layer can be further reduced, which in practice amounts to an increase in the difference in readout currents

It should be pointed out here that the opposite of the reference made to FIG. 2 explained process in reverse takes place if the inferior semiconductor were an η conductor. If an n-semiconductor would be used then the total area of the

ίο storage element uniformly uncharged. If, for example, one would like the binary ones to be characterized by a large output current when reading them, while one would like to have a negligible or practically nonexistent current pulse when reading zeros, then the binary ones would be represented by unloaded storage locations that are uniform with the uncharged grid layer are connected over the whole surface of the insulator layer. Conversely, the binary zeros of positively charged areas would then be displayed. Similar to the procedure described above, however, it would again apply to the positively charged memory locations that represent zeros that D must be smaller than L.

When reading out such a memory with n-conducting semiconductor, a read-out potential of approximately -30 to -4OVoIt is required in order to generate the necessary inversion region in the semiconductor layer under the uncharged areas of the insulator. In the area of the positively charged storage locations, at most a weakly enriched zone is generated.If the reading beam reads the uncharged, binary ones corresponding locations, the electrons generated can flow into the highly inverted and highly conductive grid-like layer, which creates a powerful output current pulse If the reading beam hits the positively charged storage locations, electrons generated by the electron beam cannot enter this highly conductive and highly inverted network-like layer and consequently recombine in the areas of diameter D, which again correspond in size after a few electron path lengths in the semiconductor. As a result, at most a very small output current is generated, which - this is the most important - can be clearly distinguished from the relatively strong current that is generated when reading out unloaded data locations of a memory of the type discussed here, if the memory is an η-conducting semiconductor used.

What is important here is the observation that the state of charge in the oxide insulator directly below the position read is practically of no significance for the mode of operation of a storage device which is so closely "described" in the manner on which the invention is based. Essentially, only the charge state of the oxide insulator in the region of the regions of diameter D is important , specifically at those points which practically touch the impingement surface of the reading beam directly. The amplitude of the output current is determined practically exclusively by the parts of the data points with a diameter D , which directly surround the impingement surface of the reading beam, so to speak, in a ring shape. If the state of charge of this ring area just defined is such that the electrons can get through the beam in the semiconductor into a large area of the network-like, highly conductive and highly inverted layer underneath, then a large charging current or discharge

adjust current. However, if this ring area, which lies within a corresponding storage area of diameter D and outside the immediate impact area of the reading beam, does not form an electrically conductive path for those electrons that are generated by the reading beam, then those electrons - which cannot migrate properly - have the tendency , within a total of a few free paths of electrons within the storage locations

If the entire "capacitor" was negatively biased during the bombardment, the bias voltage on the storage element, ie on the "capacitor", is reversed so that it is positive, and then only an area with the diameter "/ (smaller than D!) fired in the middle of the uncharged area D for an equivalent time; now this area has the properties, ie the "appearance" of a binary zero when it is subsequently read by an electron beam.

to recombine, as a result of which no output current or io sen, the diameter of which is ½, since the charge is at most an extremely small output impulse is generated by the oxide isolator immediately below the Auf-Es the result is that the charge state of the oxide-isolating point of contact of the reading beam has no influence on the output below the point of impact of the reading beam without a large output current pulse, which has the meaning explained above is, so there is more or less free choice on the storage element It is particularly important bar is These facts discussed last are for 15 that the relation of the time of the bombardment with negatidie Explanation or teaching important, how to get such ver bias at the time of bombardment with positive Memory operates so that interactions between bias voltage can be chosen so that scattered ledges different storage locations are as small as possible. trons far from the center of the writing beam.

In the case of data memories that are essentially sandwiched away, as much positive charge as are tall during the sequence-like body of the sequence metal-insulator-semiconductor-metal replace the bombardment of the central area d , there is no significant interaction between the previously carried out Original “Beden storage locations about the capacitor itself to be labeled” of the area away from the diameter D fear. But it is the writing beam and the reading became. This process is repeated every time if ray is not infinitely precisely definable; Although the large majority of the electrons, denoted by a binary zero, of the electrons are written in such an electron, so that there is no tendency for the electron beam to fly to data points or other areas lying very close to the central axis of the beam, there are always some electrons present which to discharge in the oxide insulator, which should not retain a positive charge in the more or less theoretical impact surface.

fall. As a result, there are always some electrons when reading out data from the storage element

when reading and writing, which are statistically over 30, the process described above can be carried out again to achieve a surface area of the entire memory element distributed over a certain symmetry. The meet. Over a possibly long time or over several reading beams of diameter d over the respective operating cycles, the integrated effect can be centered so data points while the storage element is rather scattered electrons large areas of the whole con-negatively biased. Charge or discharge during the Hedensators «readout phase. In order to avoid these scattering of the two capacitor plates by means of suitable electron effects, the following switching means can be used on a recycling device, for example a device: computer or detector. Following this, ie after the

In order to minimize the effect of scattered electrons hold, one can first try to reverse the polarity of the voltage on the storage element, so that it is now how much positive "stray charge" generated in this way is more positively charged in the 40 and then the same becomes a data isolator generated while writing; the place next for an appropriately selected time The step of this procedure then consists in shooting that corresponds to the time of reading, or to it a corresponding amount of such "stray charge" is in the ratio explained above. This means that they are positive To remove the sign. In a similar way to as many scattered electrons as during the readout Incidentally, it also occurs when reading out when the memory 45 generates the data location with a negative bias voltage cherelement is biased negatively, a reduction were just as much with positive bias in the tion of the positive charge generated by the insulator due to the following regeneration script, so that one explained scattered electrons. Here, too, one can hold firmly - i.e. the interaction of those lying next to each other, how much positive amount of charge is removed, brings tenstellen to a minimum, as well as the and then reapply positive charges accordingly. The long-term effect of scattered electrons leaves a grid-like surface that contains all data points compensate each other in the manner now to be described. surrounds. Assuming that the charging time of the Assume that there is a p-type silicon in the oxide insulator and the discharge time of the same is an Ii storage element is used. At the beginning of the linear function of the radiance of the electron beam The write process is then 55 everywhere in the oxide insulator and the bias voltage on the memory element is then to find positive charge. Then unloaded, the order in which these regeneration steps are binary Storage locations representing zeros take place at certain of the individual data locations, apparently from th places. While writing the binary minor.

Zeros will keep the potential of the substrate negative- Another method of overcoming the effect

and from this it follows that the desired background of those electrons which strike relatively far from the center of the positively charged insulator, which removes all the data from the beam, consists of those surrounding and continuous positive The density of the metal over which the net forms, which has a tendency to discharge due to the insulator, which is the effect of the electron beam, which is explained by the scattered electron radiation. In order to be exposed to bring to an optimal value. To counteract this effect, that is to say to compensate for it, it has been observed that if they initially zero, then after a binary bombarded first metal layer is aluminum and has been written to zero by writing a positive one Charge thin, e.g. B. is about 500 Angstroms or less thick, has removed from an area of diameter D , where disturbance effects occur, which affect multiple reflections

let xion and backscatter electrons return; part of the incident beam is practically reflected back and forth between the storage capacitor and other surfaces within the electron beam path. In order to suppress undesirable effects of this type, the first or topmost aluminum layer should, according to a finding within the scope of the invention, have a thickness of several thousand angstroms. Another metal can also be used which has an areal density of 50 micrograms per cm ^2. A material with a low backscattering coefficient, e.g. B. carbon, can be used to coat the reflective surfaces within the working electron beam. Due to the greater thickness of the unit area, the reflected electrons lose some energy during passage through the uppermost metal layer, so that they no longer have to multiple reflection enough energy insulator layer oxide za pass through the metal film pass back into the underlying. Of course, a thicker first metal layer attenuates the electron beam; With this in mind, an optimal thickness for aluminum as the first metal layer has been found to be on the order of 2000 angstroms ± 500 angstroms; this is a compromise between the requirement to avoid scattered radiation or back radiation and, on the other hand, the requirement to attenuate the electron beam as little as possible.

In Fig. 4 is a functional block diagram of a memory system represented according to the invention, with the help of which data are imprinted and read out as this has been explained in detail above. In Fig. 4 is denoted by 20 a cathode ray tube, which has a micro-deflection or scanning device

This tube 20 has a plurality of micro-deflecting lenses, which in one to the electron beam substantially perpendicular plane are arranged. The one generated by a conventional radiation source The electron beam is finely bundled and then roughly through a coarse deflection system onto one of these small ones Micro-deflecting lenses steered These (electron) lenses can now be selected from the many storage elements according to FIG. 1 be arranged, namely approximately in accordance with FIG. 6 in an octagonal pattern. The whole Number of storage elements is arranged in an octagonal pattern that has a maximum size of about 6 χ 6 cm. The arrangement consists of individually manufactured storage elements or an im whole manufactured component on a common semiconductor substrate, what with known technologies can be done. Of course, it is also possible to use the individual storage elements as a whole square in columns and rows similar to the arrangement of the data locations according to FIG. 2 to be arranged. Optional you can also choose other patterns for the actual data locations, e.g. B. a hexagonal pattern or any other face-like arrangement of. individual points, depending on how you are makes best use of the available space and equipment; It is important that you get the data can put according to the invention close to each other.

Within the tube 20, the sharply focused electron beam is directed by the X- K coarse deflection lens system onto the field of the fine adjustment deflection lenses. The coarse deflection can, for. B. use staggered electromagnetic lenses to ensure that a selected fine deflection lens is perpendicular to the lens plane hit by the beam. If electrostatic plates are used for coarse deflection, an accelerating lens can be used for the same purpose. The selected fine deflection lens then lets the electron beam fall by means of corresponding deflection signals at its electrodes onto selected or thereby controlled data locations of the corresponding downstream storage element. While the electron beam now scans the surface of the selected storage element from data location to data location by the Xy fine deflection system, the beam is switched on and off by a scanning circuit 42 which is connected to the control electrode of the tube 20. A high voltage supply 41 now supplies the actual electron beam. Generator, the focusing lens, the coarse deflection arrangement and the fine deflection arrangement with the appropriate voltages or potentials. 43 is shown in FIG. 4 the signal generator for the coarse deflection in the ^ direction; 44 is the control signal generator for the coarse deflection in the K direction; 46 is the signal generator for the fine deflection in the ^ -direction and 47 is the control generator for the fine deflection in the y-direction. These signal generators 41-47 are essentially digital-to-analog converters; they receive input variables from a computer, which contain digitally encoded position and control signals, and convert these input signals into corresponding - analog - deflection voltages or currents, so that the electron beam (for storage and reading) of the tube 20 with the correct intensity on the selected data location of a selected memory element falls.

To supply the signal generators 43 to 47, an address register 62 is provided, which stores its input variables from the computer system with which the entire memory is to work together. Register 62 gives its output through suitable UN D gates 64 to 67 to each of the generators 43 to 47. In addition to the receive digitally encrypted control signals representing the addresses and causing the distraction the AND gates 64 to 67 probing potentials from a time switch and logic gate circuit 61, as well as from a refresh register 63 for the addresses. The purpose of this latter register 63 will be described below explained in detail; first of all it must be noted that during such periods in which the Computer uses the storage tube 20, this refresh register 63 is only used for the AND gates 64 to 67 turn on, so that the digitally encrypted address signals from the address register 62 to the coarse and Fine deflector circuits 43 to 47 can arrive. During the times in which the tube 20 does not diverge Computer is used, the refresh address register takes over 63 the control of the signal generators 43 and 47 in the sense of a reading used for refreshment and renewed storage of the data locations.

The logic control circuit 61 with time function is used both to receive information from the computer system as well as to issue instructions to the computer system to be sent to the input-output circuit the computer system to transmit the facts in a message that a certain, to be stored Information was recorded, such information was read out, etc., respectively according to the commands entered. In addition to controlling the operation of both the address register 62 as well as the refresh register 63, as well as for applying the probing potentials to the gate circuit ^

64 to 67, the circuit unit 61 controls the operation of a generator 48 for the circular scanning track, the output of which can also be controlled by the fine controls 46 and 47 for the ^ -direction and the V-direction. When the generator 48 is activated, the X and K fine controls 46 and 47 cause the writing electron beam with a diameter of d = 5 μm to describe a circular path at a preselected data location on the surface of a memory element with a diameter of D = about 10 μm. Other technical measures are available to those skilled in the art in order to produce the enlarged areas of diameter D corresponding to a circular area of diameter D. Similarly, a raster generator 49 is provided to control the operation of the signal generators for fine deflection in the X and Y directions; the raster generator 49 is in turn under the control effect of the logic control circuit 61. When the raster generator 49 is touched, the fine controls for the X and K deflection cause the writing beam, a raster scan over the entire surface of a storage element under the small deflection lens assigned to this element, which in turn was selected by means of the signal generators 43 and 44 responsible for the coarse deflection. In other words: the generators 43 and 44 search for a specific memory element within the framework of the entire scanned memory, while the generators 46 and 47 then take over the scanning of the selected element.

The control circuit 61 also controls the application of suitable polarized bias potentials to the respective storage elements during the write and read processes.

For this purpose, a number of Treiberkrei- it sen 51 / 4-51N provided; they are used to apply either a positive or negative bias voltage to the respective storage "capacitor" that is in progress. For this purpose, for each memory element, that is provided for each "capacitor", such a driver stage and the time ratios of the operation of this stage are controlled by the control circuit 51 from respective input-output data registers 7 \ A-7 \ N receive the drive circuits 51a- 51N signals relating to the respective correct polarity of the bias voltage which is to be applied to the assigned memory element when processing a specific data location. The registers 71Λ-7iy behavior the input data from the computer to be written into the memory; these components also serve to return the read data back to the computer. The registers 71 can be of conventional design and have flip-flops connected to one another, which in turn represent, to a certain extent, short-term memories and are suitable in a known manner for data storage. These flip-flop arrangements can, for. B. be designed to store a data set corresponding to a word in binary form or binary data in decimal form. To control writing and reading in this sense. The control circuit 61 sends control signals sequentially in time to selected data registers 7 \ A-7 \ N. The control circuit 61 also controls the operation of further output amplifiers 21 / 4-21 / V for one storage element each, ie one "capacitor" each in the sense that the selected amplifier 21 supplies output signals to the downstream register 71 at predetermined times during the reading process ; further causes the associated downstream amplifier 21 to be blocked during certain parts of the read process and during de write processes. The bias drivers 51 / 4-517V and the downstream amplifiers! 2 \ A — 2 \ N can be of a known type; they are used to apply the required bias potential within the available switching periods and only need to have a response behavior that is suitable for processing the signals read out.

During a write operation, the connection circuit of the computer supplies the selected registers 7t with the data that are to be stored in a specific memory element, ie in a "capacitor", one word at a time. At the same time, the computer informed the time control circuit 61 that the data should be written into the actual memory and supplies the address of the location in the memory where the data is to be written to the operating address register. The address can be in the form of a binary coded address signal, which goes through the AND gates 64-67, and the circuits 43, 44 for the coarse adjustment and the circuits 46 and 47 for the fine adjustment actuated, so that the beam at the desired point, ie data location of a certain data memory or "capacitor" arrives. The circuit 61 then allows the electron beam to run over a selected series of data locations in such a way as will be explained in detail further below with reference to FIG. when the beam has then arrived at the desired data location, the circuit 61 causes the circular track generator 48 to start up; as a result, the write beam is then guided in a circular path of diameter D , while a suitable bias potential is applied to the storage element by the associated driver circuit 51 in accordance with the data stored in the associated register 71.

If you want to rewrite that information, for example in an entire memory element are stored, or that are stored in a certain area of a storage element, then the computer can control the control circuit 61 to touch the raster generator 49, so that this the Electron beam runs in the form of a raster scan over the defined area in order to make this area uniform to charge or discharge, including a suitable bias potential through the associated driver circuit 51 is delivered. If the individual storage elements or "capacitors" have a p-conducting Have semiconductors, then is the potential supplied by the driver circuits during the raster scan positive so that the insulator surface is uniformly charged with positive charge. If the The corresponding storage element is one with a n-conducting semiconductor Driver circuits apply a negative bias potential to the capacitor or to the storage element during this raster scan takes place upon completion of the enrollment or storage of the Data, the circuit 61 informs the computer that the storage has been completed, and that the corresponding data are also stored.

While reading previously stored information, The computer first informs the control circuit 61 of the "request" for the readout. Of the The computer supplies the address of the stored data to the work address register. This register then directs

the beam to the area on memory where the desired data is stored while the circuit is running 61 the corresponding driver 51 touches so that this or this a negative read potential to the place appropriate storage element; the circuit 61 also scans the associated amplifier 21 to the To output data from the storage tube capturing the same to the working registers 71. The signal generator 46 and 47 for the fine adjustment and possibly also the signal generators 43 and 44 for the coarse adjustment then cause the Scanning movement of the electron beam over the addressed address locations, with the information read out one after the other and, as it were, passed word for word through the register 71 to the computer will. After completion of the reading process, the circuit 61 then sends a signal to the computer, soft means that the readout process has been carried out completely.

The arrangement according to FIG. 4 has the peculiarity that it does not falsify the stored content can occur due to the integrated effect of scattered electrons; in the present case this is the result ensures that each bit is continuously rewritten after a read, i.e. H. saved again will. The technical means for this process are as follows: The control unit 61 ensures that the for Both write and read electron beam every time it passes through the signal generators 43-47 has been brought to a specific data location, the read-out first automatically, one after the other of the data stored there, and then rewrites the data that was in this data location, before the beam is directed or directed to the next data location in the course of the scan. this will achieved in that the output of the output amplifier is detected to the output register 71 and that the bias striker 51 for the following read-write operation at each data location so that it is either a binary one or a binary zero correctly writes again, depending on the reading taken recently on the same Job. The signal from the assigned amplifier is used as the output variable for rewriting 21 used.

During those times when the entire memory is not "used" by the computer, the The control circuit 61 sends the refresh register 63 to the electron beam all of the data one by one read out, save and save again. During those periods in which the Computer does not need the memory altogether, the refresh register 63 continuously reads all data in the Storage with immediate respective restoration. If now during such a refresh cycle or cycle 'the computer touches the memory, either for the purpose of reading or for the injection of data, the refresh cycle is interrupted and it becomes the point of time of the interruption is stored in the refresh register 63. The memory then reacts to the probe eo from the computer and upon completion of the answer to the touched question, the refresh cycle begins again and continues until the computer next time either to query or in other words: the data locations in the memory are read continuously and rewritten each time to avoid blurring or even a loss of the data in the memory due to the above-mentioned scattered electrons. In addition, during each reading and renewed write cycle after writing or reading either a binary zero or a binary one One using the appropriate bias potential automatically reverses the bias potential and the respective center of the data locations is bombarded with electrons for as long as the time The time for the read / write cycle corresponds to the effect of stray electrons on adjacent data locations to reduce or not to change the overall charge level of the storage tank.

Another possible method is to read the data and temporarily store it in the working memory of the Computer or other peripheral memory in the system. This is then all rolled into one Storage element applied to stored data. The relevant storage element, d. H. the respective »capacitor« is then completely rewritten, with the step of uniformly charging the surface of the isolator is started. This becomes automatic after a predetermined number of work cycles made under the control of the computer; you can proceed from the program as follows: that this type of refreshment during the rest periods after completing the predetermined number is carried out by cycles.

In the following, let us refer to FIG. 5 received: It will Working of a memory element according to the invention explained with the aid of some time functions. The explanation is based on the following series of individual processes:

1 write - 1 read
1 write - 1 read
Write 0 - read 0.

The relationships are shown on a memory element with p-conductive silicon.

The top representation (a) of FIG. 5 shows the course of the bias voltage across the storage element versus time for the sequence of individual processes just mentioned. In this illustration a, this bias voltage is denoted by Vcs. This bias voltage is recognizable when a binary one is written. + 5 volts When this binary one is read, the bias voltage is

- 5 Voit; then the rise to +5 volts comes accordingly writing the second binary one and then falling back to - 5 volts corresponding to the second Reading a one. Then the bias remains on

- 5 volts for both writing a binary zero and reading a binary zero. The time intervals t with indices have in FIG. 5 (a) has the following meaning:

U build-up or rise time of the electron beam and start-up time for its circular track; Value: at least about 50 nanoseconds

f2 switch-on duration of the electron beam; Value (dependent from the beam current): at least about V2 microseconds

ti switch-off or fall time of the electron beam and switch-off time for its circular track; Value: at least about 50 nanoseconds

U rise time for the bias signal; Value: at least about 100 nanoseconds

i ₅ reading time; Value: at least about 500 nanoseconds

te fall time (corresponds to the time of the switch-off process) of the electron beam; Value: at least about 50 nanoseconds.

SS; .Sr

F i g. 5 (b) shows the time profile of the electron beam current which is switched on and off by the contacting circuit 42 via the control electrode of the actual electron source in the tube 20. The measures required for this are familiar to the person skilled in the art. A comparison of representations a and b in FIG. 5 shows that the electron beam is switched on after a time t \ has elapsed, within which the potential between the plates of a storage element has risen to 5 volts; according to the above requirements, this is the beginning of the writing of a binary one. The time t \ is about 50 nanoseconds and two processes take place within this time: On the one hand, the circular track movement of the beam builds up, and on the other hand, it is the actual rise time of the beam until it reaches its working current of about 50 nanoampere, starting from the value zero. The beam is now maintained during the actual writing time Γ2 of about V2 microseconds, this writing time depending on the current of the electron beam.This is followed by a time interval f ₃ , which corresponds to the reverse process of what happens in fi: within this approximately 50 nanoseconds the circular motion process of the beam is switched off and at the same time the electron flow of the beam falls back to zero ("falling edge"). F i g. 5 (c) shows the time relationships between the switching on and off of the generator to generate the circular track of the beam. It can be seen that the intervals t \ and h at the beginning and at the end of each such working interval of the circular track generator are selected so that the circular track generator has fully started before the beam current has reached its maximum working value, and that this circular track generator is only switched off again, if the beam current has already been switched off. In other words: it is ensured that as long as the beam current is at the working value, the circle track generator is also fully, ie works within the times for the rising edge and the falling edge.

After the time ti , the bias voltage across the capacitor-like storage element is switched to the reading potential of -5VoIt, and after the setting time U, which lasts about 100 nanoseconds, the reading beam is switched on.It can be seen that the electron beam has about the same current intensity when reading and writing and about the same energy of 5-10 kilovolts. There are no reasonable physical reasons why the anode-cathode voltage of the write or read beam should have no other value. In order for the irradiated storage element to emit an output current, electrons have to pass through the upper conductive layer, which is one plate of the "capacitor", and through the insulator into the semiconductor layer. It is further desirable to have an output current pulse several orders of magnitude greater than the beam current. For this it is necessary that the electron beam penetrates a few 1000 Angstroms deep into the semiconductor layer of the storage element. In other words: The beam should still have at least 2000 electron volts after it has passed through the first conductor layer and the underlying insulator Manufacturing memory elements with very thin but non-conductive insulator layers has been found to be a practical way of using insulator layers with a minimum thickness of about 1700 Angstroms for memory elements with a surface ^{area of about 0.4 cm 2.} With such a component or such a storage element, the electron beam energy at the interface between the conductive layer and the insulator layer must be at least 400 electron volts. The thicknesses or densities for the upper conductive layer, which is always to be penetrated by the beam, are therefore chosen so that the electron beam has at least 4000 electron volts after penetrating this layer. This value then determines a practical lower limit value for the energy of the electron beam. Electrons with such high energy that they can penetrate more than about 1 micron deep into the semiconductor layer do not produce a stronger output signal (in fact mostly a smaller signal) than those electrons which are stopped within a distance of 1 micron. A thick insulating layer of approximately more than 0.5 microns and the first conductive layers that are too thick also scatter electrons unnecessarily and thereby contribute in an undesirable manner to a blurring of the effective beam cross-section. Although relatively thick layers can safely be used, they certainly do not serve to improve the usability of a memory element in the sense described here; at least they require the use of an electron beam of greater energy. The above discussion is intended to express the following: The values described using the example can, if one considers other embodiments of the invention, quite different values; it is easily conceivable that the electron beam voltage assumes any values between 4000 and 100,000 volts, depending on what kind of substances and what kind of dimensions are used for the storage elements.

A noticeable difference between the reading beam and the writing beam can be seen in the illustration given here in the duration of the application. The reading beam is applied for a time fs of the order of magnitude of 500 nanoseconds. During this reading interval the generator for generating a circular track of the beam at the point of impact is of course switched off, as can be seen from FIG. 5 (c) recognizes. The interval fs is followed by an interval U, from here about 50 nanoseconds, after which the process explained so far, ie up to this point of the description, begins and runs again, as shown in FIG. 5 clearly shows

At the end of the reading of the second binary one, ie at the end of the second interval ie, one recognizes that the negative bias potential of -5 volts remains on the two plates of the "capacitor" after the third interval U has expired, in which the circle track generator has started and the electron beam has built up The electron beam is present again and remains for a third time ti , during which a binary zero is written while the bias potential of -5 volts remains F i g. 5 (c) that while the binary zero is being written, the circle track generator remains switched on as long as it is when the binary ones are being written. Reading out the binary zero at the corresponding data location is the same as reading out a binary one at another corresponding data location comparable.

The representation (d) of Figure 5 shows the output voltage over the load resistance during the above with reference to the F i g. 5 (a) -5 (c) Processes, whereby the respective points in time lie one below the other. You can see that at the beginning and at the end

27

of the writing of the ones, sharp voltage spikes arise due to the charging and discharging of the storage element (which is a capacitor!) by applying the bias voltages that are used when writing the ones needed. While writing the ones, i. H. in the interval f2, a corresponding one arises high output voltage across the capacitor. By appropriately touching this input to the assigned Amplifier 21 (see Fig. 4!) These voltage pulses are filtered out of the output signal, which is from comes to the whole storage system. The required information only appears during the respective intervals fs of the reading process and are relatively sharply rising voltage pulses that occur precisely in the reading intervals, d. H. in the intervals fs. Now referring to FIG. 5 (d), the during the three periods fs compares the output pulses that occur, then one finds that the two pulses that appear for the first time while fs are orders of magnitude larger than the last, i.e. H. output signal arising in the third interval fs at the end of the time axis in Figure 5 (d). This latter signal is the readout result of a binary one Zero, d. H. the electrical result of scanning an unloaded data location. They are recognizable in the Time intervals fs depending on whether a one or a zero was stored, so different that they can be clearly distinguished from one another.

The representations of Fig.5 relate to a Storage element whose semiconductor is p-conductive If one uses an η-conductive semiconductor instead, With a few exceptions, curves are created that are essentially mirror images of Fig. 5. The most important such exception from the mirror-image relationships compared to FIG. 5 is the value of the invested Bias while reading. If one uses semiconductors of the η-conductive type, then the read bias is about - 30 to - 40 volts Because now the switching of voltages of this value - although It is entirely possible - it is less desirable to use p-type semiconductors in the exemplary embodiment of the invention described here Type.

For this purpose 3 sheets of drawings

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Claims (15)

Patent claims: 1. A method for operating an insulator layer with a semiconductor layer arranged thereon containing data memory, a) its data from local charges assigned by data points, which are located in the insulation layer are located in the insulator border area to the semiconductor layer and the space charges in the semiconductor layer in the semiconductor border area induce to the insulating layer, are represented, b) in which the insulator and semiconductor layers are in between Electrodes are arranged for applying a potential, c) for the data by bombarding it with an electron beam written, deleted or read out, whereby: (1) to write or erase voltages of opposite polarity to the Electrodes are applied so that by separation of the electron beam charge carrier pairs generated in the insulator boundary region, the local charge is generated or removed, and wherein (2) the reading takes place in that a current pulse appears between the electrodes or not, depending on whether the electron beam is in the semiconductor boundary area generated charge carrier pairs separating space charge is present in the semiconductor boundary area or not is available, characterized in that d) the first time the isolator boundary area is put into operation, the entire surface is calibrated is charged so that a strong inversion layer is generated in the semiconductor boundary region, and that e) in the subsequent normal operation, the charge at the data locations that represent one binary value is left unchanged, and the charge at the other data locations that represent the other binary value is removed in a range of diameter D , where D is of the order of a few electron diffusion path lengths corresponds in the semiconductor layer, so that f) when reading out with an electron beam with a diameter d, which is smaller than the data point diameter D, the discharge of a charged data point is coupled to the strong inversion layer and a large current pulse is generated and the current pulse of a discharged data point is at most a fifth of the current pulse that one received from a loaded data location. 2. The method according to claim 1, characterized in that the data locations with the diameter D are charged or discharged by defocusing the electron beam diameter from d to D. 3. The method according to claim 1, characterized in that the data points with the diameter D are charged or discharged by the electron beam of diameter d is guided around in a circle on the data point of diameter D. 4. The method according to any one of claims 1 to 3, characterized in that one immediately after reading out each data location - regardless of its state of charge - the data that existed before reading out State of charge writes in again 5. The method according to any one of claims 1 to 3, characterized in that the electron beam of diameter d is automatically directed to the center of the data point immediately after writing a data point of diameter D and this is irradiated while a potential is applied to the electrodes, that is opposite to the polarity selected for writing, this post-treatment following the writing being carried out for a length of time that is comparable to the original writing time, whereby an interaction with adjacent data locations due to stray electrons during the irradiation is reduced to a minimum. 6. The method according to claim 5, characterized in that one automatically after reading of each data point automatically reverses the polarity of the applied voltage, but the The electron beam continues to fall on the data items for as long as the time of reading corresponded to the data location, causing an interaction with adjacent data locations is brought to a minimum by stray electrons during irradiation. 7. The method according to any one of claims 1 to 6, characterized in that one during the rest periods of the memory automatically refreshes the data by reading out the data and then again enrolls. 8. Data memory for performing the method according to one of the preceding claims, characterized characterized in that the semiconductor layer (12) is doped with foreign atoms so that the free Path length of an electron in the semiconductor boundary region to the insulator layer (13) is as small as possible. 9. Data memory according to claim 8, characterized in that that one uses materials for the insulator layer (13) and for the semiconductor layer (12), which have a low backscattering coefficient to avoid multiple scattering of electrons avoid. 10. Data memory according to one of claims 8 or 9, characterized in that its from the Semiconductor (12) and the insulator (13) existing part in a gas at about 800 degrees C for so long was annealed, so that a large number of recombination centers for electron-hole charge carrier pairs is present in the semiconductor boundary area. 11. Data memory according to one of claims 8 to 10, characterized in that the electron beam source (52) facing, first electrode (15) is made of aluminum and has a thickness of approximately 2000 ± 500 Angstroms and that there is a SiO2 layer (13) on it, which in turn is thermally applied a p-type silicon body was grown. 12. Data memory according to claim 11, characterized in that the first electrode (15) has a density of about 50 micrograms per cm ² for reducing tion of the effect of scattered electrons 13. Storage element according to one of claims 8 to 12, characterized in that the semi-conductor limit area is endowed with gold The present invention relates to a method according to the preamble of claim 1. It also relates to a data memory for carrying out the method. Such a method and such a data memory are from "Applied Physics Letters", Volume 16, No 4; dated February 15, 1970; pages 147-149) The reference describes the charge storage and readout mechanism in a storage element, which is essentially a set of a metal layer, an insulator, a Semiconductor and another metal plate is an electron beam directed perpendicular to this multilayer capacitor and there is a potential of alternating polarity - depending on whether information is entered or whether information is read out - to the capacitor placed When data is written, electrons of the write beam enter the insulator through the metal film and lift electrons from the valence band or from traps in the energy band gap of the insulator into the conductivity band. When the applied potential is positive, these electrons flow through the applied electrical Field out of the insulator and therefore leave positively charged points in the insulator next to the interface between the insulator and the semiconductor. The location of the stored positive charge in the isolator and the Size of the same is determined by the size and polarity of the during electron bombardment and of the Determined location of impact of the electron beam. If the designed potential is negative, then flow positive charge carriers (defect electrons, holes) in the vicinity of the interface between insulator and semiconductor out of the isolator. By appropriate selection of the insulator layer and the semiconductor layer, both a charged State as well as an uncharged state can be maintained practically indefinitely, if only the ambient temperature is around 300 Kelvin, and if there is no destructive ionizing radiation prevails, such as B. X-rays, electrons, protons and the like. Because thereby the charge states in Isolator would be changed. By arranging the charged and uncharged positions accordingly (Data locations) in the insulator layer can therefore store data in binary form in this "capacitor" will. Since the area of the charged places or the uncharged places is of the order of magnitude proportional to the cross-sectional area of the electron beam that is used to make certain Such a storage element has a very high capacity to charge or not to charge places in the insulator layers large storage capacity in terms of the ability to hold a lot of data with extremely small space requirements. When scanning or reading out the capacitor-like storage element, a deflectable electron beam can be used to query the various points, as it were, whether at the respective Make a charge or not. The electron beam is directed to the same point at which Charges were previously stored or deleted in the isolator, with a negative voltage at the same time or a potential of zero value is applied for reading. When the electron beam hits a charged point, it reaches a space charge area in the semiconductor, which is caused by the charge stored in the insulator in the semiconductor is induced, with the beam then electron-hole pairs generated by the electrical ίο Field to be separated. If the semiconductor is a p-semiconductor creates the presence of an electric charge in the insulator layer at the corresponding location a significant depletion in the semiconductor layer at the interface between insulator and semiconductor. Electron-hole carrier are generated by the electron beam within this area and in opposite ones Directions out of the depletion zone through the electrical associated with the depletion zone Field and transported away by the applied read voltage, if one is applied; thereby receives a total of an externally measurable current pulse. At those data points where no charge has been stored in the insulator layer, a very small current, induced by the electron beam, is generated, which may be measurable, but is in any case significantly smaller than the current that occurs when reading a charged data point
Basically, it is noticeable in the known teaching that the storage density is relatively low, since the known data locations of the data memory require a center-to-center distance of at least 200 μ between the neighboring data locations that indicate a binary number based on the respective status. The present invention is therefore based on the object of the aforementioned method in such a way to improve or further develop in such a way that the center-to-center distance between the data points is significantly smaller can make, whereby with a given total area of the memory, its capacity is essential gets bigger. This object is achieved according to the invention by the method characterized in claim 1 Refinements of the method as well as a data memory for carrying out the method are in the Subclaims indicated. If the data storage device (MOS capacitor) comprises a p-type semiconductor, then means are used to initially charge the surface of the insulator uniformly with positive charges by irradiating the insulator with an electron beam while simultaneously applying a positive gradient of the electric charge Field on the capacitor, or better in the capacitor, is maintained. In those places where binary data is in a form, e.g. B. are to be stored in the form of a binary one, the positive electrical lines are retained. In those places or places that the other binary number, z. B. should store or represent the zero here, the charges are removed within an area of diameter D , which surrounds the respective point for the binary zero. D is equal to or greater than the electron diffusion path length in the semiconductor. In order to remove the charge, ie to form the positions representing the zeros, the corresponding positions are irradiated with an electron beam of diameter d, where d <D , with the application of a negative field gradient across the capacitor. the