DE2339741A1 - Anordnung zur bildung einer relativen adresse fuer einen speicher - Google Patents

Anordnung zur bildung einer relativen adresse fuer einen speicher

Info

Publication number
DE2339741A1
DE2339741A1 DE19732339741 DE2339741A DE2339741A1 DE 2339741 A1 DE2339741 A1 DE 2339741A1 DE 19732339741 DE19732339741 DE 19732339741 DE 2339741 A DE2339741 A DE 2339741A DE 2339741 A1 DE2339741 A1 DE 2339741A1
Authority
DE
Germany
Prior art keywords
address
devices
addresses
signal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19732339741
Other languages
German (de)
English (en)
Inventor
James L Brown
Richard P Wilder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of DE2339741A1 publication Critical patent/DE2339741A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE19732339741 1972-08-24 1973-08-06 Anordnung zur bildung einer relativen adresse fuer einen speicher Ceased DE2339741A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00283617A US3800286A (en) 1972-08-24 1972-08-24 Address development technique utilizing a content addressable memory

Publications (1)

Publication Number Publication Date
DE2339741A1 true DE2339741A1 (de) 1974-03-07

Family

ID=23086856

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732339741 Ceased DE2339741A1 (de) 1972-08-24 1973-08-06 Anordnung zur bildung einer relativen adresse fuer einen speicher

Country Status (9)

Country Link
US (1) US3800286A (enExample)
JP (1) JPS4960640A (enExample)
AU (1) AU476122B2 (enExample)
CA (1) CA987408A (enExample)
DE (1) DE2339741A1 (enExample)
FR (1) FR2197484A5 (enExample)
GB (1) GB1428503A (enExample)
IT (1) IT990273B (enExample)
NL (1) NL7311553A (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR122199A (enExample) * 1973-12-17
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
JPS5172203A (en) * 1974-12-20 1976-06-22 Nippon Shisutemu Kogyo Kk Deetadenso niokeru sochishogaikenshutsuhoshiki
US4096568A (en) * 1976-09-24 1978-06-20 Sperry Rand Corporation Virtual address translator
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4058851A (en) * 1976-10-18 1977-11-15 Sperry Rand Corporation Conditional bypass of error correction for dual memory access time selection
US4366551A (en) * 1977-06-24 1982-12-28 Holtz Klaus E Associative memory search system
CH631951A5 (de) * 1978-08-23 1982-09-15 Bbc Brown Boveri & Cie Vorrichtung zur aufbereitung von verunreinigtem wasser und verfahren zum betrieb einer derartigen vorrichtung.
US4280177A (en) * 1979-06-29 1981-07-21 International Business Machines Corporation Implicit address structure and method for accessing an associative memory device
DE3107632A1 (de) * 1981-02-27 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Verfahren und schaltungsanordnung zur adressierung von adressumsetzungsspeichern
US4426682A (en) 1981-05-22 1984-01-17 Harris Corporation Fast cache flush mechanism
US4538241A (en) * 1983-07-14 1985-08-27 Burroughs Corporation Address translation buffer
US4680760A (en) * 1985-08-05 1987-07-14 Motorola, Inc. Accelerated test apparatus and support logic for a content addressable memory
JPH0614324B2 (ja) * 1986-05-02 1994-02-23 エムアイピ−エス コンピユ−タ− システムズ、インコ−ポレイテイド コンピユ−タシステム
US5237671A (en) * 1986-05-02 1993-08-17 Silicon Graphics, Inc. Translation lookaside buffer shutdown scheme
US4813002A (en) * 1986-07-21 1989-03-14 Honeywell Bull Inc. High speed high density dynamic address translator
US5053951A (en) * 1986-12-23 1991-10-01 Bull Hn Information Systems Inc. Segment descriptor unit for performing static and dynamic address translation operations
US5201040A (en) * 1987-06-22 1993-04-06 Hitachi, Ltd. Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor
US4959836A (en) * 1987-12-09 1990-09-25 Siemens Transmission Systems, Inc. Register robustness improvement circuit and method
US4870400A (en) * 1988-01-26 1989-09-26 Yale Security Inc. Electronic door lock key re-sequencing function
DE69031324T2 (de) * 1989-05-31 1998-01-02 Sgs Thomson Microelectronics Inhaltsadressierbarer Speicher
US5107501A (en) * 1990-04-02 1992-04-21 At&T Bell Laboratories Built-in self-test technique for content-addressable memories
GB2260629B (en) * 1991-10-16 1995-07-26 Intel Corp A segment descriptor cache for a microprocessor
US5454094A (en) * 1993-06-24 1995-09-26 Hal Computer Systems, Inc. Method and apparatus for detecting multiple matches in a content addressable memory
US5680566A (en) * 1995-03-03 1997-10-21 Hal Computer Systems, Inc. Lookaside buffer for inputting multiple address translations in a computer system
US6199140B1 (en) 1997-10-30 2001-03-06 Netlogic Microsystems, Inc. Multiport content addressable memory device and timing signals
AU3864499A (en) * 1998-05-11 1999-11-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
JP3719897B2 (ja) * 2000-02-29 2005-11-24 富士通株式会社 データ転送装置、データ転送方法及び記録媒体
US9954557B2 (en) * 2014-04-30 2018-04-24 Microsoft Technology Licensing, Llc Variable width error correction

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3241123A (en) * 1961-07-25 1966-03-15 Gen Electric Data addressed memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387272A (en) * 1964-12-23 1968-06-04 Ibm Content addressable memory system using address transformation circuits
US3508220A (en) * 1967-07-31 1970-04-21 Burroughs Corp Fast access content-organized destructive readout memory
GB1218406A (en) * 1968-07-04 1971-01-06 Ibm An electronic data processing system
NL6815506A (enExample) * 1968-10-31 1970-05-04
GB1266579A (enExample) * 1969-08-26 1972-03-15
GB1229717A (enExample) * 1969-11-27 1971-04-28
US3685020A (en) * 1970-05-25 1972-08-15 Cogar Corp Compound and multilevel memories
US3662348A (en) * 1970-06-30 1972-05-09 Ibm Message assembly and response system
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US3701984A (en) * 1971-03-05 1972-10-31 Rca Corp Memory subsystem array

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3241123A (en) * 1961-07-25 1966-03-15 Gen Electric Data addressed memory

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DE-Z.: "Elektronik Informationen", H. 10, 1970, Rückseite des Titelblattes *
DE-Z.: Zeitschrift für Schwingungs- u. Schwach- stromtechnik, März 1966, S. 69-82 *
US-AFIPS Proceedings of the Spring Joint Computer Conference 1966, S. 65-69 *

Also Published As

Publication number Publication date
JPS4960640A (enExample) 1974-06-12
CA987408A (en) 1976-04-13
GB1428503A (en) 1976-03-17
AU476122B2 (en) 1976-09-09
NL7311553A (enExample) 1974-02-26
IT990273B (it) 1975-06-20
US3800286A (en) 1974-03-26
AU5723173A (en) 1975-01-09
FR2197484A5 (enExample) 1974-03-22

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Legal Events

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OD Request for examination
8131 Rejection