DE2330412A1 - CIRCUIT ARRANGEMENT FOR POSITIONING A PRESSURE UNIT - Google Patents

Description

January 10, 1973

El 159-üchl / Kß.

Applicant 2330412

YIiB Kombinat ZENTRONIK, '

523 Sömmerda, Weißenseer Str. 52 German Democratic Republic

Circuit arrangement for positioning a printing unit

The invention relates to a circuit arrangement for positioning of a printing unit, in particular of a serial printing unit, with each printing position having an address in binary, is preferably assigned a dual sound.

Known circuits for positioning work on the principle of constant comparison between programmed Address and the current position of the moving assembly by adding either a small or a large or generate an equality signal, after which the corresponding Movement phase is carried out. The stop signal is only supplied by such a circuit, however, if the addresses already match.

In contrast, for rapidly moving units that require a braking distance, the address must be corrected before each transport necessary. Bine designed according to this principle Device for tabulating a type carrier slide , for a type roller according to DT-AS 1 294 713 has to for this purpose an arrangement consisting of a flag, an address calculator, an address comparison arrangement and

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a tabulation logic, the Lerker has the task of the address offered to the address bucket next to the print button 11 enzah.1 of the type roller also to correct the braking distance. However, this correction can only take place after the tendency in the address comparison arrangement, ie. the Tabulation direction has been determined and reported to the tabulation logic for storage. In addition to a comparatively high technical complexity, this circuit also has the disadvantage that it does not have a fast or slow transport able to effect depending on the distance between the moment and the target position.

The object of the invention is to provide a circuit arrangement for the automatic positioning of a printing unit, in particular a line printing unit, with each Print position is assigned an address in binary, preferably dual form, to indicate that without the need for a Address correction in addition to determining the direction of movement, taking into account the distance between and target position over a fast (tabulation) or slow (step) transport decides the braking process triggers and emits an equality signal if the target and instantaneous positions match ^

The inventive solution to the problem is that the address lines of the setpoint address and the current address of the printing unit with m computing circuits of a dual working

■ -3-

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tend arithmetic unit are connected, in which the transfer output of the m-th computing circuit to the first computing circuit is performed and at the same time forms the first input of an evaluation circuit that a second input of the evaluation switching through · logical linking of the result switching— ■ gears of a group of η arithmetic circuits is given that a third and fourth input of the evaluation circuit through the outputs of a first conjunction and a disjunction, which each 'combine all other m-n result outputs both conjunctive and disjunctive is given and that the evaluation circuit outputs for forward and backward tabulation, for stepwise forward and backward transport and stop if the addresses are the same.

It is also considered expedient that within the evaluation circuit the output of a logic circuit to which the output of the disjunction and the negated output of the first conjunction are fed, cLqu input of a memory circuit for tabulation and the negated output of the logic circuit, with the output of the first stage of the Linked memory circuit, form the input of a memory circuit for step-by-step transport, that the output of the stage of the memory circuit emitting the tabulation signal and the negated output of the logic circuit are connected to a conjunction that emits a signal for the termination of the tabulation and that all result outputs of the arithmetic unit finally lead a conjunction at the output of which the address equality signal occurs.

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Advantageous features of the invention are also therein sees that in the evaluation circuit by means of logical Scolding

a) the output of the first conjunction with the negated output of a conjunction linking η result outputs to the exit for step-by-step return transport,

b) the output of the first conjunction and the carry-over output of the m-th calculation to the output for reverse tabulation,

c) the carry output with the negated output of the disjunction to the exit for step-by-step forward transport and

d) the carry output is linked to the output of the disjunction to the output for forward tabulation «

Finally, there is also an embodiment according to the invention in that when using subtractors as arithmetic circuits in addition to m-n disjunctively linked result outputs, η result outputs are also disjunctively linked, the outputs of which the fourth and second input of the evaluation circuit and the output by conjunctive linkage for the address match signal that form the conjunctive link of the fourth and negated second input the exit for stepwise forward transport, the conjunctive connection of the exit of the first conjunction with the Carry output the output for step-by-step return transport, the conjunctive link of the negated output of the first Conjunction. With the carry output the output for return

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downward tabulation and the disjunctive combination of the carry output and the fourth input of the evaluation

tion results in the output for goalkeeper tabulation.

Figures 1 to 3 show embodiments of the invention, namely

Pig. 1: a circuit with an arithmetic unit consisting of adders and storage of the iCransport type in an evaluation circuit}

Fig. 2: a circuit with adders, but without storage of the fränsportartj

FIG. 3 shows an analog circuit to FIG. 2 with subtracters as computing circuits.

In Fig. 1, an arithmetic unit RW, consisting of Computational attitudes RI to Rm are shown. Any arithmetic - in the exemplary embodiment a Yolladder - is on the input side with one digit of the momentary address M- (III- to Ate), the target address S (S1 to Sm) and the carry output Ü1 to Üm-1 of the previous one, in the case of R1 with the carry output Connected to the highest point · Bine of the bdiden Addresses are offered in a complemented form. Y / while the result outputs A1, A2 of the computing circuits RI, R2 are linked by means of a second conjunction K2, all further result outputs A3 to Am are respectively present a first conjunction K1 as well as a disjunction D1. The outputs of the first and second conjunction K1, K2, the disjunction DI and the carry output to form the

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Inputs E3 »E2, Ü4- and E1 of an evaluation circuit V · This contains a first memory circuit SKI for tabulations and a second memory circuit SK2 for step-by-step transport. The input of the storage circuit SK1 consisting of NOR elements NOR3 »NOR4 is formed by the output of a conjunction K4 into which the outputs of disjunction DI and conjunction K1, in the latter case the signal conducted via an inverter N1, open. The output of the conjunction K4 is also connected via an inverter N2 together with the N0R2 output of the storage circuit SK1 to a conjunction K5 which is connected upstream of the storage circuit SK2, which also consists of NOR elements NOR5, N0R6. The output V2 of the storage circuit SK1 and the output of the inverter N2 are switched to a conjunction K6 which emits a tabulation stop signal at the output V3 when the tabulation is ended and the braking process begins. The Speicherkreisas SK2 appears at the output V4 only one 'step signal when the beginning of the positioning, the distance between instantaneous and desired position s is equal to or less & \ three steps. By linking the outputs E3 | E2 of the first and second conjunction K1, K2 by means of a conjunction K3 produces an address match signal at the output V5 thereof, which is sent to N0R4 and N0R6 to delete the memory circuits SK1 and SK2. The carry output Um the highest point forms - unaffected - the output V1 of the evaluation circuit V. The output signal from Y1 indicates the direction of tabulation or step-by-step transport.

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In Pig. 2 arithmetic unit RW, the first link of the ER ^v gebnisausgänge A1 to Am and the recovery of the address parity signal are completely · identical with respect to FIG. 1. The most significant difference between the two circuits is that the Riehtungssignal (carry output order) does not appear separately , but together with the type of movement forms a combined, single output signal · For this purpose are linked

a) through a conjunction K7 (output Wl) the output of the conjunction K1 with the negated output of the conjunction K2,

b) through a NOR element NOR7 (output V21) the output of the Conjunction K1 and the carryover output Um,

c) by a conjunction K8 (output VA-2) the carry output To deal with the negated output of the disjunction DI and

d) through a conjunction K9 (output V22) the output of DI with the carry output Um.

The output signals at the logic circuits mean

a) Output Wl: "transport step by step, backwards"

b) Output V21: "Tabulation backwards"

c) Output W2i "Transpor-tf step by step, forwards"

d) Output V22i "Tabulation forward"

While in the exemplary embodiments described above, one of the two addresses is fed to the arithmetic unit RW as a component

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is the provision of both the instantaneous takes place as well as the target address in the embodiment of FIG. 3 ^e ~ d weils in the same, that is, either in a complemented or un--complemented form. In this case, the arithmetic unit RW consists of subtraction elements as arithmetic circuits R1 to Rm; the processing of the transfers takes place analogously to the variant with adders. The result outputs A3 to Am lead in the same way to conjunction K1 and, for the sake of simplicity, to a NOR circuit NOR1, since the result outputs A1 and A2 are also linked by means of a JTOR hold N0R2. The N0R2 output, the outputs of the conjunction K1 and the NOR circuit N0R1 as well as the carry output Um also form the inputs E2, E3, E4- and El of the evaluation circuit V, in which these signals are linked as follows:

a) the outputs of N0R1 and by means of a conjunction K10 NOR2 to output Vfj for address equality;

b) by means of a conjunction K11, the outcome of conjunction K1 with the transfer output Um to the output Wl for "Transport step by step, backwards ",

c) by means of a conjunction K12 the carry output Um with ' the negated output of conjunction KI to output V21 for "tabulation backwards",

d) by means of a conjunction Ki3 the outcome of N0R1 with the negated output of N0R2 to output V4-2 for "Transport step by step, forward "and

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e). through an NDR circuit HQRS the output of HDSI and the carry output Öm to output Y22 for "'fabulation forward**.

The mode of operation of the circuit described is intended below using the example from J? ig. 1 explained will.

When the operating voltage is switched on, the Löschleifcungeii i * ö applied to ^ "- potential and thus possibly still existing settings of the Speieberkkreis SKI» 3K2 deleted.

With the provision of the current address M (H, .. .Mm) and target address S (SI, .. .Sm) at a.en ! Arithmetic unit inputs «r— the additive calculation follows. · Since one of the two addresses is available in a complemented form, , the overall result M is "L **, if the addresses match" in this case, the conjunctions K1, 12 and K3 lead ^W L ^M -Aösgangssigaale, of which that of the conjunction K3 is the address equality signal ^ Adr.-Equal ". Because this equality signal is also applied to the NDR elements UORH- and N0R6, it prevents the storage circuit «SKI and SK2 and there is no movement of the printing unit taking place». If the current and target address differ by one, two or three positions, lead - depending on o% di ©. Setpoint address larger or smaller than the momentary address ©, the outputs from R3 to Sm are all equal to "L * or * ^) ⁿ , see above

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that the output signals iron K1 and DI are always the same. ■ Bamit is the output signal of K4 in any case "0". Above N2, NOR3 and E5, however, the storage circuit SZ2 is self-holding, since the output signal from K3 is also "0".

During the subsequent step-by-step movement, the direction of which is determined by Um, change with each step also the current addresses until they match. At this point in time, the address match signal occurs "Adr.-GIeich" and removes the self-retention of the storage circuit SK2 on; the desired print position has been reached.

If the difference between the current and target address is greater than three positions, at least one of the result outputs A3 to Am has "0" potential but also at least one output ** L "potential, if several result outputs A3 to Am show" 0 **, At the output of the conjunction K1 there is therefore ' ¹ O **, at the output of the disjunction D1 “L”, so that the conjunction K4 ^{emits an “L n} signal, which now sets the storage circuit SKI. The printing unit begins with the rapid tabulation, whose direction is again indicated by Um. The tabulation continues until the current and target address differ by only three positions. The "L" signal at K4- disappears and both inputs of the conjunction K6 carry "L", so that the tabulation stop signal is generated at the output, ie the tabulation drive is switched off and the braking process is initiated instead, with the remaining three positions

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until ziu? If the addresses match. At the bath of the braking process the signal "Adr..Equal" occurs again and the storage circuits SKI ₁ SK2 are reset. The circuit is now ready for a new positioning process.

The circuit arrangements according to FIGS. 2 and 3 can in principle. be applied to the same extent. However, there are no discontinuities in the transition from one instantaneous address to the other To keep ineffective, it is advisable to use the outputs in the vie ise memory circuits already described in connection with FIG subordinate β

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Claims (3)

Claims μ ") Circuit arrangement for automatic positioning a printing unit, in particular a serial printing unit, with each .print position an address in binary, is preferably assigned to dual fora, characterized in that that the address lines (31 ... Sei; MI ... EIm) of target address and. Momentaiiaäresse of the printing unit with m arithmetic attitudes (Ki ... Rm) of a dual working Arithmetic unit are connected, in which the carry output (Um) of the m-th arithmetic circuit (Ra) to the first Series circuit (R1) is performed and at the same time the first input (E1) of an evaluation circuit (V) forms that a second input (E2) of the evaluation circuit through logic Link (K2, 1T0R2) of the result outputs (A1, Δ2) a group of η arithmetic circuits is given that a third and fourth input (E3, Ξ4) of the evaluation circuit (V) through the outputs of a first conjunction (K1) and a disjunction (D1, NOR1), each of which remaining m-n result outputs (A3 · .. Am) both conjunctive as well as disjunctive, is given and that the evaluation circuit (V) outputs (V1 ... V5) for and backward tabulation, for step-by-step forward and backward transport and stopping if the addresses are the same. 2. Circuit arrangement according to claim 1, characterized in that within the Äuswert circuit (V) the output -13-409815 / 0990 a logic circuit U ^ O, which the output (E4) of disjunction (Di) and the negated output (.S3) of the first Conjunction (Ki) are fed to the input of a storage circuit (SKi) for 'tabulation and the negated output the logic circuit (K4), linked with the output of the first stage of the storage circuit (SKi), the 3input a storage circuit (3K2) for step-by-step '.Transport form that the output (V2) of the! Tabulation ons signal emitting level of the Speieherkreis (SKi) and the negated Output of the logic circuit (K4) are switched to a conjunction (K6), which sends a signal (V3) for termination the tabulation and that all result outputs (Ai ··· Ahl) of the arithmetic unit finally ah a conjunction (K3) at whose output (V5) the address match signal occurs » 3. Circuit arrangement according to claim i, characterized in that in the evaluation circuit (V) by means of logic Circuits (K ?, NOR ?, KB, K9) a) the output (B3) of the first conjunction (Ki) with the negated output (E2) of a conjunction (K2) linking η result outputs (Ai, A2) to output (V4i) for. gradual return transport, b) the outcome of the first conjunction (Ki) and the transfer outcome (Ei) the m-th arithmetic circuit for the. Output (V2i). for backward tabulation, 98157 c) the carry output (E1) with the negated output (E4) of the disjunction (D1) to the output (742) for stepwise, forward transport and d) the transfer output (E1) is linked with the output (E4-) of the disjunction (D1) to output (722) for forward tabulation. . _v 4-, circuit arrangement according to claim 1, wherein the arithmetic circuits are designed as subtracting elements, characterized in that in addition to generally n disjunctive (MOR 1) linked result outputs (A3 .. · Am) also η result outputs (A1; A2) disjunctive ( NOR 2) are linked, the outputs of which form the fourth and second input (E4-, E2) of the evaluation circuit (7) and by conjunctive link (K10) the output (V5) for the address equality signal that the conjunctive link (K13) of the fourth (EA-) and negated second (E2) input the output (V42) for stepwise forward transport, the conjunctive link (K11) of the output (E3) d- ^e ^ first conjunction (K1) with the carry output (E1) the output ( WI) for step-by-step return transport, the conjunctive link (K12) of the negated output (E3) of the first conjunction (K1) with the carry output (El) the output (V21) for backward tabulation and the disjunctive link (N0R8) of the carry output (E 1) and the fourth input (Ξ4) of the evaluation circuit results in the output (V22) for forward tabulation » A09815 / 0990