DE2327560A1 - METHOD FOR DIGITAL EXTRAPOLATION OF THE CENTER OF PULSES OF DIFFERENT AMPLITUDE AND EDGE PITCH - Google Patents

Description

Method for digitally extrapolating the center of different pulses Amplitude and edge steepness When transmitting and regenerating binary signals in serial or parallel channel coding (e.g. in the multi-level signal form) carry out the query for the decoding at the exact point in time of the pulse amplitude maximum, if the signal-to-noise ratio of the transmission chain is to be used optimally.

In the event of deformation of the transmitted binary signals due to attenuation and Runtime instability of the transmission elements is currently known decoding process mostly only the leading edge of the so-called leading impulses for the approximate time determination the contribution pulse amplitude is used in such a way that one or more of the statements Amplitude level comparators are compared with each other via a logic and only the Comparator statement for the largest recorded pulse amplitude, if necessary under # Include a fixed delay is declared as the "maximum" amplitude time value.

L8 is also known, e.g. if it is known or possibly through additional Filter arrangements of reduced slope of the falling pulse edge below Including the variable maximum amplitude detected by a sample-and-hold circuit the master pulse with a monoflop controlled by this in its turnaround time value an approximation of the time of the then delayed by a constant amount To obtain the maximum amplitude value (technical report of the research institute of PTZ A 44 TBr 29 from June 1971, p. 9 above).

Both methods record the actual maximum pulse moment value only approximate and cause time errors with certain signal distortions for decoding (phase jitter). In addition, they are due to the necessary, possibly. variable time constant members are difficult to use as integrated microcircuits realize. Hirmi comes that she, like all analog processes, is sensitive and are critical in their attitude.

The method according to the invention sets itself the task of the point in time the transmitted maximum amplitude more precisely and without complex controlled time constants to be recorded by fully integrable switching means from the point in time of the pulse center.

The method according to the invention makes the methods of digital Use counting technology.

The use of digital counters to distinguish and sort out of impulses is not in itself new.

Thus, in a method for monitoring the pulse-lawsen ratio a square wave for the duration of the first drawing step forward and counting down during the duration of the second character step, the binary counter is used and the difference between the two counter readings is saved and displayed (DOS 2 036 631).

Next is a device for eliminating input signals that do not meet a given time condition, known that works with 3 binary counters, of which the first on the one from the leading flank and the second on the one from the Responds to the trailing edge of the pulses obtained from the Singangssignals. The third counter speaks also on the one obtained from the leading edge, but through a delay line delayed pulses. A comparison device only supplies an output signal if the content of two counters is the same but different from the remaining counter is (DOS 2 209 198).

The special object of the invention occurs with both known methods not on, even if here the results of binary counting processes are compared and off Switching criteria can be derived from the comparison.

In contrast, the above-described object of the invention Method in the manner shown in claim 1 money.

A circuit arrangement for carrying out the method according to the The invention is described in claim 2.

The method according to the invention is described below with reference to two figures explained in more detail. FIG. 1 shows a timing diagram of the pulse to be examined FIG. 2 shows a block diagram of a circuit arrangement for carrying out the invention Procedure.

In the timing diagram of FIG. 1, the amplitude of the can be found at the top Pulse to be examined, which in principle could have any slope and can also be asymmetrical to the pulse center. Below the amplitude curve the square-wave voltage is drawn in after a certain value has been exceeded Threshold value of the pulse amplitude at the output of the amplitude discriminator results. Below that is the actual time diagram with the time t as the abscissa and the analogously represented value of the binary counter reading N achieved in each case as Ordinate.

As can be seen from FIG. 1, when the amplitude threshold value is reached a help counter started with the clock T1 and counts until the value falls below the Threshold values. The main counter then starts with a clock cycle that is twice as fast T2 until the respective counter reading of the help counter is reached.

The time required for this is exactly half the time in which the Pulse amplitude was above the threshold. Then the main counter counts with the simple one Clock T1 continues until a time value K that can be preset as a binary code word is reached. This time value is then exactly around the presettable time period K. from the middle of the optimally recorded shortest pulse width and thus with high probability also the maximum pulse height is constantly delayed.

The pulse to be examined is shown in the block diagram of FIG first fed to an amplitude discriminator 1.

The output of the amplitude discriminator 1 leads once to one Input flip-flop 5 and on the other to an AND gate 3, whose other input is on the simple clock T1 generated by the generator 2 lies. When the threshold value is reached, See Figure 1, the clock T1 reaches the digital counter 4 and via the AND gate 3 is made by the same expensive logic after falling below the threshold value from input flip-flop 5 and AND gate 3, switched off again. at the same time becomes over the AND gate 7 and the OR gate 8 of the frequency converter 6 of the clock T1 doubled clock T2 applied to the input of the main counter 9. Twice that fast clock T2 is on the main counter until that between the auxiliary counter 4 and the main counter 9 lying coincidence gate 10 indicates the same count. Then the Singangs-Blip-Blop 5 and the Tom 7 and 8 become the fast clock T2 off and for this the normal clock T1 via a further flip-flop 11 and the gate 12 switched on, the main counter 9 continues to count with this normal clock Ta as long as until a further coincidence gate 13 achieves one in a particular one Memory 14 entered counter was displayed and via an Auagangs blip-flop 15 a constant time period K to the respective extrapolated pulse center (see Figure 1) delayed pulse at output 16 is emitted.

For simple applications of the method according to the invention, in particular In the case of pulse shapes symmetrical to the pulse center, an ordinary gate can also be used can be used as a pulse amplitude discriminator.

It is also possible, instead of a basic clock to be doubled assume a basic clock rate to be halved by frequency division.

Claims (2)

Claims 1. Method for digitally extrapolating the center of pulses of different types Amplitude and edge steepness, especially of the leading pulses from channel-coded Multistage signals, that is, that the impulses in the expected time range are first fed to an amplitude discriminator (1) and by means of a binary auxiliary counter (4) with the clock T1, the time is counted and the counter reading reached is stored digitally, in which its amplitude one The threshold value given by the gate exceeds that when the threshold value is undershot the auxiliary counter stopped and a binary main counter (9) with a double fast clock T2 = 2 ~ T1 is started, which goes up to the counter reading of the auxiliary counter (4) counts, and then continues to count with the simple clock T1 until an as binary code word presettable time value K is reached, around which the point in time is then reached the pulse center determined in this way is exactly delayed. 2. Johaltungsanordnung for performing the method according to claim 1, characterized in that depending on the switching position of the amplitude discriminator (1) downstream input flipe-flop (5) and the gates controlled by it (3, 7) the clock T1 generated by a pulse generator (2) directly on the auxiliary counter (4), or after doubling the frequency on the main counter (9) is switched that between Help counter (4) and main counter (9) Coincidence Gate (10) is switched, which with the same count of both counters via another flip-flop (11) the clock T1 via an AND gate connected in parallel to the frequency doubler (6) (12) and an OD £ # gate (8) can get directly to the main counter (9) that between Main counter (9) and a presettable memory (14) a further coincidence gate (13) - is switched, this when the binary counter status of the main counter matches (9) with the code word of the memory (14) via an output flip-flop (15) the extrapolated Output signal (16) triggers (Fig. 2).