DE2320422C2 - Device for error detection - Google Patents

Description

S (X) = (I + xf fix) as

According to Peterson, a cyclic code is used as a sub-group

realized, where t (x) and f (x) represent polynomials to consider pe out of 2 " possible sequences of η bits. In which are relatively prime to one another, an odd anpolynomial notation means s" e have a minority of terms and where t (x) m \ nde- group of all possible polynomials of degree <n— \, at least of degree isL 40, ie:

3. Device according to claim 2, characterized

by an encoder according to the generator poly ao + ai x + ai x ² + ... + a "- \ x" - ¹ .

A cyclic code can be generated by means of a generator po-

g (x) - (l + xf {\ + x + x *), 45 lynomial g (x) can be defined. It consists of such

Multiples of g (x) that are of degree <n- 1. It leaves

as well as easily showing by a mixer according to the mixed poly, that there are exactly 2 "- ' polynomials which nom are both multiples of g (x) and a degree

have <n- 1. Consequently, before the transfer

S (x) = (1 + xf (1 + x + x ³ ). 50 encodes a sequence of digits in such a way that it is a multiple of the

Represents generator polynomial

Consider a cyclic code as an example

/ 7 = 7 bit positions with a generator polynomial

The invention relates to a device for recognizing 55 g (x) = 1 +
tion of odd-numbered error quantities as well as of

According to ⁴ = 2 ³ = 8 polynomials, the data transmission equipment to the preamble multiples of g (x) represent Thus, each Fehlervergriff is - burst errors up to length of b bits in There are in this case 2 "- ^r = 2. ⁷ Claims 1 and 2. Division of the form x> E (x) recognizable if / any

Initially, some aspects of the cyclical 60 positive integer should be briefly represented and E (x) not replaced by g (x)

Coding of digital data, the mode of action is so divisible. The evidence for this fact is as above

rather cyclical codes as well as the effect of the literature cited by Peterson.

fung used special mixing stages (scramblers) men.
be considered on the error behavior. In this

Relation to the basics on the 65 cyclic codes and error properties
the following literature can be referenced: WW Peterson,

"Cyclic Codes for Error Detection," W. W. Peterson Two classes of errors are of interest. There are

»Verifiable and Correctable Codes«, Oldenburg Verlag, these odd numbers of error quantities and bundles

3 4

failure. The detection of error distributions with unintentionally alternating binary signals for consecutive numbers of errors can be achieved by simple parity checkers, with the following signals being achieved with a mixed polynomial. The generator polynomial for such S (x) = 1 + x two at a time genome code is g (x) = 1 + x. This is true because of the facts. For an input data sequence
before that all polynomials with an even number of 5

Divisions are divisible by 1 + x. For example, this is χ · ~ ² + χ · - ^χ + λ »" + A ^{1 + 1}
Polynomial 1 + x + J ^ + x ^ without remainder, divisible by 1 + j.

A bundle error of length b is defined as one that would be the output sequence χ '-' + * '+ ¹ . It should be error distribution, which will be taken over a maximum of b successive that a sequence of identical digits, the following bit positions extends Such a burst error 10 that is 1111, can be in the NRZI mixer correctly to 1010 (1-Jx ²⁾ by the polynomial x > ■ B (x) is represented, and that the sequence 0010 (x ² ) on which B (x) a polynomial of at most degree b - \ receiving side arrives stage multiply the received sequence (x ² ) with the mixed polynomial ö <3 1 + χ , ie

x> B (x) = χ ¹ + χ * + χ *. (1 + X) (X ² ) = x ² + x ⁱ .

On the other hand, a bundle fault can be represented with fc <5. This means that the single fault in an adjacent one can be represented as X ¹ B (X) = 1 + x *. th double here is converted, which is no longer

20 is recognizable via the parity With armored words, for

Bundle Error Protection Characteristics of a channel error e (x) appears as an error

Generator polynomial E (x) = S (x) e (x). In the example above with e (x) = x ² and

S (x) = 1 + is given by E (x) = x ² + x ³ . Originally

In order to detect bundle errors with a maximum length b , the cyclic codes contained the factor \ - + 'x on the basis of the above, 25 detection of all individual errors and all odd-numbered generator polynomials should have the following properties for error sets. If, however, one has on the receiver side: Demixing stages must be provided, these errors will also appear

multiplied by the mixed polynomial S (x) and can therefore

(1) g (x) is at least of degree b; half can no longer be discovered.

(2) g (x) has a constant other than zero. It is an object of the invention to add a device. with which errors are transmitted in mixed form.

; ί digital data sequences can be recognized, where-

To ensure that all errors of form E (x) would - x> B (x), recognized for these errors of odd error amounts as long as E (x) is not divisible by g (x) in buying and / or burst errors of length can b made , considering condition (2) it can be stated that g (x) 35. The solution to this problem is not contained in claims 1 with a factor of the form x> For example, and 2 and is partly based on the transfer g (x) = 1 + x it can be shown that x * / (x + 1) always in the visual observation that neighboring double errors result in a remainder So that E (x) is divisible by g (x) in a digital sequence, which must also be in polynomial form B (x) thus be divisible. Given the above is not divisible by 1 + x ^2,
gen condition (1) comprises g (x) has a higher degree than 40 According to one embodiment, the inventions B (x), so that B (x) thus is not divisible in a dung in a digital data transmission system vertypischen case with g ( x) = 1 + λ ⁴ were all bundle errors in which a cyclic encoder for converters of length 6 <4 and with g (x) = 1 + x + x ⁱ⁵ all bundling of the digital data sequences by dividing these del errors of the Length b < 15 can be recognized. Data sequences by a selected polynomial g (x)

45 is seen and in which a mixing stage for the other

Mixer and its influence on errors Division of the coded data sequences by the mixing point

lynomial S (x) = 1 + x for a polynomial g (x) in the form

Up to now it has been found that (1+ x ² ) t (x) is provided by suitable. For the general case of the form of a generator polynomial, odd Fchleran error detection of odd numbers of errors applies
pay as well as bundle errors on the recipient side

can be known. Now, however, in excess of s (x) = (1 + x) "f (x) and

p load systems additional mixing stages are used, g (x) = (\ + x) ^m + \ t (x),

|| whereby the mixing creates a certain randomness

φ is performed in order to reduce the effects of any symbol-in where f (x) and t (x) each have an odd term interference. Usually a sol-number is included.

before mixing stage on the transmission side between the code If in addition to the odd-numbered error detection

i'er and the transmission channel switched on, while bundle errors with a length of < b bit positions in the corresponding unmixing stage the received digital sequences are to be recognized before they are forwarded to the decoder, the following applies in addition to the aforementioned condition 60 conditions that f (x) and t (x) are relatively prime to one another

This mixing or scrambling process can be required and t (x) is at least of the degree ά
Special form of coding are considered and further features of the invention are iii the sub-meaning that thereby the data stream is also characterized by claims. The invention is divided into the p a polynomial. In a corresponding manner, the following description:? ^ With the aid of the drawing is explained in more detail by the segregation process on the recipient message,
te the received data flow with a polynomial must show:

multiplied F i g. 1 a digital data transmission system with

A frequently used, so-called NRZI mixer, mixer circuits in which the invention is implemented,

Fig. 3 and 4 NRZI mixing or unmixing circuits,

F i g. 2 and 5 a coding or decoding circuit for recognizing odd-numbered errors and for generating the polynomial g (x) - 1 + x ² ,

F i g. 6 and 7 an encoding and decoding circuit for the detection of bundle errors and odd numbers Errors as well as for generating the polynomial

(1+ xf f (x) and
(NS()

"4M-0 + X / -0 + X + X ⁴ ) ίο

F i g. 8 is a timing and failure analysis diagram for the system of FIG. 1 with partial circuits according to FIGS. 2 until 5.

In Fig. 1 shows a block diagram of a digital data transmission system. A data source 2 supplies Feiger with digital data to the encoder 1. The encoder performs a conventional division of the sequences by the polynomial g (x) . The data sequences encoded in this way are then again convolutionally divided by the polynomial S (x) in the NRZI mixer 21.Depending on the requirements of the transmission channel 31, digital data sequences encoded in this way are sent to the transmission path either directly or via a suitable modulator (not shown) At the receiver end, the data sequences are then demodulated and passed to an NRZI demixing stage 41. The data are demixed there by conventional multiplication by S (x) and then passed on to a decoder S1

Before describing the FIG. 2 to 7 is passed over, the correctness of the properties of the Generator and mixed polynomials are treated. This should be done in the usual way in this technical field Wise, by setting up various "propositions" and their respective proofs.

Sentence i:

If the mixed polynomial S (x) is the generator polynomial

S (x) - (\ + x *) t (x)

where f (x) has an odd number of terms, g (x) generates a cyclic code that recognizes all odd numbers of channel errors φ) if the mixing and unmixing circuit is present Proof:

φ) should be the polynomial representation of channel errors with an odd number of terms. Conversely, it should again be assumed that

x) φ)

.5 E (x) = S (x) φ) - (1

is divisible by g (x). This can be expressed as follows:

E (x) _ (l + x) ^m f (x) e (x) _m / (X) e (x) g (x) (1 + x) ^{m + i} t (x) (\ + x) i (x) '

It follows from this that if f (x) and e (x) are to be divisible by 1 + x , the following applies in accordance with the proof of sentence 1 for / fr *

f (x) _ {', + x) afc) or
φ) - (I + x) v (x).

Since neither f (x) nor e (x) should have an even number of members, there is a contradiction to the prerequisite. But this shows that φ) is not divisible by g (x) Theorem 3: Is the mixed polynomial

S (x) ™ (l + x} »f (x) and g (x) - (1 + xf K)

\ + x, then allowed

recognize all odd numbers of channel errors, where t (x) em represents any polynomial Proof:

In order to recognize all odd numbers of channel errors φ) , it has to be shown that the polynomial expression for the present error φ) is not divisible by g (x).

E (x) -S (x) e (x) - {\ + x) c (x)

Conversely, assuming that (1 + χ) φ) is divisible by g (x) , it follows that φ) and (ϊ + χ) must be divisible. But then:

φ) = (1 + χ) φ) = φ) + χν (χ).

With this assumption, however, φ) has an even number of channel errors. But this contradicts the assumption that φ) had an odd number of terms. Therefore: eft) is not divisible by g (x). Sentence 2: With

where t (x) is relatively prime with respect to f (x) and represents a polynomial of degree> b , a code for detecting burst errors in the channel of <b bits is obtained. Sentence 4

If one wants to recognize all odd numbers of channel errors as well as bundle errors of length < b , the mixed polynomial must be used

50

55 S (x) - {\ + xp f (x)

and the generator polynomial

g (x) - (\ + xf ^ t (x)

where f (x) and t (x) are relatively prime. Furthermore, f (x) and t (x) must have an odd number of terms, where t (x) is of degree> b

Any even number of errors can be expressed with E (x) = (1 + χ) φ). Since the bundle error length b must be <5 , the polynomial φ) must be of degree <3. It also follows from this that g (x) allows all odd numbers of line faults and all even numbers of trunk faults of length <5 to be recognized F i g. 2 shows an exemplary embodiment for an encoder 1. Each digital data sequence from the data source 2 is fed to the encoder via the line 3. The encoder transmits the data sequence and delivers the test

bits. The check bits are obtained from the separate division of the data sequence using the code polynomial g (x) . For this purpose, the data is fed to the encoder via two paths at the same time. One way consists of the line 3, the switch Tc in the position Tb and the line 8. The other way contains the EXJÜLUSIVE-OR gate 5 and the feedback path-9 via the closed switch 10c in the position 106.

In the context of this exemplary embodiment of the invention, a digital data block with η - / - bits is supplied in each case before the transmission of the r remaining bits. The r check bits are obtained by applying the data sequence to the encoder when the data is transmitted over the line 8. This ensures that the check bits are always available immediately after the last data bit has been sent.

When the data file is present on line 3, switch Tc goes to position Tb and switch 10c to position 106. Each transmitted bit is also applied to EXCLUSIVE-OR gate 5. This EXCLUSIVE-OR element only generates a binary "1" if there is an inequality in terms of its input values. As a result, a binary “1” is only generated if there is a difference between a bit on line 3 and the content of delay element 13. The output signal from 5 is then fed to the delay element 11 via the line 9, whereupon its content is in turn ^{shifted into the delay element V} 3. After the last data bit has been transmitted, switches Tc and 10c respectively go to the other position Ta and 10a. As a result, the feedback path 9 is interrupted and the content of the delay elements is transmitted to the line 8.

In Fig. 5 shows the logical structure of a decoder at the receiver end. The decoder 51 has the task of multiplying the received data and check bits with the generator polynomial g (x). If during the transmission there was a change in an odd number of bit positions, this change will appear in the delay elements 55 and 57 in the form of two binary ones. If no odd numbers of errors have occurred, these two bit positions should each have a binary "0". The data are still stored in a buffer register 493. The decoder checks the data and, if there are no errors, causes the contents of the register 493 to be output to a consumer circuit.

To explain the method of operation of the invention, reference is made to FIG. 8 with reference to a timing and error analysis diagram of the logical output behavior of a digital data system is shown. This data system contains the encoder (FIG. 2), the NRZI mixer (FIG. 3), the NRZI demixer (FIG. 4) and the Decoder (FIG. 5) in the one shown in FIG. 1 overall arrangement shown.

In Fig. 8 the successive bit time intervals 71 to 7 * 12 are shown and identify the respective columns. It should be assumed that during time 71-74 an input signal 1111 having four bit positions and during TT- T10 a further data sequence 1001 are sent to input 3 of the encoder of FIG. 2 is created. The time intervals T5, T6 as well as Γ11 and 7 * 12 are reserved for the transmission of the check bits. For the purposes of this example, it should also be assumed that the initial The content of the delay elements 11 and 13 of the encoder 1 is in each case a binary "0".

On the output line 8 of the encoder, the output signal 1111 appears immediately during the time intervals Ti-T4 and the output signal 1001 occurs during TT-TiO. Furthermore, the check bits output by the EXCLUSIVE-OR element 5 to the output line 8 are "0" and "0" during T5-7 * 6 and "1" and "1" during 7 * 11-712. For the content of the

ίο delay element 27 in the mixer (Fig.3) during times 71 and 77 each assumed a "0". During the time intervals 71 - 76, on The output of the mixer receives the sequence 000010 for a corresponding input signal 111100. In a similar way During 77-712, the output sequence 010000 was generated from the input bit sequence 100111.

The bit sequence mixed in this way is placed on a transmission medium, although it cannot be ruled out that it in regarding some of its symbols by the channel noise at the demixing stage in an impaired manner 41 arrives at the receiving end.

In the receiver there is, inter alia, one shown in FIG. 4 shown demixing stage provided. The operation of the separator also begins at time 71. For the further explanation is the consideration of synchronization and clock problems irrelevant. In terms of Regardless of this point, it should be noted that the invention can be generally applied to various fields regardless. If one pursues by approaching hung the f i g. 4 and 8 the process of conventional multiplication, it results that for an input bit sequence 000010 while 71 - 76 an output signal 111100 appears on the output line 49 (inverter 47). In in the same way is at the output 111111 while 77-712 for a corresponding input signal 000000. The output signal obtained by the demixer 41 is serialized to the one shown in FIG. 5, the decoder 51 shown is supplied via the line 49. The output data of the segregation stage are still in a buffer memory 493 added. When the data is read into the buffer memory, the decoder 51 begins to divide each digit position on the line 49 by the code polynomial g (x). As a result, if the during the time intervals 76 and 712 in the Ver delay elements 55 and 57 stored digits if both are "0", this means that no error has been detected. For the period 71 - 76 is in no error has been detected in the selected exemplary embodiment. Hence the content of the two

so delay elements 55 and 57 each "0", as shown in FIG. 8 for the period 76. At the entrance 31a of the segregation, however, a single error was observed during the time interval 78. This single error was multiplied and appears during 78 and 79 as an adjacent double fault on the inverter passage 47 of the segregation stage. The error display appears such that the contents of the delay elements 55 and 57 are both "1" at time 712.

To explain the handling of the two check bits

In the decoder 51, with regard to the time intervals 74, 75 and 76, particular reference should once again be made to FIG. 5. During the time interval 74 appears as the input on line 49 a binary "1", while the contents of the delay elements 55 and 57 through a binary “0” or “1” are shown. The EXCLUSIVE-OR gate 53 generates a "1" on the line 54 only if there is a difference between the binary digit on line 49 and the one in the delay

element 57 contained binary digit occurs. Since at time TA a "1" appears both on the input line and in the delay element 57, the EXCLUSIVE V-OR element consequently supplies a "0" at the output. This output signal is shifted into the delay element 55 at the beginning of the time interval TS , its (earlier) content being shifted into the delay element 57 on the other hand. During TS the input is "0" and the output of the delay element 57 is also "0", so that the EXCLUSIVE-OR gate 53 generates a "0". At time T% , the state of the EXCLUSIVE-OR gate 53 reaches the delay element 55 as “0”, while the (earlier) “O” state of the delay element 55 is shifted into the delay element 57. Since the input on the line 49 and the content of the delay element 57 are both "0", the content of the EXCLUSIVE-OR element 53 is "0". At the end of the time interval Γ6, both delay elements 55 and 57 each have a "0", which indicates that no error has been detected. If the last shift is not carried out, an error in the last bit position of the input data sequence cannot be recognized.

What happens in the same system during the time intervals T6-Ti2 for an arbitrary input bit sequence 1001 if a single error occurs, for example, in the second bit position (TS) of a coded data sequence during transmission? This error reaches the segregation stage via input 31a. During the time intervals TT- 7 "10, the successive data digits of the selected example 1001 are coded and transmitted in the manner described above. The error occurring at the time T% at the input of the unmixing stage (in this case the individual error due to the falsification of a» 1 « However, the two adjacent error positions appear during 7 "8 and T9 at the inverter output 47 of the unmixing stage, which can be easily seen by a comparison with the outputs occurring during 7" 2 and Γ3. If one goes through the functional sequence of the decoder in the manner described above for this case, the result is that at the end of the time interval 7 "12 a binary" 1 "is contained in each of the two delay elements 55 and 57. With regard to the representation in FIGS. 2 and 8, it should be noted that between the time intervals TA and TS as well as Γ10 and Γ11 the switch 10c opens by changing from the position 106 to the position 10a. The switch 7c also goes to the position 7a. As a result, the states contained in the delay elements 11 and 13 during the time intervals TA and Γ10 are output during the corresponding time intervals TS, T6 and T 11, T 12, respectively.

If the coding circuit shown in FIG. 6 and in addition instead of the one shown in FIG. 4 the decoder shown Decoder according to Fig. 7, one could again follow the logical sequence through each stage and verify that the inventive method as well as the associated circuit is able to both Detect odd numbers of errors as well as bundle errors.

The in F i g. 7 represents an encoder more complex polynomial

than that in Fig. 2 with g (x) = i + x ² . Regarding the basic circuit design, reference can be made to the book by WW Peterson, "Error-Correcting Codes", MIT Press, Cambridge, Mass., 1961. In addition, a reference to the illustration of FIG. 8 corresponding analysis diagram can be used to check the logical properties of a system shown with these subcircuits according to the type of overview Figure 1.

For this purpose 3 sheets of drawings

Claims (2)

1 2 1967, pages 138,242,243,246,330-335, Proceedings of Claims: the IRE, January 1961, pages 228 to 235; U.S. Patent 3,465,287; IBM Technical Disclosure Bulletin, VoI. 11 1. Device for the detection of odd numbers. May 12, 1969, pages 1623/24.
gen amount of errors in a data transmission input 5 direction using a cyclic code. Some properties of cyclic codes Between the working coder and a corresponding decoder and an additional Mi-Peterson deals with the coding of sequences of scissors and corresponding unmixers, whereby n-r successive digits are indicated by the coder adding r check bits and transmitting the n -r ator polynomial information digits and r check bits. Similar as in the following, Peterson uses for illustration g (x) = (1 + xf t (x) of the binary information a polynomial notation, ie every sequence of binary digits is thought of as and the mixer the mixing polynomial 15 coefficients of corresponding polynomial terms of a dummy variable. In this notation, S (x) =: (1 + xf a block of π bits appears in the form of consecutive ones Polynomial terms up to degree n— \. realized, where t (x) is a polynomial with an odd- For example, the representation of the binary sequence is represents the Güederzahi and m> i and integer 20 0110111 -in this polynomial notation is x + x ² + * ⁴ + * ⁵ + X ^s ; the binary sequence would be accordingly 2. Device for detecting bundle errors 110101 can be written as l + x + x ³ + ^ . This up to a length of b bit positions in a data notation is based on the agreement that the transmission equipment is ordered using a polynomial element according to increasing degree, according to a cyclic code working coding a corresponding decoder and the usual way of first sending the link of the highest order to an additional mixer and sending it accordingly. Peterson also shows that the polynomial mixers, characterized in that the coder expressions can apply the normal calculation rules to the generator polynomial. The only exception is the addi- 30 tion that is to be carried out in modulo 2 fashion. Example: g (x) = {\ + xft (x) (1 + * / = i + x
and the mixer is the mixing pole at x + x ²