DE2252192A1 - INCREMENTAL PROCEDURE AND EQUIPMENT FOR DRAWING THE SQUARE ROOT - Google Patents

Description

Incremental method and device for taking the square root The invention relates to an incremental method of taking the square root the number of input pulses present as a pulse train corresponding to an input variable as well as a circuit arrangement for carrying out this method.

When digitally observing and evaluating an input variable, for example a measured variable, it is often desired, at the same time Conclusions about the measurable variable are not linear and in the case considered here square dependent to get further sizes. Such is the flow rate of a fluid by a flow meter proportional to the square root of the differential pressure at the measuring point. Since this differential pressure is used as the measured quantity, one can only say something about the size of the flow when the pulsatile present Measured variable is square rooted, in other words: it must be the transmission behavior of the The sensor can be linearized.

For this purpose, it is known that the number of pulses counted as a function is decreased or increased by the non-linearity of the characteristic. this happens by frequency dividers or multiplication circuits, their multiplication or Division ratio for all occurring Mefl values due to the difference between the quadratic and one linear characteristic curve in the observed measuring range interval is calculated; see.

Kollataj and Harkonen, ELECTRONICS, March 4, 1968, p. 122 ff.

However, this frequently used method has the disadvantage that For example, when the measuring range is extended, those to be subtracted from the linear characteristic or the correction pulses to be added must be recalculated. Even the circuit implementation must be adapted to the particular application and is also right through the use of complicated and highly integrated components laborious.

It is therefore the object of the invention to provide a method and a device to pull the square root of the number corresponding to an input variable from as Specify pulse sequence present input pulses, with a simple circuitry Realization should be possible.

This object is achieved according to the invention in that of the incoming input pulses successively, starting from i D O, 2i + 1 pulses subtracted where i is the content of a result register corresponding to the square root to be extracted which is increased by "1" each time 2i + 1 input pulses arrive.

In the method according to the invention, the known recursion formula for representing the squares x of the integers y used. At the end of the pulse sequence, the content of the result register represents the end result, ie the square root of the total input pulses, and at the same time determines the number of pulses to be subtracted from the incoming input pulses. This provides an autonomous method which can be used for all input variables present as a pulse sequence without the need to adapt the method steps when processing the input pulses for different input variables.

The circuit arrangement required to carry out the process is drawn are characterized by particular simplicity.

Only two meters are required for this, and their capacity is only the must correspond to the highest square root to be taken, and its counter contents each are linked according to the coding used.

According to a preferred embodiment of the invention, this circuit arrangement is characterized by a first binary counter with one that can be set at parallel inputs Counting base, at whose clock input the to be extracted Pulse rate of Input pulses and when the number of input pulses is the same the counting base is an overflow pulse to the clock input of a second binary counter and then to a set input that enables the parallel inputs of the first binary counter outputs this binary counter, with the corresponding to the sum of the overflow pulses The content of the second binary counter is available at parallel inputs, of which each with a parallel input of the connected to the first binary counter, during which the parallel input representing the lowest rank is fixed with a binary one.

This wiring of the parallel outputs of the second counter with the parallel inputs of the first counter automatically becomes the counting base of the first Counter determined.

With this circuit arrangement, both counters work in pure binary code.

To get a representation in any code, as for example the output of the results in the second counter is facilitated after a further preferred embodiment of the invention, the specified circuit arrangement varies, which is characterized by the following features: A binary coaster with a clock input acted upon by the input pulses, a set input and a Exit; a first "modulo m" counter with one that can be set at parallel inputs Number base, a clock input connected to the output of the binary scaler, a set input that enables the parallel inputs and a series output that emits an overflow pulse when the number of pulses arriving at the clock input falls below the counting base by one; a second "modulo m" counter whose clock input is connected to the series output of the first counter, whose +) is connected to contents corresponds to the sum of the UberZ running pulses emitted by the first counter and on The parallel outputs of the second 'tmodulo m @ counter are available for parallel outputs are each connected to the parallel inputs of the first "modulo" with the same priority m "counter: the series output of the first" modulo-m "counter is also connected via a time delay element with the set input of the binary scaler and the set input of the first "modulo m" meter.

When using counters with any number representation, for example a representation in binary, BCD or another code, need in this embodiment only the parallel outputs of the second counter with the corresponding parallel inputs of the first counter, the first counter then having an overflow pulse releases as soon as a negative carry appears in this counter. Such presettable Counters are already known and have commercially available, higher integrated counting modules realizable. In this exemplary embodiment, therefore, is for the representation of numbers any code in the second counter corresponding to the desired result outputc freely selectable, whereby the same code is then fixed for the first meter.

It is known from German Offenlegungsschrift 1 524 267, the square root of a number in a adding machine using the given Calculate recursion formula; however, it is not an input of the measured variable provided as a pulse train, rather the entire number to be square rooted in Register R1 must be entered.

There are also two registers Ro and R2 and an auxiliary memory Y is necessary, whereby in the register R2 by adding places for each step growing odd Numbers are provided. The initial value this series of odd numbers is in auxiliary memory Y.

Now the respective content of the register R2 is carried out in places complementary addition subtracted from the radicand written in register R1. This subtraction continues until a negative result is obtained, after which the last step is undone. The number of subtraction steps is as a result in the register Ro Apart from that, for this procedure higher cost of circuitry elements than de. Procedure according to the Invention is necessary, it is not without intermediate storage of the entire radicand applicable to an input variable present as a pulse train. This is only possible: by arranging two counters, the counter contents of which are linked to one another in the described Way are coupled.

In the following, two exemplary embodiments of the are based on the drawing Invention described in more detail. The figures show: FIG. 1 a block diagram of a first Embodiment of a circuit arrangement for taking the square root of a Number of input pulses present as a pulse train according to the invention; Fig. La a Table explaining the mode of operation of the circuit arrangement; Fig. 2 is a block diagram of a second embodiment according to the invention and FIG. 2a a corresponding one Table for explaining the mode of operation of this second embodiment.

The pulse signals, e.g. at the output of a digital voltmeter (not shown here) or a frequency counter in digital form available input or measured variable, for example the differential pressure at the measuring point of a flow meter, a sequence of input pulses is assigned to clock input 1 as a subtrahend register 2 designated, binary "modulo m" counter supplied, whose counting base m at his Parallel inputs 7 to 7 can be set. The indices 0 to n + 1 give the Rank of the set binary digits as soon as one of these counting bases is the same Number of input pulses @ the clock input 1 of the subtrahend register 2 supplied is, an overflow pulse appears at a series output 3 of the subtraction register 2 k. This is a clock input 4 of a second result register 5 below called binary counter and stored here. The current content 1 of the result register 5 is therefore made up of the sum of all that have arrived so far Overflow pulses K together.

At parallel outputs 6o, 1, ... 6n of the result register 5 is in binary code the content i available. Each of these parallel outputs 6o to 6n has a one parallel input 71.72 ... 7n + 1 of the subtraw current register 2, while the lowest-ranking parallel input 7 is connected to a binary one is hardwired.

As a result of this position shift, the binary number i appears at the parallel input 7 multiplied by "2" so that after adding the binary one to the lowest Place the number 2i + 1 at the parallel input 7, which is the counting basis of the first Counter 5 defines m = 2i + 1.

In order to allow a clear functional sequence, the series output is 3 of the subtrahend register 2 continues over a delay element 8 connected to a set input 9 of the subtrahend register 2, which takes over releases the parallel information at input 7, with the time constant # of the delay element 8 is greater than the write time of the result register S is. This ensures that after an overflow pulse k has been emitted, this is first written into the result register 5, and then the content i of the result register via the parallel outputs 60 to 6n after the delayed Arrival of the overflow pulse k at the set input 9 as counting base m = 2i + 1 in the subtrahend register 2 is enrolled.

To clarify the mode of action, reference is made to the figure la, in table form the current digital value of the measured variable x, symbolically the Input pulses #, the counting base m of the subtrahend register 2 and the counting base Apart from the input impulses arriving at clock input 1, also symbolically the overflow pulses k and the counter contents i of the result register 5 are shown are.

An asterisk in the bottom row indicates that the Subtrahendenregister 2, so marked the writing of the new counting base m.

Before the start of the evaluation process, the counter content i of the result register 5 cleared to zero. This is also the counting base m of the subtrahend register 2 fixed at m = 2i + 1 = 1. As soon as x assumes the value "1", the clock input 1 of the subtrahend register 2 is supplied with a pulse. This pulse is taken from the counting base m = 1 subtracted, so that the current counter content of the subtrahend register 2 is zero will. An overflow pulse then appears at the series output -3 of the subtrahend register 2 k that in the result register 5 is written so that its Content is now i = 1. The analog content i = 1 corresponds to the binary number representation of the result register 5 a binary L which is applied to the parallel output 60.

After the delayed overflow pulse k has arrived at the set input 9 the binary L is written into the subtrahend register 2 via the parallel input 71, so that its counting base in the binary representation LL or in analog representation "3" is. This process of setting is carried out in the third column of the table marked with a star.

At the value x12, an input pulse f is again entered into the subtrahend register 2 is entered, whereby the number content m is reduced from three to two x reaches the value "4", the counter content m of the subtrahend register 2 is again Zero, so that a second overflow pulse k is written into the result register 5 and its content i assumes the value "2" or LO in binary notation. To the writing of these digits in the subtrahend register 2 becomes their counting base m, written in binary, to LOL, which corresponds to an analog value of "5".

The process described is repeated accordingly with increasing Values of the measured variable x, as shown in the table. From the table is also it can be seen that the content i of the result register 5 is rounded down to whole numbers Is the square root of x, namely i @ entier (x), which - in each case for values x = 1,4,9,16 etc exactly assumes the value of the square root to be taken 1,2,3,4 etc. So is a statement about the rounding error of the smallest. Place of result made; e.g. n places after the decimal point can be obtained if the unit of the input variable 1On corresponds to pulses.

In the circuit arrangement described, subtrahend and result registers Be a binary counter, then the simple derivation of the counting basis m »2i + 1 from the content i of the result register by shifting the binary number to the left by one digit plus a hardwired binary one is possible. In many cases the representation is of the result i @ another K @ de desirable, e.g. for simple decdic Result display in BCD code, with which no complex recoding circuit is used must become. With the circuit variant shown in Zig 2, the possibility of Use of a result register given in any code, with only result and subtrahend registers to enable parallel transitions of the content i im the same code must work.

The input pulses # are a binary scaler 11 with a clock input 12 and additional set input 13 and only then bar its output 14 the clock input 15 of a subtrahend register 16 is supplied. The subtrahend register 16, also fails a "modulo m" counter with a counting base m that can be set via parallel inputs 17, gives when the number of pulses arriving at clock input 15 # the counting base m exceeds by one, an overflow pulse k from its series output 18. As previously described, this overflow pulse k is entered in a result register 20 @ input 22 so that @ the sum of the overflow pulses k is calculated @ @ at parallel outputs 21 of the result @ t @ permanently available content i is via the P @@ sillelei @@ length 17 in the subtrahend register 16 through the in one Delay element 23 triggered by overflow pulse k delayed by t. In addition to the setting of the su @ trahenden @ egister 16, the overflow pulse K of the binary @ setter 11 to "interest", binary L, so that si @ h the following in the table 2a shows the mode of operation of the circuit arrangement described.

Before the start of the measurement, the content of the result register 20 is displayed i = O deleted. The counting base m of the subtrahend register 16 is in this case m = i = 0; the binary scaler 11 is set to BU = L. As soon as the measured variable x den Assumes value 1, i.e. a pulse # appears at clock input 12 of subquiler 11, the binary scaler 11 switches on to "0" and emits an overflow pulse t; to the clock input 15 of the subtrahend register 16. This impulse is from the Counting base m-O subtracted, so that the value 'of the counter content of the subtrahend register 16 runs below zero. The subtrahend register 16 then gives an overflow pulse k, which is written into the result register 20, so that its counter content increased to i = 1 After a time delay @ @ the overflow pulse k triggers the takeover this new content i = 1 into the subtrahend register 16, so that its new Counting base m = 1.

With the same overflow pulse, the binary scaler will open again BU = L set.

At the second incoming pulse 5., which corresponds to the value x-2, the binary scaler 11 switches again by emitting an overflow pulse # to BU = O, 'so that the counter content of the subtrahend register 16 changes from m = 1 reduced to m = O.

The binary scaler switches with the next pulse #, which corresponds to x3 11 to BU = L, so that no overflow pulse # occurs. Only with that the next pulse #, which corresponds to x = 4, the binary scaler 11 goes under Abçabe of a pulse in the state BU = 0 over, so that thereby the value of the content of the Subtrahendenregister 16 runs below zero and at its output an overflow pulse k appears. This increases the counter content of the result register @ 0 to i = 2.

After setting it again, in the table with an asterisk in the corresponding Indicated in the column, the counting base of the subtrahend register 16 has the @ert m = 2, while the binary scaler 11 switches to the state 3U = L.

For the following pulses #, which correspond to the values x = 5,6,7 and 8, the binary scaler 11 only emits an overflow pulse for the; 7ths x = 5 and x = 7 # to the subtrahend register 16, whereby its content gradually changes from 2 reduced to 0. With the ninth pulse I air the counter contents of the subtrahend register 16 again below the value "0", so that again an overflow pulse k is sent to the result register 20 is delivered, the content of which is now i, 3.

These steps continue until the end of the pulse train, see above daF then in the result register 20 the on whole numbers, or - as mentioned above - the square root of X rounded off to a certain number after Konn.a appears.

Patent claims:

Claims (3)

Claims 1 '. Incremental method for taking the square root the number of input pulses present as a pulse train corresponding to an input size, thereby q e -k e n n n z e i c h n e t that of the incoming input pulses (#) successively, starting from i = 0, 2i + 1 pulses are subtracted, where i is the the content of a result register (5; 20) corresponds to the square root to be taken, which is increased by one after the arrival of 2i + 1 input pulses (2). Circuit arrangement for carrying out the method according to claim 1 to take the square root of the number of corresponding to an input variable as a pulse following input pulses, g e kZe n n z e i c h n e t through a first binary counter (subtrahend register 16) with one on parallel inputs (17) settable counting base (m), at whose clock input (15) the to be rooted q de Pulse sequence of the input pulses () and the if the number of input pulses () is always equal to the counting base (m.), an overflow pulse (k) to the clock input (4;) of a second binary counter (result register 5) and then to one of the parallel inputs (7) of the first binary counter (2) enabling set input (S of this binary counter (2), the content corresponding to the sum of the overflow pulses (k) ( i) the second binary counter (5) is available at parallel outputs (6ob to 6n), each of which has a parallel input representing a "1" higher priority (71 to 7n + 1) of the first binary counter, during which the lowest The parallel input (7J) representing the priority level is fixed with a binary one (L) is. 3. Circuit arrangement for performing the method according to claim 1 to pull the square root of the number of an input variable corresponding to Input pulses present as a pulse train, g e k e n n n z e i c h -n e t through the following features: a binary scaler (11) with one of the input pulses (#) applied clock input (12), a set input (13) and an output (14); a first "modulo m" = counter (subtrahend register 16) with one at parallel inputs (17) settable counting base (m), one with the output (14) of the binary scaler (11) connected clock input (15), a set input that releases the parallel inputs (17) (19) and a series output (18), which emits an overflow pulse (k) when the The number of pulses (r) arriving at the clock input (15) increases the counting base (m) by one falls below; a second "modulo m" counter (result register 20), whose clock input (22) is connected to the series output (18) of the first counter (16), the content of which (i) corresponds to the sum of the overflow pulses (k) emitted by the first counter (16) and is available at parallel outputs (21); the parallel outputs (21) of the second "modulo m" counter (20) are each connected to the parallel inputs with the same priority (17) of the first "modulo m" counter (16) connected; further is the Series output (18) of the first "modulo m" counter (16) via a time delay element (23) with the set input (13) of the binary scaler (11) and the set input (19) of the first> modulo m1> counter (16).