DE2235308A1 - CIRCUIT ARRANGEMENT FOR DETECTING THE DIGITAL CONDITION OF ELECTRICAL SIGNALS - Google Patents

Description

Circuit arrangement for verifying the digital state of electrical Signals.

The invention is concerned with a circuit arrangement for detection the digital state of electrical signals with an input delay element and an input comparator, which is delayed by the input delay element compares with the non-delayed input signal and if the two are inequality Input signals emits an output signal, with one to the output of the input comparator connected counting stage, which is generated for each output signal of the input comparator starts to count from an initial value and only after reaching a predeterminable value Counting time emits an output pulse, and with a final comparator, whose to its one input with the output of the counter stage and its other input with the output of the input delay element is connected and the presence of signals an output signal at the output of the input comparator and at the output of the counter stage gives away.

Such circuit arrangements can be used to prove whether electrical signals that change their digital state are in the new state one Persist minimum time. Brief changes in the state of such electrical signals, how they are caused by malfunctions, for example by bouncing on switches can, should as not valid changes of state are recognized.

The circuit arrangements described can be used in particular for Use reliable detection of the insertion of coins into the coin stacking tubes of coin machines. In such coin stacking tubes namely switches are provided that one in the Have Nünzkanal the Nünzstapelrohrs projecting switching arm. The switch arm is from the inserted coins moving through the channel due to the force of gravity actuated. When coins hit the switch arm, bouncing often occurs, in which the switching arm performs fluttering movements. The flutter movements are supposed to however not already considered to be inserted coin or even inserted coins will.

Let the known circuit arrangements of the type mentioned above however only to prove the digital state of single-channel electrical signals, as they arise, for example, in a coin stack tube. When signals occur in several channels, it would be possible to use several of the circuit arrangements described However, such a technique would be particularly useful because it is for each channel then required counting steps very expensive.

The invention is based on the object of a simply constructed Circuit arrangement for verifying the digital state of multiple channels at the same time to create occurring electrical signals.

In the case of a circuit arrangement, this task becomes the one mentioned at the beginning Art solved in that for processing of multiple channels occurring at the same time Signals the input of the input delay element and the free input of the A time division multiplex circuit is connected upstream of the input comparator and that the input delay element one Has delay time that is equal to the product of one is an integer multiple of the number of channels and the cycle time.

According to the invention, the incoming on multiple channels are Input signals initially fed to an input multiplexer circuit and in this Circuit converted into a multiplexed single channel signal. Through this multiplexed single-channel signal, the counter level is reset at each transition until the There is enough time between two transitions for them to continue counting to their final value can. When the end value is reached, the counting stage emits an output signal which allows the information signal to pass through the final comparator. Then takes place a counting for a new state of another channel and it will upon reaching of the final value in turn emitted an output signal for controlling the final comparator. This process is repeated until the states of the signals on all input channels are proven over the predetermined counting time. Each time the predetermined one is reached Counting time, an output pulse is emitted at the output of the counting stage, which contains the information signal at the output of the input delay element through the final comparator to the output the circuit forwards. A prerequisite for error-free work is that the duration of the valid signals is at least as long as the product of the predetermined Counting time of the counting level and twice the number of channels.

The new circuit arrangement is particularly advantageous because there are none to prove the digital state of signals on multiple channels additional counting stages are required. The counting levels are relative the most complex part of the circuit arrangement.

An advantageous development of the circuit arrangement is thereby characterized in that the output of the input delay element with one of the Counting stage through controllable switching mechanism is connected, the output of which is connected to the input of the final comparator and connected to the input of an output delay element is that the output of the output delay element with the input of the switching mechanism to enable complete information signal circulation is connected that the counting stage is designed in such a way that it only responds to O-L transitions, and that a further counting stage is provided, the input of which is connected to the output of the input comparator and whose output is connected to the switching mechanism, which in its mode of operation of the corresponds to another counting level, but only responds to O-L transitions and upon delivery of a pulse at the output the switching mechanism and the output delay element for resets the channel in question to its original state.

With the circuit arrangement developed in this way, it is possible, the digital status after a complete counting process in all channels to be demonstrated if a change in status occurs in all channels at the same time.

Namely after the counting stage has reached its predetermined counting time has, the information contained in the input delay element is direct passed on to the final comparator without being used for the signals sent to the individual Channels are assigned, the counter level once again to prove the status up runs to its final value. This enables the detection of signals to be carried out even more quickly than the basic arrangement and the circuit arrangement is faster for further evidence is free. On the other hand, in this further developed circuit arrangement another counting stage is provided, which is used for L-O transitions for the concerned Channel a safe reset of the switching mechanism and the output delay element guaranteed, and errors are even better avoided.

The circuit arrangement is further developed in that between an intermediate comparator at the input of the switching mechanism and the output of the input delay element is switched, whose further comparison input with the output of the output delay element is connected and the information signal emitted by the input delay element only passes on if there is no information signal in the output delay element.

Even with the further developed circuit arrangements according to the invention only two counting stages are provided, which allow a very reliable operation.

The circuit arrangement according to the invention and its developments can be produced simply and cost-effectively, especially if they are in integrated circuit technology. In particular, it is beneficial execute the circuit arrangements in MOS (metal oxide semiconductdt technology).

Embodiments of the invention are described below with reference to the drawings described. The figures show: FIG. 1 a block diagram of an embodiment of FIG Circuit arrangement according to the invention with switching mechanism, output delay element and interim comparators, 2 shows a section through a coin stacking tube, 3 shows a signal that changes between two states, as is the case with a throw-in qüxize a ze can arise in the coin stack tube according to FIG. 2 and FIG. 4 shows a more detailed one Circuit diagram of an embodiment of the invention according to the block diagram of FIG. 1.

In Fig. 1 is an embodiment of a circuit arrangement for detection the digital state of electrical time-division multiplexed signals. With this circuit arrangement the information signal lines are attached to the vertical sides of the blocks and the control signal lines are attached to the horizontal sides of the blocks. The circuit arrangement has on the input side a time division multiplex circuit, whose Input terminals with the outputs of various types, for example actuated by coins Switches are connected.

The output of the time division multiplexing circuit containing the information Emits time-division multiplexed signals is to the information input of an input delay element 2 connected.

The information output of the input delay element 2 is with the Input of an intermediate comparator 8 connected, the output of which to a first information input a rear derailleur 9 leads. The output of the switching mechanism 9 is on the one hand to the information input a final comparator 10 and on the other hand via a non-element 11 to the information input an output delay element 12 connected.

The output of the final comparator represents the information output terminal the circuit arrangement. The information output of the output delay element 12 is connected to a second information input of the switching mechanism 9.

The following are those used to control the information Devices of the circuit arrangement described.

A control output of the time division multiplex circuit 1 is connected to a first Control input of an input comparator 3 connected.

A second control input of the input comparator 3 is connected to one Control output of the input delay element 2 connected. The control output of the input comparator 3 is each with a first input of two counting stages 4 and 5 connected. Another control output of the time division multiplex circuit 1 leads directly to a second input of the counting stage 4 and via a non-circuit 6 to a second input of counting stage 5. The control outputs of counting stages 4 and 5 are connected to control inputs of the switching mechanism 9.

In addition to the output carrying the information, the switching mechanism 9 has a control output which is connected to a control input of the end comparator 10 is. The output delay element 12 has in addition to the information emitting Output has another control output, which is connected to another control input of the End comparator 10, a control input of the intermediate comparator 8, another Control input of the counting stage 5 and a non-circuit 7 with another Control input of the counting stage 4 and another input of the switching mechanism 9 are connected is. There is also a clock (not shown) is provided that the counting stages, Delay elements and other clock-controlled elements controls. -The following will the mode of operation of the circuit arrangement according to FIG. 1 is now explained: that of the time division multiplex circuit 1 binary switch signals supplied on parallel input lines are triggered by this time division multiplex circuit into a single binary multiplex signal converted. As already mentioned at the beginning, an O-L transition or of an L-O transition in any of the channels can be checked to see if they are contrary to a glitch around a true transition of the binary state in the relevant Channel, a true transition is characterized by the fact that the new Binary state is maintained for a minimum time.

However, an output signal should only then be present at the output of the circuit arrangement appear when a newly occurring binary L is held for a minimum amount of time. On the other hand, a reset of the circuit arrangement for the channel in which the binary L has been held for a required minimum time only if in the event of an L-O transition, the binary state O is held for a corresponding minimum time became.

In Fig. 2 a part of a coin channel of a coin stacking tube is a Slot machines shown, in which when a coin 13 is inserted, the mentioned Switch signals for a channel occur. The coin 13 slips namely through the Channel 14, in which a switching arm 15 of a switch is located. When the coin strikes the switch arm of the holder, it is pushed back so that the Coin can continue to run past the switch arm through the channel. At the first push the coin against the switching arm, this switching arm is in a swinging motion offset so that the output signal of the switch initially between 0 and L back and forth before it reaches a constant value.

A switch output signal that occurs when a coin passes through the coin channel is created is shown in FIG. 3. If there is no t in the timeline follows, you can first see the oscillations of the switching arm, which are frequent Express changes in state. In the middle part, the switch signal takes longer Display a constant value.

Only when the coin has completely passed the switch arm, if the switch drops to 0 from, but again after a corresponding oscillation process, during which the signal between the State 0 and state L swiftly back and forth X. rm the insertion of coins To be able to count exactly in the coin channel, it is necessary to wait until the vibrations have faded out and then in each case it can be proven that the set State of the signal is held for a certain minimum time.

The circuit arrangement according to the invention should therefore be like a filter act, which forwards signals to the output that have a state adhere to a certain period of time.

Checking whether the information has changed after a binary state change of a channel the new state is held for a minimum time or not occurs with the help of the two counting levels 4 and 5 and the switching mechanism 9. So there is the switching mechanism 9 the incoming information, which has assumed the state L, only 'further if it is switched through by a control signal from counting stage 4. Counting level 4 on the other hand, only emits a control signal if it has been released by a 0-L transition can continue counting a certain number of clock pulses. Counting on takes place directly - with the help of the external clock. However, occurs before expiration from the determined number of cycles on a further 0-L transition, the counting stage becomes 4 released again, so that at its output only after a renewed further counting a control signal can be issued up to the specified number of cycles, provided that. no further release of counting level 4 takes place.

Counting stage 4 is enabled when there is a 0-L transition via the Input comparator 3. The input comparator 3 always gives a control pulse when there is a change in the signal state (O-L transition or L-O transition) within the delay time of the input delay element 2 occurs. For approval of the counting stage 4, however, the further condition that the binary state goes from 0 to L, so that on the control line from the time division multiplex circuit 1, the state L is present for counting stage 4.

At the output of the switching mechanism 9 there is consequently only information appear at a 0-L transition, if the binary state L over the full counting time the counting stage 4 is present on the relevant channel of the time division multiplex circuit.

On the other hand, an L-0 transition does not lead to the relevant channel to a reset of the counting stage 4. There is simply no more information are present at the input of the switching mechanism 9, which also no longer has any information at the output of the rear derailleur 9 can be delivered.

Let it now be the path of information between the input delay element 2 and the rear derailleur 9 considered. The delayed by the input delay element 2 Before it reaches the switching mechanism 9, information is passed through the intermediate comparator 8 led. In the intermediate comparator 8, the information is matched with that at the output of the output delay element 12 pending information compared. Differentiate Both pieces of information are from each other, i.e. they are located in the exit delay element 12 still has no information for the channel in question, the input delay element 2 fed information is forwarded by the intermediate comparator 8 to the switching mechanism 9. Is located on the other hand at the output of the output delay element 12 already contains a piece of information, then that of the input delay element 2 becomes further information is not passed on to the rear derailleur 9.

The information appearing at the output of the switching mechanism 9 is the End comparator 10 supplied, but only forwarded by this if at the output of the output delay element 12 is no information and if further from Switching mechanism 9 emits a control signal which is determined by the control signal of the Counting stage 4 is caused when its final value is reached. Even if the one in the The newly set binary state L is maintained for a longer period of time in the relevant channel is, however, no more output information appears at the output for two reasons. Once the content of the output delay element 12 is on the new binary state L modified and thus the final comparator 10 blocked. On the other hand, there is the counting level after a further clock number corresponding to the number of channels, so that the final comparator 10 is also blocked by the switching mechanism 9 via the control line.

On the other hand, it is also the one at the output of the output delay element 12 occurring information is fed back to the switching mechanism 9 and also to the output of the switching mechanism 9 forwarded and written back into the output delay element, provided that none of the counter stages emits a control pulse. So the information runs for the relevant channel in the circle between switching mechanism 9, non-switching 11 and Exit delay element 12 and back to the switching mechanism 9 to. At the exit of the Circuit arrangement, however, no information can appear because the final comparator 10 because of the blocking effect by the output delay element 12 and because of the blocking effect of payment level 4 does not let any information through.

Each time the information is circulated, the output delay element appears at the output 12th a control pulse is given. However, this control pulse not only blocks the final comparator 10 but also the intermediate comparator 8, so that no further information for this channel in question can get into the switching mechanism 9. This blocking effect the intermediate comparator 8 is only for the information in the relevant Channel available. Only when the binary state is in the relevant channel again changes in that an L-O transition occurs, this new information is passed through the interim comparator 8 can be routed to the switching mechanism 9.

In the event of such an L-0 transition, the input comparator 3 is again after the delay time of the input delay element 2, a control pulse L and a control pulse 0 is supplied.

A control pulse is thus generated at the output of the input comparator 3. However, this control pulse can only reset counting stage 5, since the information 0 via the non-circuit 6 at the other input of the counting stage 5 also a for Releasing the counting stage 5 generates the necessary L. As a further condition for the release the counting stage 5 must still have the control signal at the output of the output delay element 12 L in contact. This condition is met because the information from the exit delay element 12 revolves continuously via the switching mechanism 9 and the non-circuit 11. When the counting level 5 is enabled, it is incremented in the cycle up to a certain value.

If there is no further reset to enable counting level 5, then it emits a control pulse as soon as it has reached a certain number of cycles, the one more circulation of the information between the output delay element 12, the rear derailleur 9 and the non-shifting 11 prevented. The information at the exit the multiplex circuit, namely the now set binary 0 is in the intermediate comparator 8 forwarded as a binary L to the switching mechanism 9. However, this binary L cannot through the final comparator 10 to the output of the circuit arrangement passed on because of the information previously pending on the relevant channel L a binary blocking signal is present at the output of the output delay element 12, which blocks the final comparator 10. Since counting stage 5 only receives a control pulse is issued until this counting stage turns itself after another one of the channel number resets the corresponding cycle number, any further information in the relevant Channel that reaches the switching mechanism 9 can no longer be passed on.

The circuit arrangement consequently only gives an output pulse at the output when there is a 0-L-transition in which the binary state L at least during the duration of the counting stage 4 is maintained in the relevant channel.

When counting stage 4 is released again by its own reset pulse has been, it is available for another counting process in every other channel Disposal. The same applies to counting level 5.

If 0-L transitions occur in different channels before the counting stage 4 was able to run through to its reset value, it will go through these transitions released each time. From the "last" transition on, the counting stage 4 can finally run through undisturbed up to their reset value and thus enables an output pulse at the final comparator. In the channels in which 0-L transitions had already taken place, binary states L are already being written into the input delay element 2. Since now the output control signal of the counting stage 4 via one of the number of channels corresponding Number of clocks is present, all information that is in the input delay element 2 are written, through the switching mechanism 9 to the final comparator 10 and its output forwarded.

The prerequisite for this, however, is that in the individual channels no information is written into the output delay element 12. The input signals must maintain multi-channel verification over times in this type of multiplexing which are at least as long as the product of the predetermined counting time or throughput time of counting level 4 and the number of channels. The same applies accordingly for the duration of the binary state O, since the counter stage 5 in any case by L-O transitions can be reset in further stages until it reaches its final value can go through with the delivery of a control pulse.

In Fig. 4 is a detailed circuit diagram of the essential Parts of the block diagram of FIG. 1 are shown.

At the input there is again the time division multiplex circuit 1, whose Output with both the input delay element 2 and the input comparator 3 is connected. The output of the input delay element 2 is also connected to the input comparator. The output of the input comparator 3 is as already described, connected to one input each of counting levels 4 and 5. It can be seen that the output signal of the input comparator 3 AND circuits 16 and 17 of the counting stages 4 and 5 is fed. The AND circuit 16 is also direct connected to the output of the input multiplex circuit 1, while the AND circuit 17 with the inverted output of the input multiplex circuit via the non-circuit 6 1 is connected. The other inputs of the AND circuit 16 and 17 have reset outputs of its own counting stages as well as with the output of the output delay element 12 resp. its inverted output connected. The output of the AND circuit 16 is with the reset input of a bistable flip-flop 18 and with a capture of a NOR circuit 19 connected. The output of the NOR circuit 19 is with a no circuit connected, the output of which is connected to the input of a Counter 21 led is. The counter 21 is reset to 0 with each input pulse and runs then continue in the measure until it has run through a certain number of measures which it emits an output signal. The output of the counter 21 through which the signal is issued after the certain number of cycles, is a bistable with a set input Toggle circuit 22 connected. The counter 21 also gives after a further number of Cycle that can roughly correspond to the number of channels at another output Reset pulse, this output with the set input of the bistable multivibrator 18 is connected and also with a non-circuit 23, which is connected to the negative Reset input of the bistable flip-flop 22 is connected. The output of the bistable Flip circuit 18 is connected to the further input of the NOR circuit 19.

The output of the bistable multivibrator 22 represents the output of the Counting stage 4 represents. It is connected to the switching mechanism 9. The output of the bistable Flip circuit 22 is also via a non-circuit 10 with an input of the AND circuit 16 connected. So if at the output of the counting stage 4 after the certain number of cycles a control signal is present, then the AND circuit 16 and thus the input of counting level 4 blocked. The counter 21 will therefore certainly continue to run for a few clocks can until it emits a reset pulse, both of the flip-flop 18, as well as the bistable flip-flop 22 is fed. The bistable trigger circuit 18 is set while the flip-flop? 2 is reset. In order to the output signal of counter stage 4 becomes 0 again.

The counting stage 5 is constructed in accordance with the counting stage 4 and they also works accordingly, only that it is reset to the initial value of the counter does not take place with a transition from 0 to L, but with the transition from ßem state L to the state 0. This is achieved by the of the Multiplex circuit 1 supplied input signal in the non-circuit 6 inverted will. The counting stage 5 has, corresponding to the counting stage 4, in addition to the AND circuit 17 a flip-flop circuit 25, a NOR circuit 26, a non-circuit 27, a counter 28 and a flip-flop 29 and non-circuits 30 and 31 on The output of the bistable trigger circuit 29 acts as the output of the Counting stage 5 and it is connected to the switching mechanism 9. The two output control signals the counting stages 4 and 5 are used to control the switching mechanism 9, and through them is also determines whether information signals can pass through the switching mechanism 9 or not.

The information signals occurring at the output of the input delay element 2 are, as already described with reference to the block diagram of FIG. 1, about the Intermediate comparator 8 fed to the switching mechanism 9.

Let it be the structure and the mode of operation of the rear derailleur g considered closer.

The switching mechanism 9 is made up of AND circuits, AND non-circuits and NOR circuits assembled. There are circuits 32, 33, 34, 35, 36, 37 and 38 provided. The AND circuit 33 has three inputs, one of which with the output of the intermediate comparator 8, another via the non-circuit 7 with the output of the output delay element 12 and the third with the output the counting stage 4 is connected. The output of the AND circuit 33 has an input the NOR circuit 32 is connected. It therefore becomes the information signal at the output of the intermediate comparator 8 is only forwarded to the input of the NOR circuit 32, if no information is available at the output of the output delay element 12 and if further the counting stage 4 up to the delivery an output signal has counted. The AND not circuit, 34 has two inputs, one of which the one in turn with the output of the ~ white comparator 8 and the other with the output of the counting stage 5 is connected. The output of this AND-not circuit 34 is connected to one input of the AND circuit 36. At the output of this AND-not circuit 34 a signal only appears if one or both input signals are 0. This occurs when either no information is given by the interim comparator will or if the ~ output of counter stage 5 is 0 or if both are also 0.

The NOR circuit 55 has two inputs, one of which with the output of the counting stage 4 and the other is connected to the output of the counting stage 5 is. Only if there is no output signal at the outputs of both counting levels 4 and 5, An output signal will appear at the output of this circuit. The outcome of the The NOR circuit is connected once to the final comparator, a NOR circuit 10 and on the other hand with one input of an AND circuit 38. The other input of the AND circuit 38 is connected to the output of output delay element 12. The AND circuit 36 also has an input that is connected to the output of the Output delay element 12 is connected, as is the AND circuit 37, whose other input is connected to the output of counting stage 4. As long as at the exit of the Output delay element 12 is no information available, block the AND circuits 36 to 38, the outputs of which are connected to three inputs of the NOR circuit 32 and generate Nuil signals at these inputs. It can only if the counting level 4 could count freely and if there is output information at the output of the intermediate comparator 8 is applied, get a signal to the fourth input of the NOR circuit 32, which with the output of the AND circuit 33 is connected. This information signal at the input the NOR circuit 32 causes at its output no signal is present. The output of the NOR circuit 32 is, however, connected to an input of the final comparator 10 connected.

Another input of the final comparator is with the output of the output delay element 12, as already mentioned above, connected. The third input of the final comparator 10 is connected to the output of the NOR circuit 35. Because at the output of the counting stage 4 a signal is applied, the output signal of the NOR circuit 35 is also 0, see above that the three inputs of the final comparator are supplied with signals. In order to appears at the output of the final comparator 10 and thus at the output of the circuit arrangement an impulse. Furthermore, of course, the information signal is sent to the output delay element 12 registered. The information signal is in the output delay element 12 in Clock switched on. When it gets to its output, it is via the AND circuit 36, 37 and 38 are fed back to the NOR circuit 32. Furthermore, it is about the non-circuit 7 the AND circuit 33 blocked, so that no further information signal from the intermediate comparator can get to the rear derailleur. Ba s The information signal is then as long as circulate between output delay element 12 and switching mechanism 9 until the counting stage 5 an output signal is emitted, which via the circuits 34 and 35 at all Inputs of the NOR circuit 32 0 signals appear. The content of the The output delay element is reset from 1 to 0 and the switching mechanism is free again for a new verification process. In this case, however, it results no signal at the output of the final comparator, because at the output of the output delay element 12 an information signal is still present, so that not all inputs of the final comparator Have signals.

It should also be pointed out that the circuit arrangement shown in FIG in addition to comparison circuits, only AND circuits, NOR circuits and non-circuits having.

This circuit arrangement is therefore particularly suitable for integrated circuit technology. The circuit arrangement can of course also be used with others logic gates, for example NAND circuits, OR circuits and non-circuits or also from other groups of links or combinations are formed from this.

Claims (5)

Claims Circuit arrangement for verifying the digital state of electrical Signals with an input delay element and an input comparator, the delayed by the input delay element with the non-delayed input signal compares and emits an output signal if the two input signals are different, with a counting stage connected to the output of the input comparator, which counting from an initial value for each output signal of the input comparator starts and only after reaching a predeterminable counting time an output pulse outputs, and with a final comparator, one input of which is connected to the output of the counting stage and its other input is connected to the output of the input delay element and the presence of signals at the output of the input comparator and emits an output signal at the output of the counting stage, characterized in that for processing signals occurring simultaneously in several channels dem Input of the input delay element (2) and the free input of the input comparator (3) a time division multiplex circuit (1) is connected upstream and that the input delay element (2) has a total delay time equal to the product of a whole Multiples of the number of channels and the cycle time. 2. Circuit arrangement according to claim 1, characterized in that the output of the input delay element (2) with one of the counting stage (4) controllable Switching mechanism (9) is connected, the output of which is connected to the input of the final comparator (10) and is connected to the input of an output delay element (12), däß the output of the output delay element (12) with the input of the switching mechanism (9) is connected to enable complete information signal circulation, that the counting stage (4) is designed in such a way that it only responds to O-L transitions and that a further counting stage (5) is provided, the input of which connects to the output of the input comparator (3) and whose output is connected to the switching mechanism (), which corresponds in their mode of action to the other counting stage (4-), but only on L-O transitions responds and when a pulse is emitted at the output, the switching mechanism (9) 'and the output delay element (12) for the relevant channel in their Resets the initial state. 3. Circuit arrangement according to claim 2, characterized in that between the input of the switching mechanism (9) and the output of the input delay element (3) an intermediate comparator (8) is connected, the further comparison input of which is connected to the output of the output delay element and that of the input delay element The information signal only passes on if it is in the output delay element there is no information signal. 4. Circuit arrangement according to one of the preceding claims, characterized characterized in that it is implemented in integrated circuit technology. 5. Circuit arrangement according to one of the preceding claims d a it is indicated that it is implemented in MOS technology.