DE2234203A1 - METHOD AND DEVICE FOR RECEIVING SERIAL INCOMING DIGITAL, PHASE-CODED SIGNALS - Google Patents

Description

Method and device for receiving serially arriving, digital, Phase Encoded Signals The Brfindttng relates to a method and apparatus to receive serially arriving, phase-coded in the manner of a directional clock script, in the event of an error, signals that are not recognizable, ~ The directional clock is a known writing method used in magnetic tape or magnetic disk storage. When reading data recorded in this document, signals arise from which a clock signal sequence can be derived. By that of the directional tactical script Adhering redundant representation of the data, errors that occur during reading can be avoided recognize (article: "Design Approach for a Digital Casette Recording System", by J. Sykes in "Computer Design", October 1970, page 101).

Which correspond to phase-coded signals in the manner of a directional clock Signals as they occur when reading magnetic tape or magnetic disk memories, on which binary characters are stored in such a font. The binary characters "L" or "O" are differentiated by positive or negative signals after the expiry half of the period assigned to a binary character. With consecutive The same binary characters result in further positive ones at the beginning of each new period or negative signals. The recording density of binary characters and the speed with which the storage media are moved past reading heads, determine the magnetic tape or -disk store the duration of a period within which a signal occurs got to. Under binary characters, the text in the following # is one of the logical constants 'O' or 'L' to be understood in directional clock script on a storage medium recorded or in one of the direction Corresponding clock script Way can be prepared for a data transmission.

The invention is based on the object of a method Euld a Device for receiving serially arriving, digital, in the manner of one r i directional clock ft phasellcodiertetl in case of an error undetectable signals zt # ~ # itwind, the one error detection and error correction without repeated transmission of the same Enable data or encryption using additional data.

The object is achieved according to the invention in that from the temporal Distance between two consecutively received signals is the period between two incoming signals Calculated binary characters and a clock signal sequence 'whose period and phase with the Signals is synchronized, it is generated that the binary characters by one period the clock signal sequence are forwarded out of phase and that due to the mutually different polarities of two according to the directional clock successive signals taking into account the polarity and phase of the last received signal before the absence and the first received signal after the absence of signals for one or more consecutive clock periods a correspondingly supplemented binary character is output and / or an error message is generated will.

The invention makes use of the polarity and phase position of the last received signal to be expected in the absence of one in the middle of the period Signal to determine the corresponding binary character. All errors that result in the absence or the loss of an expected signal are therefore corrected. If a missing signal is added in the middle of a period, then one in the Signal not received in the middle of the subsequent period due to a signal be corrected with polarity reversed with respect to the supplemented signal. the Bug fix Thus includes the remaining number, namely seven out of eight of all molichen failures are two consecutive signals Rapid possible failures of three consecutive signals.

Another advantage of the method according to the invention is that rin that signals with periods of different sizes can be processed.

In a preferred embodiment it is provided that counting pulses are summed up in the time between two consecutively received signals, that the counting result is divided to distinguish half-periods, which also are counted that the first half of the period is a signal that is a binary character corresponds to and the second half of the period a signal that two consecutive corresponds to the same binary characters, Iind that for phase synchronization is assigned every incoming signal the period half count is halved by the duration to limit the currently applied half of the period, while in the absence of one Signals the clock signal sequence with that synchronized with the last received signal Period and phase expires.

This method delivers a clock signal sequence without complex measures, which is synchronized with the received signals. The signals occur etça in the middle of the period halves. Although there is no synchronization if there are no signals the clock signal sequence takes place, the location of the before and after the absence of Signals received signals within the period halves significantly from each other deviate without losing the assignment of the signals to the period halves. The counter shows the number of period halves that have elapsed. # Ii Receipt of the last signal detected. The value in the pulse counter is used to correct the period divides the clock signal sequence according to the counted half-time periods.

In a further development of the method according to the invention, when commissioning the transmission of the count is based on a fixed value that is so large is that there is at least two clock periods between the first and second received signals expire. This value depends on the transmission speed and can can be roughly determined from this. With this further development of the process takes place the frequency and phase synchronization of the clock signals after the second received signal, while the error correction already starts with the transmission begins.

A favorable embodiment is that the beginning of a Transmission is always determined by the same coded signal sequence and that starting from the known polarity of the signals in the absence of a signal a corresponding one Binary character is added.

Another favorable embodiment is that the received Positive or negative polarity assigned to signals to determine the pre or Downward counting direction of a counter acted upon by the signals serves that at an error signal is generated from zero or one different count and that after a clock signal period has elapsed in which there is no corresponding binary character Signal has been received, the count is preset to two.

If a signal assigned to a binary character was not received, an error signal results in this embodiment.

Becomes one that occurs with two consecutive, identical binary characters Signal not received, then also occurs when the next signal is received an error signal. This means that all errors that occur after the Detect synchronization of clock signals and received signals.

Furthermore, errors can be detected if, after the start of the Transmission the first signal does not arrive.

The error detection can # with advantage when writing information to be used on a tape. As the written information for verification afterwards is read, the error signal is used to ensure that the faulty reception causing Information is rewritten. On the other hand, if a tape is only to be read, then the error correction is carried out while the error signal is ignored.

In the case of a device for carrying out the method, it is provided that the signals going back to positive and negative signals each correspond to the setting or the reset path of a flip-flop that can be fed with an EXCLUSIVE-OR gate is connected, which is led to the preparatory input of a flip-flop, whose triggering input can be acted upon by the signals of the clock signal sequence whose Period and phase is synchronized with the incoming signals, and that the second Input of the EXCLUSIVE-OR gate is connected to a flip-flop, into which upon receipt of a signal, a signal negated to the clock signal can be stored, while a Presetting via a gate circuit that can be controlled by the clock signal and a deletion can be produced via a counter that determines the half-periods of the clock signal.

A distinction is made over the half-periods of the clock signal sequence of signals assigned to a binary character and of intermediate pulses possible that arise when two binary characters of the same type follow one another. Under The redundancy of the directional clock can then be used in the absence of a Signal in the half-periods in which a signal is to be expected, the corresponding Corrections are made. The arrangement comes with little circuitry Effort. If a magnetic tape is used as storage, then one track is sufficient for the data recording.

One. preferred embodiment is that counting pulses in Up counters can be entered1 which have the content zero when a signal is received are resettable that before resetting the counter contents with simultaneous Division can be entered in shift registers, the content of which can be fed to down counters is, whose content is zero, a signal can be given to the preset input of a flip-flop is, which is followed by a further flip-flop, the output of which is the clock signal sequence can be inferred, and that the output signal of the first flip-flop is a further counter can be supplied, which can be reset to zero when a signal is received and about a decoder circuit the shifts in the shift registers and along with the output signal of the first flip-flop controls the deletion of that flip-flop, which is connected upstream of the EX-KLUSIV-0DER link.

With this arrangement made up of a few elements, the clock signal sequence synchronized with the received signals in terms of frequency and phase. While the absence of expected signals, the arrangement works with the last synchronized frequency and phase until a new signal is received.

In a further preferred embodiment it is provided that an AND-NOT element to the clear input of the flip-flop connected upstream of the EXCLUSIVE-OR element is connected, whose inputs from the clock signal sequence and from the negated output signal a flip-flop can be acted upon, which can be deleted by a signal from the second counter is, and whose triggering input can be acted upon by counting pulses from a clock generator while the presettable input is connected to an AND-NOT element, whose inputs the clock signal sequence, the inverted output signal one of signals, which can be derived from received signals, retriggerable, monostable multivibrator and the output signal of an EXCLUSIVE-OR gate can be fed to flip-flops connected, which is intended for error correction at the beginning of a transmission are.

This arrangement can be used even if the reception is faulty the preamble, a fixed code sequence at the beginning of a transmission, the errors correct.

Another favorable embodiment is designed such that a retriggerable, monostable multivibrator is provided which is received by Signals can be retriggered, and their non-inverted output signal with the Clear input of a flip-flop is connected, whose preparatory inputs each "0" or t signals can be applied, - while the triggering input is on the second counter is connected, and that the output of the flip-flop is linked with an output signal of the second counter for the presetting of the Down counters controllable flip-flop and a decoder switch mechanism for presetting the further flip-flop is provided.

The arrangement allows it to be switched off if there are no signals for a longer period of time be received.

Another expedient embodiment is that of received Signals derived signals can be fed to the triggering inputs of flip-flops, "L" signals can be applied to the preparatory inputs and the non-inverting ones Outputs are connected to an EXCLUSIVE-OR gate, the output signal of which is a Counting chain triggers, which controls counters, shift registers and switching elements as a master unit.

In the following the invention is illustrated in a drawing with reference to a Aiisfiihrungsbeispiel explained in more detail.

1 is a diagram showing the processing of on a Magnetic tape illustrates data stored, Fig. 2 is a circuit diagram of an arrangement for carrying out the method, Fig. 3 a), b) and c) diagrams of the time course of signals entered in FIG. 2, Fig. 4 is a diagram of the Time course of signals according to FIG. 2 at the beginning of a transmission when they occur of mistakes.

FIG. 5 shows a diagram of the time profile of signals according to FIG. 2 at the beginning of a transmission when errors occur after two correctly received Signals, FIG. 6 shows a diagram of the time profile of signals according to FIG. 2 in the event of incorrect reception of two immediately consecutive signals, FIG. 7 a further diagram of the time course of signals according to FIG. 2 in the event of an error Receipt of two immediately successive signals, Fig. 8 is a diagram of the temporal progression of signals according to FIG. 2 in the event of faulty reception from one two and three successive signals, Fig. 9 is a diagram of the time Course of signals according to FIG. 2 in the event of incorrect reception of three successive ones Signals, FIG. 10 a diagram of the time course of signals according to FIG. 2, which clarifies the synchronization when one signal fails, FIG. 11 a diagram of the time course of signals according to FIG. 2, showing the relationships illustrated with strongly fluctuating period of the received signals.

In Fig. 1, A denotes the track on a magnetic tape. the Track A is divided into trace elements, which are shown in dashed lines in Fig. # 1 Lines can be distinguished from one another. The river change in the middle of a Trace element is assigned to a binary character. With successive same Binary characters occur additional changes of flow at the borders of the trace elements. The data recorded in track A corresponds to the binary characters 0, L, O, L, O, O, L, L. The type of recording of the data corresponds to the direction clock, which is explained in more detail in DIN 66oil, page 4, from January 1972 under No. 25.

When reading track A, read signals NB, Nz and PB, Pz arise every change of magnetic flux. From two successive river changes that arise in the middle of a trace element, the period 4 of the transmission of the signals N, P determine.

Due to this period, a clock signal sequence K is generated, which is around about arc / 4 is lagging out of phase with the pulses N, P. The impulses NB, PE always coincide with the high level of the K signal. The intermediate pulses Pz, Nz, which go back to a change of flow at the border of a trace element, coincide with a low level of the signal. This way is one Differentiation of the type of impulses given, which is taken into account in the correction of errors can be. The synchronization in terms of phase and period between the signals PB, NB and the signal K takes place in that after receiving a pulse PB or N B another quarter of the time interval between two successive ones Pulses PB, NB calculated period # elapses until the signal K is at the low level transforms. When an intermediate pulse Pzl NZ is received, a quarter of the calculated one runs Period ## until the signal K rises to the high level. The synchronization thus takes place immediately after the result of the calculation is available.

As a result of the synchronization, additional information is available in each case an indication of the half-periods of the signal K is available. That is already given the possibility of receiving a message to be expected according to the directional clock Check signal P or N. If at a high level of K after a half-period has elapsed of the signal K no reception of a signal PB or NB has been registered, an Correction. Since the polarity of each received signal PB or NB is monitored and stored can be expected in the absence of one due to the directional clock Signal a corresponding binary character can be generated. The output of the information takes place one period after the receipt of the respective signal PB or NB. How out 1, the signal course of I corresponds to the binary characters 0, L, O, L, O, O, L.

The period of the signal K is determined by counting Pulses between two signals PB and NB. At the beginning of a transmission, a fixed predetermined count is assumed, which is already after the first two received signals can be corrected. A correction in the event of faulty reception at the beginning of a transmission is possible due to the fact that a certain Code sequence of signals is transmitted, which start with the binary characters 0, L, Will first noticed a signal NB, then -can in the absence of the following signal PB a correction will take place. However, if a signal PB occurs first, then becomes: always a logic 0 is output and a period of the signal K later a logic L, The positive and negative signals PB, Pz and NB, Nz when reading the track of a Magnetic tapes are produced, are converted into unipolar signals and via not shown Read amplifier and pulse shaping stages i, 2, which in the circuit according to FIG are shown, separated the set or reset input one of two cross-coupled OR-NOT gates 3, 4 supplied to existing bistable flip-flop. As pulse shaper stages 1, 2, for example, those on page 34 of the "TTL Integrated Circuits, Condensed Catalogtf from April 1971 from Texas Instruments described Schmitt trigger used will.

The signals at the inputs of pulse shaping stages 1 and 2 are in Figures 2 and 3 labeled POS and NEG. Here POS means a signal, on a positive magnetic flux change in the Track A is based, in a corresponding manner, the signal NEG goes to a negative going magnetic flux change in track A back.

The outputs of the pulse preregistration stages 1, 2 are still the triggering ones Inputs of D flip-flops 5, 6 connected, their preparatory inputs with a Voltage assigned to a logical L can be applied. As a D flip-flop can be found in the above-mentioned catalog from Texas Instruments on page 75 Use the elements shown under the type designation SN7474.

The non-inverting outputs of the flip-flops 5, 6 are at inputs an EXCLUSIVE-OR gate 7 connected, which emits an output signal DA. Further there is a connection between the non-inverting output of flip-flop 6 and an input of a retriggerable monostable multivibrator 8, as it is e.g.

in the above catalog on page 33 under the designation So74123 is specified.

The output of the EXCLUSIVE-OR gate 7 is with the preparatory Connected to the input of a D flip-flop 9, the first stage of one of the other D flip-flops 10, 11, 12, 13, 14, 15 and 16 existing tail units. The connection was made in the Fig. 2 indicated that sorohl at the output of the EXCLUSIVE-OR gate 7 as the signal designation DA was also entered at the input of the flip-flop 9. The Arit the illustration was, as can be seen from FIG. 2, also for further connections chosen to improve clarity. The non-inverting exit of flip-flop 9 feeds the preparatory input of flip-flop 10. In the same way is the non-inverting output of the flip-flops 101 11, 12, 13, 14, 15 one with the preparatory receipt of the one marked with the next higher number Flip-flop connected. As D flip-flops 9q 11, 13, 15 and 10, 12, 14, 16 can be two which are explained in the above catalog under the designation So 74175 on page 48 Arrangements are used.

A pulse generator 17, the two mutually complementary signals ZCP and ZCP emits, its non-inverting output corresponds to the triggering one Inputs of the flip-flops 9, 11, 13, 15 and with its inverting output with the triggering inputs of the flip-flops 10, 12, 14 and 16 in connection. They don't inverting outputs of the flip-flops 9 to 16 deliver the signals CIQ, C2Q, C3Q, C4Q, C5Q, C6Q and C8Q.

The output of the OR-NOT gate 4, at which a signal SP is available is to an input of an AND-NOT gate 18 and an EXCLUSIVE-OR gate 19, the output of which is connected to the preparatory input of a D flip-flop 20 is performed, at its non-inverting output in accordance with the Binary characters taken from track A of a magnetic tape are logical "O" or 1, L "signals be available. The D-Fli'pflop 20 can be one of the above under the type designation SN 7474N consist of the elements mentioned. The triggering # input of the D flip-flop 20 is fed with the signal TQ of the non-inverting output of a J-K-MS flip-flop 21, its two preparatory inputs from a signal assigned to the logical "L" be applied. For a J-K-MS flip-flop, the above catalog can be found on Type SN 7476N specified on page 75 can be used. The triggering input of the D flip-flop 21 is fed with a signal LX of the output of an AND-NOT gate 22, the Input is connected to the inverting output of a D flip-flop 23, the emits a signal LX. The triggering input of the D flip-flop 23 is connected to the inverting one The output of the clock generator 17 is connected, while the preparatory input is acted upon by a voltage assigned to the logic "ott. The D-Fli # flop 23 can e.g. all of the above catalog on page 75 under the type SN 7474 specified arrangement exist. The preset input of the D flip-flop 23 is with connected to an AND-NOT element 24, the inputs of which are connected to AND-NOT elements 25, 26 are connected.

One input of the AND-NOT element 26 is fed by a signal S, which is present at the inverting output of a J-K-MS-Plipflop 27, like the one above mentioned flip-flop 21 can consist of the type SN 7476N. The J input of the flip-flop 27 is from one of the logical "L" and the K input from one of the logical "0" assigned voltage applied.

The triggering input of the flip-flop 27, the second input of the AND-NOT element 26, an input of your further AND-NOT gate 28, an input of an AND-OR-NOT gate 30, an input of a further AND-OR-NOT gate 31 and an input of an AND-NOT gate 32 are fed from the third output 34 of a 4-bit binary counter 35. The exit 34 of the binary counter 35 supplies a signal C, while at the first output 36 and at second output 37 the signals A and B are available. The fourth Output 33 of binary counter 35 is not used, corresponding to binary counter 35 Circuits are on page in the above catalog. 20- under the designation SN7493N described.

The triggering input IA of the binary counter 35 is to the AND-NOT element 22- connected. The outputs 36 and 34 feed an EXCLUSIVE-OR gate 38, the with the second input of an input of an AND element of the AND-OR-NOT element 30 is connected. The inputs of the second AND element of this AND-OR-NOT element 30 are led to the outputs 36, 37 ~. There is also a connection between the output 37 and the second input of the OR-NOT gate 29, which is connected to an AND-NOT gate. 39 is connected, the other inputs from the output 36 and the non-inverting Output of the flip-flop 12 are fed.

The output of the AND-OR-NOT gate 30 is an input of one AND-NOT gate 40 out, whose second input to the non-inverting Output of the flip-flop 10 is in communication.

The AND-NOT gates 39, 40 are at inputs of an AND-NOT gate 41 connected, the third input of which is acted upon by a signal m that is output from the inverting output of the flip-flop 16.

Two inputs of the one upstream AND element of the AND-OR-NOT element 31 are connected to the outputs 36, 37. The second input of the further upstream AND gate of AND-OR-NOT gate 31 is connected to an EXCLUSIVE-OR gate 42.

The AND-OR-NOT gate 31 feeds a NOT gate 43, which is with a AND-NOT gate 44 is connected, the second input to the non-inverting Output of the flip-flop 12 is connected. The AND-NOT elements 40, 44 are with an AND-NOT gate 45 connected. The AND-NOT gates 41, 45 give their Outputs signals Si and SO.

The exits. the AND-NOT gates 41, 45 have control inputs connected by three shift registers 46, 47, 48, their triggering inputs from the non-inverting Output of the clock generator 17 are fed. The im The above-mentioned catalog on page 6i under the designation SN74I9iN specified circuit arrangements whose control inputs have the designations S1 and SO. One shift register each 0 46, 47, 48 is with its outputs on inputs of a presettable counter 4% 50 51 led. Such meters can be found in the above-mentioned catalog on page 60 mentioned under the designation SN7i193.

The left shift control input of shift register 48 is charged with a voltage assigned to the logic "L" The control input for the right shift of the shift register 48 stands with the output for the lowest value at the shift register 47 in connection. From the exit for the The highest priority on shift register 48 is a line to the control input for left shift ram shift register 47. Between the control inputs for left or, right shift and the outputs at the shift registers 46, 47 is one to the shift registers 47 and 48 similar connection established. Of the Stewar entrance for the shift to the right at the shift register 46, wan becomes a logical occurs associated voltage is applied.

The input for counting up on the counter 51 is one of the logical "L" assigned voltage is supplied while the input for down counting is on the non-inverting output of the clock generator 17 is connected. The exit forward of counter 51 is connected to the forward counting input of counter 50. The down output of the counter 51 is connected to the down counter input of the counter 50 connected. The counter inputs and outputs are similar the counters 49 and 50 are interconnected. From the counter output backwards 49, which emits a signal BOR, leads a line to the input of the AND-NOT element 25th

The set inputs of the last two links in the chain of the shift register 48 are connected to outputs with the two highest values of a counter 52, which corresponds to the counters 49 to 51 in structure. The outputs with the two lowest Significant values are not used for counter 52. In the same way as with the counters 50, 51 exist between the outputs forwards or backwards and the inputs Counting forward or counting backward of the counter 52 and another similar one Counter 53 connections between each other. The two least significant outputs at the counter 53 feed the set inputs of the links at the beginning of the chain of the shift register 48.

The outputs with the two highest priority values on counter 53 are connected to set inputs of the links at the end of the chain of the shift register 47. The counter input from the counter 52 is connected to the non-inverting output of the Clock generator 17 connected, while the count input backwards from one of the logical "L" assigned signal is built; fschla # gt.

Furthermore, a counter 54 is provided, the circuit of which corresponds to that the # counters 49 to 53 match. The counting inputs are upward or downward at the counter 54 with the outputs forwards or backwards at the counter 53 in one at the other counters 49 to 52 already explained type connected.

The set inputs of the first two links in the chain of the shift register 47 stand with the outputs for the two lowest place values on counter 54 in connection. The two outputs with the highest value of the counter 54 feed the two set inputs of the links at the end of the chain of the shift register 46, whose links are at the beginning of the chain by applying one of the logical ttO7t assigned voltage can be preset.

All preset inputs of the counters 52 and 54 are connected to one of the voltage assigned to logical XO. The preset inputs are received at the counter 53 for the two lowest values and the preset input for the highest Significance is supplied to a voltage assigned to the logic "0", during the Preset input with the third highest priority in front of a logical "L" assigned voltage is applied.

The shift registers 46 to 48 take over at their set inputs pending information when both control inputs S and S1 carry 2tLtt signals. With ~ L "signal at input S1 and ItOt signal at input SO, there is a right shift of the In-0 takes place, i.e. a division by the factor 2 for each period of the Signal sequence ZCP. If there is a "0" signal at input S1 and ~ L "signal at input SO, then there is a left shift 0 of the content, i.e. in each period of the clock signal sequence ZCP a multiplication by the factor 2. If both inputs SO, S carry "O" signals, then the shift registers 46 to 48 are blocked for the signals ZCP.

The presetting inputs of the counters kot 50, 51 are controlled by a signal Z2 acted upon, which is delivered by an OR-NOT gate 55, one of which Input to the AND-NOT gate 22 and its second input to the non-inverting Output of the flip-flop 14 are connected. The preset inputs of the counter 52, 53t 54 are connected to a NOT element ^ 56 56, which is controlled by a retriggerable, monostable flip-flop 57 is fed, which is constructed in the same way as the flip-flop 8. The clear inputs of the counters 49, 50, 5i are from the inverting output of the Flip-flop 57 fed, which emits a signal FQ #. The clear inputs of the counter 52, 53, 54 are connected to the non-inverting output of the flip-flop 12. The inputs of the flip-flop 57 are each connected to a voltage source supplying the logic 0 and the inverting output of the flip-flop 13 £ t puts, which emits a signal C56. The non-inverting output of the flip-flop 57 with a signal FQ feeds one Input of flip-flop 8. The clear input of flip-flop 57 is activated with an ~ L "signal applied. The output of the OR-NOT gate 29 is connected to the clear input of the flip-flop 8 connected.

The NOT element 56 is with the clear inputs of the flip-flops 21, 27 tied together. The AND-NOT gate 28 feeds the clear input of a D flip-flop 58, the is constructed in the same way as the flip-flops 5 and 6. The non-inverting one The output of the Flip # -flop 58 is connected to the second input of the EXCLUSIVE-OR # GlIeds 19 connected, this output emits a signal KQ. At the preparatory entrance, of the flip-flop 58 is a signal TQ of the inverting output of the flip-flop 21 on, The triggering input of the flip-flop 58 is connected to the inverting output of the Flip-flop 16 connected, which supplies a signal f.

There is also a connection between the preset input of the Flip-flop 58 and an AND-NOT gate 59, whose inputs are connected to the non-inverting Output of flip-flop 21 and to the inverting output of another D flip-flop 60 are connected, which emits a signal RDQ, the clear input of the flip-flop 60 is led to the output of the UNfl-NOT member 32, whose signal 5 of the inverting output of flip-flop 27 is applied to the second input will.

The triggering input of the flip-flop Go is with the non-inverting # den Output of the clock generator 17 in connection. The preparatory input of the flip-flop Go becomes an AND-NOT element via an unspecified NOT element 61 fed, the inputs of which to the EXCLUSIVE-OR gate 42, which emits a signal G, the non-inverting output of the flip-flop 21 and the inverting output of the Flip-flop 8 are connected.

The inputs of the EXCLUSIVE-OR gate42 are non-inverting Outputs of J-K-MS flip-flops 62, 63 in connection, the structure of which the flip-flops 21, 27 corresponds. The J input of flip-flop 62 and the input of flip-flop 63 are acted upon by a voltage assigned to the logic "o". At the K entrance of the flip-flop 62 and at the input of the flip-flop 63 is a logic "L" assigned Voltage on. The triggering inputs of both flip-flops 62, 63 are from an OR-NOT gate 64 fed whose inputs to the inverting outputs of the flip-flops 23 and 27 are connected.

The preset input of the flip-flop 62 is with the AND-NOT gate i8 connected, its second and third input to the inverting output of the flip-flop 27 and the output of an AND-NOT gate 65 are performed. There are further connections zzlschen the inputs of the AND-NOT gate 65 and the inverting Outputs of the flip-flops 10 and i6, which emit signals C2Q and C 8Q. The AND-NOT element 65 feeds one input of an AND-NOT element 66, the other inputs of which are connected to the inverting output of the flip-flop 27 and the output of the OR-NOT gate 8 3 connected are. The output of the AND-NOT gate 66 is connected to the preset input of the flip-flop 63 connected. There are also connections between the extinguishing inputs the Flip-flops 62, 63 and the non-inverting output of flip-flop 57.

The clear inputs of flip-flops 5 and 6 are on the inverting ones Connected to the output of the flip-flop 10, which supplies a signal C2Q. The non-invasive one The output of the trigger stage 57 is also led to an input of an AND-NOT stage 67, whose second input is fed by the inverting output of the flip-flop 15 ', which emits a signal C7Q. bas AND NOT element 67 is connected to the reset inputs of the Counter 35 connected, its output 36 to the input iB and its input So that the non-inverting output of the flip-flop 23 is connected. The tilting stage 57 continues to feed the clear input of flip-flop 20 with its output signal FQ.

Another binary counter 68 is connected to the 'counting input' ## l with two AND-NOT gates 69, 70 connected, each of which has an input to the non-inverting Output of flip-flop i4 is connected.

The AND-NOT gate 69, which feeds the counting input forward, is connected with the output of the OR-NOT gate 3. The output of the OR-NOT gate 4 is to the second input of the AND4NOT element that feeds the counter input backwards 70 led. The preset inputs of counter 68 are given the value ~ 2 ".

At the delete input, the inverting output is the retriggerable one monostable multivibrator 57 connected. The output of the counter 68 with the place value two are fed back to the preset input via an OR-NOT gate 71. An AND # NOT element 72 is connected to the second input of the OR-NOT element 71, which is preceded by an AND-NOT gate 73, whose inputs to the non-inverting Outputs of the flip-flops 58 and 21 is connected. Another input of the AND NOT element 72 is connected to the output of the OR-NOT gate 64. The counter 68 can be constructed in the same way as counters 52 to 54.

The signals shown in Figures 1 and 3 to 11 can Accept levels assigned to logic constants ot or «tL". A logic "O" a low level and a high level is assigned to a logical tZLs'. The logical one In FIGS. 1 and 3 to 11, ~ 0 "corresponds to one shown in part by dashed lines Line. The logical "L" is indicated by one above the dashed lines solid line shown.

In the following discussion, the leading edge of a signal the transition from a low to a high level and, on the trailing edge, the change understood from high to low level.

According to FIG. 3a, the signal POS changes from one at a time t1 high to low while the signal NEG maintains its high level. As a result, the signal SP rises to the high level. With the trailing edge of the signal POS becomes the ~ L "signal pending at the preparatory input of flip-flop 5 transmit non-inverting output. This means that via the EXCLUSIVE-OR element7ein Signal DA high to flip-flop 9.

With the after the rise of the signal DA to the high level first Occurring leading edge of the signal ZCP appears at the non-inverting output of the flip-flop 9 has a logic "L".

The next following leading edge of the ZCP signal causes the takeover a logical "L" in the flip-flop 10. The signal C2Q changes from high to the low level and clears the flip-flop 5. The signal DA goes up again return to the low level. After the fall of the DA signal, the C1Q signal decreases with the next leading edge of the signal ZCP to a low level. Simultaneously Because of the high level of C2Q, a logic 'L' enters flip-flop 11. From this it can be seen that the signals DA and C1Q for the duration of a period of the signal ZCP lead a high level.

As explained in connection with the flip-flops 9 and 11, arise in the same way at the non-inverting outputs of the flip-flops 11, 12, 13., 14, 15 and 16 through the clocking device with the signals ZCP signals one after the other with the signal level assigned to a logic "L'i". These "L" signals are mutually exclusive are each phase shifted by half a period of the signal ZCP, last one Period from ZCP on.

The diagrams shown in Fig. 3a are based on the assumption that there on the trailing edge of POS by the first on the magnetic tape after the start of the transfer removed signal change.

With this assumption, the content is in the counters 49, 50, 51 zero. The lower counting limit of the counter 49 is therefore in each period of the signal ZCP undershot. Therefore occur with the trailing edges of the signal ZCP at the output backwards of the counter 49 brief pulses of the signal BOR, which have a low Have signal level. The flip-flop is on for the duration of these pulses. 23 the default setting ineffective. The output signal LX of the flip-flop 23 therefore shows only short, against the low signal level directional pulses emanating from the leading edges of the signal ZCP can be generated. The signal LX then rises as a result of the presetting of the flip-flop 23 to the high level again.

The brief pulses in the LX signal call via the OR-NOT element 55 pulses of the signal Z2 with reversed polarity emerge.

At the same time as the signal C2Q, the signals SO, S1 and G lead a signal level associated with a logic "L". Because the signal FQ during this time has the low level, the counters 52, 53, 54 take them at the preset inputs given numbers. With the transition of the signals SO, S1 to the high level the number present in counters 52, 53, 54 goes to shift registers 46, 47, 48 over. After both signals SO ,, S1 back to the low Levels have decreased, the shift registers 46, 47, 48 for the signals ZCP blocked.

With the signal C4Q the content of the counter. 52, 53, 54 subsequently cleared, The leading edge of the C5Q signal generates the rise of the FQ signal the high level. A half cycle of the signal ZCP later, the signal C8Q rise and the signal Si goes high.

At the same time, the trailing edge of signal C6Q causes the to rise Signal Z2 to the high level. The contents of the shift registers 46, 47, 48 arrive at the same time in the counters 49, 50, 51 and is then shifted one place to the left. With the next leading edge of the signal following the rise of the FQ signal ZCP is the pending logic "O" at the preparatory input in flip-flop 23 accepted. The signal LX thereby falls to the low level. At the same time causes the fall of the signal x to the low level via the AND-NOT gates 65 and 66 a presetting of the flip-flop 62, which sends a signal to the EXCLUSIY-OR gate 42 feeds. The signal G rises to the high level.

With the trailing edge of the LX signal, an "L!" Signal reaches the flip-flop 21, the output signal TQ of which rises to the high level.

The signal at the output of the multivibrator 57, which is labeled FQ, goes high when the signal C5Q goes high. Of the The rise of the signal FQ causes the inverting output of the flip-flop 8 to be low Level. Once the G and TQ signals have reached their high levels, will at the output of the AND-NOT gate 61, the low level is generated because the flip-flop 8 is high at the inverting output at this point in time. On the preparatory As a result, the input of the flip-flop 60 reaches the high level. With the next one On the leading edge of the ZCP signal, the flip-flop 60 takes on a logic "L. This the signal RDQ rises to the high level. By the leading edge of the signal 5, the signal KQ is set to the low level because it is at the preparatory input of the flip-flop 58 at this point in time a logical "o" is present. Since during the rise of the signal TQ at the two inputs of the EXKLUSIY-OR element The preparatory input receives 19 signals SP, TQ with similar levels of the flip-flop 20 is supplied with a logic 0, which is stored the signal I the level assigned to a logic ~, # ~.

Signal Z2 rises with the trailing edges of signals LX and C66 the high level. As a result, the counters 49, 50, 51 are switched over to counting down. The content of the counters 49, 50, 51 is decreased in time with the signal ZCP. If the Counting zero is reached with the next period of the signal ZCP a pulse in the signal curve of BOR, which briefly the level of the signal BOR humiliated. According to Figure 3a, this pulse occurs at time t2 and causes a Presetting of the flip-flop 23, whose output signal LX rises to the high level, until the next leading edge of the signal ZCP, the signal LX to the low Brings back level. The trailing edge of the LX signal causes a change in level of the signal TQ and thus the storage of a bit in the counter 35. The signal TQ falls to the low level, while the signal A assumes the high level.

While the signal Z2 has the low level, that in the shift registers 46 to 1 + 8 stored number, which is now due to the shift to the left that has occurred once is twice as large as the number given to the counters 52 to 54 in the counters 49 to 51 transferred. One half cycle of the ZCP signal after the signal has fallen TQ, the signal RDQ also goes back to the low signal level, since the output of the AND-NOT gate 6i carries an "O" signal at this point in time.

The trailing edges of the signal following the rise of signal Z2 ZCP reduce the count in counters 49 to 51, until the Content zero is reached. After that, the next time the signal changes level ZCP a pulse in the signal curve at time t3 due to the overflow of counter 49 from BOR. With regard to the signal curve of LX and Z2, the same processes that have already been described above in connection with time t2 became. With the trailing edge of the signal LX, the signal TQ rises to the high level at. At the same time, a second bit is input to the counter 35, which is a low Level of signal A and a high level of signal B causes. During the first half-period of the signal ZCP following the rise of the signal TQ prevail at the inputs of the AND-NOT gate 59 high level, via which the flip-flop 58 is preset will. The flip-flop 58 therefore takes on the non-inverse.

output to the high level. With the high level of the signal KQ lie at the EXCLUSIVE-OR gate 19, a high and a low level, so that this supplies a high level to the flip-flop 20, the output signal I of which with the The leading edge of the signal KQ takes over the high level.

Between the change of the signal assigned to a logical "L" POS and the rise of the signal I from a logical "O" to a logical "L" a phase shift of approximately one period of the signal TQ occurs.

Since the counter 49 to 51 after the fall of the signal Z2 again with the number stored in shift registers 46 to 48 are preset, after the rise of the signal Z2, a downward counting takes place through the clocks of the Signal ZCP until, after reaching the count zero *, another pulse of the The BOR signal arises. This low level pulse triggers on the signals LX, TQ, RDQ and Z2 have the same effects from those above in connection with the timing t2 were described.

By changing the signal LX in the counter 35 is another Bit entered. Signal A therefore rises to the high * at time t Level. The signals B, G, KQ and I keep their levels.

After the content of the counter 49 has returned to zero, occurs at time t5 in the signal BOR again a pulse that. regarding the signals TQ and Z2 trigger the processes already explained above for time T3. With the trailing edge of the signal LX, the signals A and B are at the low signal level is brought back while the signal C becomes the high signal level. The rise of the signal C at the high level causes the flip-flop 60 to be cleared, so that the Signal RDQ maintains the low level. Since both the signal SP and the signal KQ lead high levels, a logical "~" is generated with the leading edge of the signal TQ taken into the flip-flop 20, the a fall of the signal I to a logical ~ 0 "results in the signal level assigned to it. The signal I therefore changes after it has elapsed a period of the signals TQ from a logic "L" to a logic t'O ".

At time t6, the signal NEG changes level. The signal SP thereby goes from high to low level. As in connection with the Change of signal SP at time tl 1 described, changes occur thereafter- of the signals DA and C1Q to C8Q. When both signals SO, S1 are high, the number in counters 52 to 54 is transferred to shift registers 46 to 48. Simultaneously with the rise of the signal C26 to the high level, the flip-flop becomes 63 preset.

The signal G therefore falls to the low level. With the fall of the Signal C4Q at the low level, the contents of the counters 52 to 54 are cleared. While signal C66 is high, signal Z2 goes low Level back.

The number present in the shift registers 46 to 48 is then used into counters 49 to 51. With the leading edge of signal C7Q, the signal FQ has the high level, the counter 35 is cleared, i.e. the signal C changes to low level above.

The, trailing edge of the signal C causes the signal S to rise the high level. The signal KQ goes to the leading edge of the signal C86 low level. While the signal S1 together with the signal C8Q the high Leads level, the low level of the signal SO does not change. In the shift registers 46 to 48 finds a left shift of the content by one place, i.e. a multiplication with a factor of 2.

In Fig. 3b is that which occurs after the time t6 Signal curve shown. at time t7 an overflow signal BOR arises as short impulse. Thereafter, the signal LX goes high for one period of the signal ZCP Level and the signal Z2 the low level. With the trailing edge of the LX signal the signal TQ goes back to the low level, while the signals A and G go up increase the high level.

At time t8, a brief pulse occurs again in the signal curve from BOR to. With regard to the signals LX and Z2, the is already connected with the times t2 to t7 mentioned signal curve. With the trailing edge of the At the signal LX, the signals TQ, B and KQ rise to the high level. Simultaneously the signal A falls to the low level. A half cycle of the ZCP signal later the signal RDQ also rises to the high level. The signal I keeps the low Level at.

Between the point in time t8 and a point in time tg would have to be due to the Directional clock font a change in the signal level of POS may occur. Suppose that as a result of incorrect reading such a change is not detected. To the Time tg in turn creates a pulse in the signal curve of BOR, which with respect to the signals LX and Z2 triggers the effects already mentioned above. With the back flank of the signal LX, the signal TQ falls to the low level, while the signal A goes high. The other signals B, C, S, G, KQ and I do not change.

A new pulse in the signal curve of BOR arises at time t The signals LX and Z2 then take their levels explained in detail above at. Signals TQ, C and I go high, while signals A and B fall to the low level. The signal RDQ has after a half period of the Signal ZCP the high ~ level.

At time t11, there is a new change in signal NEG.

This change calls a signal DA and signals C1Q to £ 8Q inder Connection with the time t1 described type emerges. The signals S1 and SO lead to the high level with the signal C2Q. Remains during the high level of C4Q the high level of the signal SO obtained. The signal S1 at this time has a low level. This causes a shift in the shift registers 46 to 48 of the content to the right by one place, i.e. a division by a factor of 2. Da through the failure of a change in the POS signal counters 52 to 54 double the number Pulses counted as with properly successive signal changes of POS and NEG, the period ~ of this signal change is corrected by the division and thus also a synchronization established. With the trailing edge of the signal C7Q the counter 35 is cleared. This also causes signal C to go low Level back. While the signal C6Q is high, the signal is conducting Z2 the low level. At the same time, the number arrives in shift registers 46 to 48 in counters 49 to 51. With the leading edge of signal 5, a logic "O" into flip-flop 58, signal KQ going back to the low level.

At time t12, there is a change in the level of signal POS. At this time, the signal SP rises to the high level. The clock signals are then generated C1Q to C8Q. It is assumed that a signal change from NEG not recognized became. Therefore, the signal C leads at the same time with the signal C4Q the high level. The signal SO also takes the high level on while the signal S1 is low. During this time the number becomes shifted one place to the right in the shift registers 46 to 48, i.e. es division by a factor of 2 takes place. The counter 35 is cleared with the leading edge of the signal C7Q. The other signals keep their levels up to on the signal KQ, which with the leading edge of the signal C8Q to the low Level back

At time t13, a appears as an overflow signal from counter 69 short pulse in the signal curve of BOR. They already follow this impulse several times mentioned changes in signals LX and Z2. Goes with the trailing edge of the LX signal the signal TQ returns to the low level. A half cycle of the ZCP signal later the signal RDQ also assumes the low level.

Signal A rises high on the trailing edge of signal LX Level on. All other signals POS, NEG, SP, DA, C1Q to C8Q, S1, SO, FX, BC, S, G, KQ and I keep their levels.

Close to the next overflow signal from counter 9 at time t14 the changes in signal level LX and Z2 described above. During the signal A goes back low on the trailing edge of the LX signal the signals TQ, B, KQ and I are high. The signal RDQ rises a half cycle from ZCP to the signal TQ to the high level. All other signals change not.

The next overflow signal from counter 49 occurs at time t15 on. The impulse in the signal curve of BOR gives the signals LX and Z2 the already explained effects. During the signal TQ llnd a half cycle of ZCP later, when the signal RDQ goes low, the signal A rises on the high level. In the -15 following time t lead the time segment the signals A and B, 'the levels associated with a logic Lt, i.e. the binary counter 35 contains the number 3. Since the counting of the half-cycles of the signal TQ with the value Zero starts, this means that after the level change from POS at time t12 three half-periods of TQ have passed.

With each subsequent pulse in the BOR signal curve, e.g. at the times t16 and t17 become the content of the counter 35 µm; one increased. Accordingly arise logical "O" or ~ L "signals at the outputs 36, 37, 34. One period of the signal ZCP later than at time t16, the signal I goes to the one # he logical "O" assigned level. The signal KQ falls to the low at time t17 Level down.

At time t18, there is a level change in signal NEG, which is accompanied by meets a low level of the signal TQ.

This level change indicates an intermediate pulse Nz that arises when two identical binary characters follow one another.

This has an effect on the sequence of signals SP, DA and C1Q to C8Q but not deviating from the relationships set out above. These signals show the same course as explained in connection with time t11. The content of the counter at time t18, a binary five, shows that the one before The intermediate pulse is not recognized by the circuit shown in FIG. 2 became. The high level of signals A and C prevents that for the duration of the signal C26 high levels appear at the outputs of the AND-NOT gates 41, 45. Therefore no number is transferred from counters 52 to 54 to shift registers 46 to 48. As long as the signal C4Q has the high level, occurs at the output of the AND-NOT gate 45 a high level of SO, which is a division of the number in the shift registers 46 to 48 means by the factor 2. Since then the signal S1 the high Level, division is repeated by multiplying by a factor of 2 reversed. Counter 35 is cleared with the trailing edge of signal C7Q, so that the signals A and C go low. The signal KQ rises with it the leading edge of the signal CBQ goes high.

At time t19, the first pulse appears in the signal curve from BOR after the level change from NEG. The signals LX and Z2 change in the process type mentioned above. With the trailing edge of the signal LX, the signals TQ, A rise and I to the high level. The RDQ signal follows a half cycle from ZCP later.

The other signals do not change.

The level change of the signal NEG is concluded at time t20 a level change of the signal POS. The signal SP takes on the high again Level on. The signals DA and CIQ to C8Q join in the one already explained above Way on. Since the signals B and G are the low level and the signal A is the high level Level, the two signals are generated for the duration of the 'L' signal from C26 S1 and SO with high levels. As a result, the contents of the counters 52 to 54 reach the Shift registers 46 to 48.

The signal St remains high for the duration of the ~ L11 signal from C4Q Level at, while the signal SO has the low level.

This means a multiplication of the contents of the shift registers 46 to 48 with a factor of 2. When transferring the content of counters 52 to 54 a division by the factor 4 takes place in the shift registers 46 to 48. The shift registers 46 to 48 therefore contain a value that is a quarter of the time interval between two successive level changes assigned to a binary character which corresponds to the signal POS or NEG.

Since by an intermediate pulse Zz, Pz in the counters 52 to 54 only half of the pulses are summed up, the distance between two binary characters must be associated level changes, according to value can be calculated by the content the shift register 46 to 48 multiplied by a factor of two will. The multiplication takes place by means of the signal 51. during the signal C8Q leads the high level. Furthermore, the signal Å increases with the trailing edge of the signal C7Q shows the low level. The signal KQ goes with the trailing edge of the signal m to the low level.

At time t21, after the level change from POS, the first appears Impulse in the signal curve of BOR. This impulse already creates you at the point in time t20 detailed curve of the signals LX and Z2 with the trailing edge of the signal LX takes the signal TQ and a half period of ZCP later takes the signal RDQ to the low level. The signal A rises with the trailing edge of LX to the high level on The other signals retain their level.

The period of the signal ZCP is smaller than the time interval between two successive level changes of the signals POS or NEG. In the FIGS. 3a to 3c show the signals DA with their entire duration. In the figures to 11, the signals DA are only represented by pulses Direction of the flux change of a signal read from the magnetic tape which is a signal DA is caused by a P or NT to the side of the momentum of DA in the figures 4 to 11 indicated. Here P means a positive and N a negative flow change #. If a signal is received at a time specified by the directional clock from the circuit according to FIG. 2 is not recognized, a corresponding signal DA is dashed registered.

After each impulse from DA, those relating to signals C1Q to run C8Q, S1, SO, LX, BOR, S, G and Z 2 shown in Figures 3a to 3c, Yorgange away. These signals were therefore not included in the figures. until 11. the Figures 11 through 11 show those for understanding error correction and synchronization important Signals SP, DA, TQ, A, -B; C, KQ, I, RDQ. Because the time between two consecutive Signals DA is large compared to the periods of ZCP, the in Figures 3a to 3c illustrated clock signals CZQ to C8Q and the signals derived therefrom expire without difficulty.

4 shows the situation at the beginning of a transmission. This beginning is determined by a code number, which consists of the binary characters "O, L, 0, L, O, L ". According to FIG. 4, the first binary character already has one logical "0", an erroneous reception, because the first negative Signal DA / N associated with a flow change is not determined at time t22. To the A signal DA / P is recognized at time t23.

As a result, the signals TQ and KQ rise to high by time t24 Level on. The time t24 is determined by the overflow of the counter 49. There in If only a small number was entered in the counters 52 to 54, t24 is ~ close to t23. At time t24, the signals TQ and RDQ go back to the low level, while the signal A rises to the high level. After each overflow of the counter 49 is a new value from the shift registers 46 to 48 is entered into the counters 49 to 51. Compared to the value entered in counters 49 to 51 after time t23 the value entered after time t24 due to the shift to the left larger in the shift registers 49 to 51.

The time between t and t24 is therefore less than the time 23 between t24 and the time t25 at which a new overflow of the counter 49 takes place. At time t25, signals 25 TQ, B, RDQ, KQ and I assume the high level, while the signal A- falls back to the low level. By the time t led 25, the signal I is the level assigned to a logic "O". This corresponds to the Binary digit dead at the beginning of the transmission. Then the signal I goes to Level of a logical "Lt ' over that is transmitted as the second binary digit will. -Despite incorrect transmission ~ the binary digits are output correctly.

The next time the counter 49 overflows, the Transition of signals TQ and C to the high level takes place. The signals A, B and I. fall to the low level.

At the time t28, a signal should be given due to the directional clock DA / N occur. However, this signal does not materialize.

The signals TQ, # KQ, A, fl,. #, RDQ and I change at this point in time not.

A signal DA / P appears at time t29. The one between the two Signals DA / P at times t23 and t2 in counters 52 to 54 by pulse counting The resulting number is divided by the factor 4 and stored in the shift register 46 to 48 are entered, in which a further division by the factor 2 takes place. This value then reaches the counters 49 to 51.

After reading out the counters 52 to 54, these are cleared. the The number in the shift registers 46 to 48 is again with the factor after reading out 2 multiplied. Due to the signal DA / P, the counter 35 is also cleared, see above that the signals KQ and C assume the low level. Since the signal TQ still has a leads to a high level, a logic "L" is stored in the flip-flop 60, which causes a signal RDQ of high level.

At time t30, the counter 49 overflows due to the between two signals DA / P counted clocks from ZCP. The signal TQ is noticeable as a result the low level while the signal A rises to the high level. So is already after the first two signals recognized by the circuit according to FIG a synchronization in terms of period and phase between TQ and the received ones Signals established, the signal RDQ goes low with the signal TQ return.

The next overflow of counter 49 occurs at time t31. Included the signals TQ, A, B, KQ, RDQ and I change their levels. After the level change of the Signal I is a logic "L" available at the output of flip-flop 20, which is due to the signal DA / P at time t29. The output of the received Data takes place by means of the circuit according to FIG. 2 with a phase shift of a Period of TQ.

Another signal DA / N should appear at time t.

32 As indicated in Fig. 4, such a signal becomes due to a Error not detected. Keep all TQ, AB, C, KQ, RDQ and I signals therefore their level at time t32.

32 At time t33, a new overflow in counter 49 results in a Level change of the signals TQ and RDQ. A new half-period of the Signals TQ. This half-period ends at time t34 with the next overflow signal from counter 34-49. At this point, signals A, B and I go low Level down while the signals C and RDQ rise to the high level. The edition of a logic L't is ended after one period of the signal TQ. The signal I carries the ~ level assigned to a logical "0". This logical ~ 0 "is the assigned to unrecognized signal DA / N at time t32.

Due to the coding in directional clock script, at time t35 another signal DA / P arise. Assume that this signal is due to an error is not recognized. The signals TQ, A, B, C, KQ, RDQ and I change therefore '^' does not change at time t35.

35 At time t36, an overflow signal from the 4cm counter begins 49 a new half cycle of the signal TQ. The signal Ä ascends the high level, while the signals KQ and RDQ d # en assume the low level.

At time t37, counter 49 emits the next overflow signal. The signals TQ, B, KQ, RDQ and I then go high. The signal A falls to the low level. This makes the output a logical one. ~ 0 "through the flip-flop 20 ends, the 33 signal not generated at time t33 Assumes the "L" level assigned to DA / P.

At time t38 a signal DA / N is produced, which leads to a level change of the signal SP leads. At this point in time, the signals B, C and KQ also change theirs Level. Subsequent to the time t38, the content in the Shift registers 46 to ~ i8 instead. This value is transferred to counters 49 to 51, which emit an overflow signal at time t39, with which a frequency and phase synchronization between the signals DA and TQ is established.

Fig. 5 shows the beginning of a transmission in which already a signal of the circuit according to FIG. 2 is fed to the first binary character. Regarding of the signals DA, TQ, A, B, C, Q, RDQ and I, which are shown in FIGS. 4 to 11 are and the signals C1Q. to C8Q, S1, SO, LX, BOR, S, G and Z 2, which are only in the Figures 3a to 3c apply to the I; ig. 5 and all other figures the statements made in connection with FIG.

At time t0, a signal DA / N occurs, with which the signals SP and KQ are set to the low level. The signals TQ and I rise to the high level. The signal RDQ, the high level of which is the output of the signal I can control stays at the low level. The input becomes through the signal FX of Set value in the counters 52 to 54 caused. This leads to the signals TQ, A, B, C and IÇQ to operations in connection with FIG. 4 for the signal W / P have already been explained in detail at time t23. In contrast to signals 4, the signal I has the high level, while the signal KQ is low. The signal RDQ rises with the signal B to the high Level and falls back to the low level with the leading edge of signal A return. For the duration of the high level of the signal RDQ, the signal I corresponds to one logical ~ 0 "in accordance with the signal DA / N.

At time t41, a signal DA / P appears which indicates a level change of the signal SP causes. Simultaneously-the signals C and KQ are on the low Level set back. The number of clocks added up between the signals DA / N and DA / P from ZCP are used for frequency and phase synchronization of the signal TQ with the signals DA, in which the value in counters 52 to 54, divided by a factor of 4, is about the shift registers 46 to 48 is input to the counters 49 to 51, which at the time t42 emit an overflow signal. With this signal, the TQ signal goes low Level while the signal A rises to the high level.

A new one begins with the next overflow signal at time t43 Half period of the signal TQ, which changes the level of the signals A, B, KQ and RDQ evokes.

Since a signal DA / N does not occur at time t4 due to an error, there is no change in the levels of the signals SP, TQ, A, B, C, KQ, RDQ and I. The signal I corresponds to a logic "L" and can during the high level of RDQ are issued.

Determined by the contents of the shift registers 46 to 48 change after time t in the waveform of TQ low and high Levels periodically from one another, with each half cycle the count of the counter 35 increased by one. Periodically with the signal TQ, nO "and XLt 'signals alternate in the course of 1. At time t45, for example, the signal I goes to the low level back while the signal RDQ rises to the high level. The one represented by signal I. logical ~ 0 "corresponds to the signal DA / N not recognized at time t44.

At time t6, a signal -DA / P should also be output as a result of an error do not occur. One period of the signal TQ after the time t45 increases Signals RDQ and I return to the high level. Accordingly, in the course of I a logical "L" is available, which corresponds to the signal DA / P that was not generated at the time t6 corresponds. The circuit shown in FIG. 2 thus corrects two consecutive ones Failure.

At time t47, a signal DA / N- occurs, which indicates a level change of the signal SP generated. At the same time, the counter 35 is cleared, so that the signals #A, B, C go low. By the signal DA / N at the time As already explained in connection with FIG. 4 at time t40, t47 becomes a Phase synchronization of the signal TQ with the signals DA established. This requires a level change of the signal TQ at time t47. A half cycle of the signal TQ later the signals A, B, KQ, RDQ and I also change levels. The flip-flop 20 a logical "O" can be taken from the signal DA / N to the Time t47 is due.

Since the signal DA / P was not detected at time t49 due to an error , the change 49 of the signal TQ continues periodically after time t, wherein the count of the counter 35 is increased until a signal at time t50 DA / N occurs.

At this point in time, the counter 35 contains the value four. In connection at the point in time t50 becomes the sum of the pulses 50 between the points in time Number corresponding to t47 and t50 divided by the factor 8 from counters 52 to 54 are transferred to the counters 49 to 51 via the shift registers 46 to 8.

Changes with the overflow signal from the counter 49 at time t51 the signal TQ the level. This is a frequency and phase synchronization between the signals DA and TQ produced.

Fig. 6 shows a transmission in which an intermediate pulse DA / P occurs at time t52, which is the flux change between two consecutive corresponds to binary zeros. The intermediate pulse DA / P clears the counter 35, i.e. the signal A goes back to the low level. The signal KQ rises to the high level, since the signal TQ with a clock from ZCP into the memory 58 is adopted. The intermediate pulse DA / P synchronizes the Signals TQ according to frequency and phase with the signal DA. As shown in Fig. 6, At times t and t55, those to be expected according to directional clock 53 occur Signals DA / N and DA / P off. The signal TQ therefore changes with that caused by the intermediate pulse DA / P frequency set at time t52, the half-periods of the signal TQ are continuously monitored by the counter 35. Leads at times t53 and t54 the signal RDQ in each case the high level, while the signal I the low level having. This corresponds to the two consecutive binary zeros.

At the time t55, the content of the counter 35 increases. the value five. The signals RDQ and I go to the high level.

The logic "L" represented by signal I is the undetected Signal DA / P assigned at time t54.

At time t56, a new pulse DA / P appears, which, as already mentioned above, brings about a synchronization of the signals DA and TQ and the counter 35 clears.

Three quarters of a period of the signal TQ later is triggered by the overflow signal of the counter 49 reset the signal I to the low level, while the Signal RDQ rises to the high level The change of signal I from the one logic "L" assigned level to the level assigned to a logic pOn is due to the binary zero1 of which the signal DA / P at time t56 goes out. The signal TQ, whose level changes periodically, whose half-period counts Continuing 35 also requires the correct switching of the level of the signals I, RDQ, although z9 the times t imd t the expected-57 the signals DA / P and DA / N does not arise. The signal I therefore carries the one at time t or t logical "O" or

57 59 level assigned to a logic "L".

The signal DA / P appearing at time t, which reacts to an intermediate pulse # goes back, brings about a phase synchronization of the signals TQ and W. Eine Frequency synchronization takes place with the signal DA / N occurring at time 't60 instead of.

In Fig. 7, as in Fig. 6, the case is initially shown, that the expected signals DA / N and DA / P n # icht on an intermediate pulse DA / P occurrence'. In contrast to FIG. 6, according to FIG. 7, it occurs at time t61 an intermediate pulse DA / N. Up to the point in time t61, those in FIGS. 6 and are correct 7 therefore match the signals shown. At time t61, the signal C goes to low level because the counter 35 is cleared. At the same time, the Division of the contents of the shift registers 46 to 48 initiates phase synchronization, which takes effect with the overflow signal at the output of the counter 49 at time t62 by the signals TQ, A, 'I and RDQ changing their levels.

At time t63, a signal DA / P4 appears as a result of the one level change the signals SP, A and KQ is caused. In response to this signal DA / P, the Contents of the shift registers 46 bis 48 multiplied by a factor of 4, to calculate a value that is half a period of two consecutive Signals DA / P and DA / N not separated by an intermediate pulse or

DA / N and DA / P corresponds. The signal DA / P conducts at time t63 accordingly the frequency and phase synchronization.

Although at time t64 an intermediate pulse DA / N and at the time t65 a signal DA / P fails due to errors, is after every half cycle of TQ the content of the counter 35 is increased by one. -This takes the signal KQ at the time t63 has a low level and at the half-period following the point in time t64 of the signal TQ becomes high. The signal I remains after time 62 the level assigned to the logic "L".

At time t66, an intermediate pulse DA / N, which provides phase synchronization, appears which initiates signals DA and TQ and causes a level change in signals A and B. If the signals DA / P and DA / N then fail at times t67 and t68, changes with the periods of the signal TQ and the increment of the content of the counter 35 nothing. The signal I also keeps d-n corresponding to a logic "L" Level at. With the signal DA / P occurring at time t69, a Frequency and phase synchronization between the signals DA and TQ take place. From the Figures 6 and 7 can be seen that even if two successive failures Signals an error correction takes place.

The diagram shown in FIG. 8 shows a signal at time t DA / P, which effects a frequency and phase synchronization of the signals DA and TQ. At the following times t71, t a signal DA / N and an intermediate pulse occur DA / P off.

72 The signal TQ changes the level periodically and causes the Counter 35 to increase the count at every half cycle. The signal KQ leads to the times t71, t72 the high level. Since the signal SP during this time also has the high level, results in a high level for the signal I, which can be traced back to the signal DA / P at time ~ t70. By the signal DA / N at time t73, signals C and 73 KQ change levels. Simultaneously a frequency and phase synchronization is initiated, which takes place at time t74 takes effect.

Despite a twofold error, the signal I shows the correct course.

Following the signal DA / N at time t, the 73 signals fall DA / P, DA / N and DA / P at times t75, t76 and t77. The signal DA / N to the Time t76 represents an intermediate pulse. The signal I is over the signals However, DA, TQ, A, B, C, KQ and RDQ are corrected so that it is out of phase the signals DA / N, DA / P and DA / N at the times t and t information to be transmitted follows. The 75 intermediate pulse DA / N at time t78 in turn effects phase synchronization of the signals DA and TQ.- If the signal DA / P following this time pulse is missing, then this error is in turn corrected if at time t79 a <signal DA / N occurs. The rig. 8 shows that in addition to the failure of two successive signals DA also the failure of three successive signals by the circuit according to Fig. 2 can be corrected.

FIG. 9 shows a signal DA / P which, at time t80, shows a level change of the signals SP and KQ and a frequency and phase synchronization between DA and TQ at time t81. The according to ': the directional clock the. At times t82 and t83 expected signals fall due to faulty 8? more ridiculous Transmission off. At time t85 a signal DA / P occurs, so that the intermediate pulse DA / N is missing at time t84. Through the periodic sequence of low and high Levels of the signal TQ and the incrementation of the counter 35 per half period of the signal TQ is corrected via the signals SP, KQ and RDQ, the signal I so that one of the Binary characters "O, L, O" and "L" corresponding sequence of levels occurs. If the DA / P signal at time t85 is followed by an intermediate pulse at time t86, then the signal DA / P to be expected at time t87 can be an intermediate pulse DA / N fail at time t88 and a signal DA / P fail at time t89 without the signal level of I changes. The next signal is on at time t Between -90 pulse DA / N effective, which ensures a phase synchronization between TQ and DA causes. From Fig. 9 it can be seen that even with various types of failures three successive signals the error correction of the circuit according to Fig. 2 works flawlessly.

10 is a diagram of the signals SP, DA, TQ, A, B, C, KQ, RDQ and I with strongly fluctuating period of the magnetic tape not shown in detail coming patent signals shown.

At time t a signal DA / P appears, which has a frequency 91 and Phase synchronization between the signals DA and TQ causes. During the signal DA / N fails at time t92, a signal DA / P is generated at time t, where The period 93 has decreased compared to the signal DA / P at time t91. However, the signal DA / P at time t93 still hits with the high level of the signal TQ together. As a result, there is again a frequency and phase synchronization between DA and TQ instead. A further reduction in the period of the signal DA is from the signal DA / P occurring at time t can be seen on a 95 at time t94 expected faulty signal DA / N follows.

The signal DA / P at time t95 also hits the high level of the signal TQ together, so that again a frequency and phase synchronization takes place between TQ and DA. The same applies to the further course of the signals according to FIG. 10.

The signals SP, DA, TQ, A, B, C, KQ, RDQ and I are shown for very strong changes in the periods of the signals DA. the The circuit shown in Fig. 2 can therefore also be used for magnetic tapes whose Drives are subject to fluctuations in speed. In particular, the Accelerating or decelerating the belts for some sections use the recording of information.

The error message occurs via the counter 68, whose output with the Place value two outputs a signal E, which has an "L" signal in the event of an error. Dependent on the count of the counter 68 is increased by one by each signal POS or NEG or humiliated. The signal E goes high when the count two is reached or when a counting pulse is subtracted from the count zero. This applies to two successive signals POS or NEG. With two consecutive However, there is an error with the POS or NEG signals due to the directional clock Reception before. The output signal E is retained by using the OR-NOT element 71 the counter 68 is preset with the predetermined number.

The error message appears with the first one to be guessed after the failure of one Received signal.

If a signal associated with a binary character is not received, then the ~ presetting input of the counter becomes with the trailing edge of the signal TQ 68 acted upon with twOtt signal, since at this point in time the signals LX, S, KQ and TQ are all high levels. This means that the "L" signal also appears in the signal curve by E.

Mjt t of all of the elements 68 to 73 existing arrangements record all reception errors that are assigned to a binary character Signal or one resulting from two consecutive identical binary characters Return signal.

The error signal E can especially when writing information be evaluated on a magnetic tape. The newly written information is then read immediately, with an error signal appearing if the information is incorrect was written. This error signal can interrupt the read and write process to rewrite the incorrectly recorded information on the tape.

Claims (12)

Claims Method for receiving serially arriving, in the manner of a directional clock phase-coded signals that cannot be recognized in the event of an error, characterized by: that from the time interval between two consecutive received signals the period calculated between two incoming binary characters and a clock signal sequence whose Period # and phase is synchronized with the signals, it is generated that the binary characters be forwarded phase-shifted by one period of the clock signal sequence and that due to the mutually different polarities of two according to the directional clock successive signals taking into account the polarity and phase of the last received signal before the absence and the first received signal after the absence of signals for one or more consecutive clock periods a correspondingly supplemented binary character is output and / or an error message is generated will. 2. The method according to claim 1, characterized in that counting pulses are summed up in the time between two consecutively received signals, that the counting result is divided to distinguish half-periods, which also are counted that the first half of the period is a signal that is a binary character corresponds, and the second half of the period a signal that two consecutive corresponds to the same binary characters, - and that for phase synchronization for each incoming signal the period half counter is halved by the To limit the duration of the currently applied half of the period, while failing to do so of a signal, the clock signal sequence synchronized with that of the last received signal Period and phase expires. 3. The method according to claim 2, characterized in that upon commissioning the transmission of the count is based on a predefined value, which is so large that between the first and the second received signal at least two clock periods expire. 4. The method according to claim 1 or one of the following, characterized in that that the beginning of a transmission is always determined by the same coded signal sequence and that based on the known polarity of the signals in the absence of a A corresponding binary character is added to the signal. 5. The method according to claim 1, characterized in that the the positive or negative polarity assigned to received signals for determination the up or down counting direction of a counter acted upon by the signals is used to generate an error signal if the count is different from zero or one and that after a clock signal period in which no binary character corresponding signal has been received, the count is preset to two. 6. Apparatus for performing the method according to claim 1, characterized characterized in that the positive and negative signals ID Pz, NB, N go back Signals (POS, NEG) each to the set or reset input of a flip-flop (3, 4) are supplied, which is connected to an EXCLUSIVE-OR gate tal9), which is based on the preparatory input of a flip-flop (20) is performed, the triggering input can be acted upon by the signals of the clock signal sequence (TQ), their period and Phase is synchronized with the incoming signals (POS, NEG), and that the second Input of the EXCLUSIVE-OR gate (19) is connected to a flip-flop (58), in the signal negated to the clock signal (TQ) when a signal (POS, NEG) is received (TQ) can be stored, while a presetting via a clock signal (TQ) controllable gate circuit (59) and a cancellation over one of the half periods of the clock signal (TQ) determining the counter (35) can be produced. 7. Apparatus according to claim 5 for performing the method according to Claim 1 or 2, characterized in that counting pulses (ZCP) in up counters 52, 53, 54 can be entered, which on receipt of a signal (POS, NEG) on the content zero are resettable that before resetting the counter contents with simultaneous Division can be entered in shift registers (46, 47, 48), the content of which is down counters (49, 50, 51) can be supplied, if the content is zero, a signal is sent to the preset input a flip-flop (23) can be specified, followed by a further flip-flop (21) is, whose output 'the clock signal sequence (TQ) can be taken, and that the output signal of the first flip-flop (23) can be fed to a further counter (35) which, upon receipt of a signal (POS, NEG) can be reset to zero and via a decoding circuit (29, 30, 31, 39, 40, 41, 43, 44, 45) the shifts in the shift registers (46, 47, 48) and, together with the output signal of the first flip-flop (23), the deletion of the flip-flop (58) that is connected upstream of the EXCLUSIVE-OR gate (19) is. 8. Apparatus according to claim 6 for performing the method according to Claim 3, characterized in that the presettable inputs de.s first and last counter in a chain of three counters (52, 53, 54) with ~ O "signals and the preset inputs of the middle counter (53) of the chain with the lowest and highest values with t'0 "signals and with the second highest value can be acted upon with a ~ L ', signal at the beginning of the transmission. 9. Apparatus according to claim 6 or 7 for performing the method according to claim 4, characterized in that the delete input of the EXCLUSIVE-OR element (19) upstream. Flip-flop (58) an AND-NOT gate 459) is connected, its Inputs from the clock signal sequence (TQ) and from the negated output signal (RDQ) of a Flip-flop (60) can be acted upon by a signal (C) of the second counter (35) can be deleted and the triggering input of counting pulses (ZCP? one Clock generator all7) can be acted upon, while the presettable input with an AND-NOT element (61) is connected, the inputs of which the clock signal sequence (db), the inverted output of one of signals (FQ). that of received signals (POS1 NEG), retriggerable, monostable flip-flop (8) and that Output signal of an EXCLUSIVE-OR gate (42) can be fed to flip-flops (62, 63) is connected, which is used to correct errors at the beginning of a transmission are determined. 10. Apparatus according to claim 6 or one of the following, characterized characterized in that a retriggerable, monostable multivibrator (57) is provided which can be retriggered by received signals (POS, NEG), and its non-inverted Output signal (FX) is connected to the clear input of a flip-flop (27) whose preparatory inputs can each be acted upon with "0" or "L 'signals, while the triggering input is connected to the second counter (35), and that the Output of the flip-flop (27) in combination with an output signal of the second counter (35) for the presetting of the controllable by the down counters (49, 50, 51) Flip-flop (23) and a decoder switch (18, 65, 66) for presetting the further flip-flops (62, 63) is provided. 11. Device according to claim 6 or one of the following, characterized in that that from received signals (POS, NEG) derived signals trigger inputs from flip-flops (5, 6) can be supplied, whose., preparatory inputs with "L" signals can be loaded and their non-inverting outputs with an EXCLUSIVE-OR element (7) are connected, the output signal of which triggers a counting chain (9 to 16) which as tail counter (35, 49, 50, 51, 52, 53, 54), shift register (46, 47, 48) and switching elements (5, 6, 35, # 39, # 40, 44, 41, 57, 65, 55) controls. 12. Device according to claims 6 to 11 for performing the Method according to Claim 5, characterized in that a presettable up / down counting he (68) is connected to the counting inputs with AND-NOT gates (69, 70) that each an input of the AND-NOT gates (69, 70) to the non-inverting output of a Flip-flop (14) of the counting chain (9 to 16) is connected that an input of the Count input forward feeding AND-NOT element (69) with the one OR'NOT element (3) of the flip-flop (3, 4) and an input of the counter input feeding backwards AND-NOT gate (70) with the other OR-NOT gate (4) of the flip-flop (3, 4) in The connection is that the output assigned to the place value two has an OR-NOT element (71). Is applied to the preset input of the ~ counter (68) that the second input of the OR-NIGHT element (71) two AND-NOT elements (72, 73) connected in series is, the inputs of the first AND-NOT-Qieds (73) of output signals of two Flip-flops (21, 58) and conjunctively linked output signals of another flip-flop (21) and an AND-NOT gate (22) are applied, and that the preset inputs of the counter (68) the value two can be supplied. Blank page