DE2215519A1 - PROCEDURE FOR RECORDING INFORMATION AND CIRCUIT ARRANGEMENT FOR PERFORMING THE PROCEDURE - Google Patents

Description

E. 8 33

15.3. ^ 972

Attachment to

Pat ent registration

ROBERT BOSCH GKBH, 7 Stuttgart ". P.O. Box 50

Process for recording information and circuit arrangement for carrying out: the process __

The invention relates to a method for recording information on electro-sensitive paper, in particular on registration metal paper, using a group of ei write electrics placed next to one another, which electrically oppose are isolated from each other and each individually via a controllable Switches can be controlled.

There are already methods of this type known in which one or several groups of walking electrodes as a so-called electrode comb are trained. For controlling each individual writing electrode a special character generator is used here;

309841/0637

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Robert Bosch GmbH? ? 1 RR 1 9 Fb / ΐΌ

Stuttgart

. all character generators being the individual writing electrodes drive at the same time. The simultaneous control of the writing electrodes brings with this method the disadvantage of bridges—

. Formation between the individual writing electrodes with.

It has now been found that this disadvantage of bridging is eliminated in a method of the type mentioned at the outset,
if, according to the invention, the individual writing electrodes are driven one after the other and the duty cycle of each individual
The writing electrode is chosen to be shorter than the time after which the
The burnout process is all finished.

A preferred embodiment of the method according to the invention
is that the group of juxtaposed
Writing electrodes is assigned a demultiplexer whose number of information outputs is equal to the number of writing electrodes
of the electrode group is that the information to be recorded on the electrosensitive paper is sent to the first input of a
two inputs provided NAND gate and are rasterized by the second input of this NAND gate, successive clock pulses at equal time intervals \ that
the rasterized information lying at the output of this NAND gate is placed on an enable input of the demultiplexer, that the clock pulses lying on the second input of the NAND gate are also placed on the clock input of a binary counter, that the generated at the information outputs of the binary counter
Pulses applied to the information inputs of the demultiplexer
and that the write pulses arising at the information outputs of the demultiplexer are sent to the control electrodes of the controllable
Switch are supplied. The write time is equal to the duration of the clock applied to the second input of the NAND gate.
impulses. Since this time is shorter than that until the onset of the
The time elapsing after the next clock pulse ensures that the individual writing electrodes of the electrode group are controlled one after the other.

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Robert Bosch GmbH ^ 2215519

Stuttgart -

In a further development of the invention 'it is advantageous between the' Output of the NAND gate and the release input of the demultiplexer 'a mono-flop with adjustable duration of its output pulses to lay. The writing time is then the same as this adjustable Duration tg of the output pulses of the mono-flop. The result possible change in writing time also allows a change the point size and thus the degree of blackening, so that gray value recording is possible. ■

The invention also relates to a circuit arrangement for recording information using five electrode groups arranged next to one another, each of which has the same number of writing electrodes that at the same time the switch-on duration of each individual writing electrode is shorter than the time after which the burnout process ends by itself. Demultiplexers are assigned, the information outputs of the binary counter being connected to the information inputs of all five demultiplexers and the information outputs of the five demultiplexers with the writing electrodes each of one electrode group e are connected so that each Cct is assigned five demultiplexers of one of five HAND gates each provided with three inputs, with the first release inputs of the demultiplexer being connected to the output of one of these. NAND gates are connected, that the first input of these five NAND gates is connected to the output of the mono-flop, that three flip-flops are also provided, that the input of the first flip-flop to the output of the highest value of the binary counter is connected that the input of the second

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Robert Bosch GmbH 2215519 Fb / Lo

Stuttgart

Flip-flops to the non-inverting output of the first flip-flop is connected that the input of the third flip-flop is connected to the non-inverting output of the second flip-flop is that. the inverting output of the third flip-flop is connected to the second release input of the fifth demultiplexer is that the non-inverting output of the third FJip-Flop to the second enable inputs of the other four Demultiplexer is connected that the second input of the first demultiplexer associated NAND gate to the inverting Output of the first flip-flop is connected that the third input of this NAND gate to the inverting output of the second flip-flops is connected that the second input of the second demultiplexer associated NAND gate to the not inverting output of the first flip-flop is connected that. the third input of this NAND gate to the inverting one The output of the second flip-flop is connected to the second input of the NAND gate assigned to the third demultiplexer is connected to the inverting output of the first flip-flop that the third input of this NAND gate to the non-inverting. Output of the second flip-flop is connected that the second input of the fourth demultiplexer assigned NAND gate is connected to the non-inverting output of the first flip-flop that the third input of this NAJD gate that the second input of the fifth demultiplexer is connected to the non-inverting output of the second flip-flop associated NAND gate is connected to the non-inverting output of the third flip-flop and that the third input of this NAND gate is held in the "HIGH" state by applying the operating voltage.

The invention is to be explained in more detail with the aid of the drawing.

-b-

309841/0637

—5—
Robert Bosch GMBH . τ-> ι rr ι r »

_e . ... zz praise la

.Stuttgart
Show it: . ■ ""

Fig. Ι a circuit arrangement according to the invention with a Group of sixteen write electrodes arranged next to one another and a demultiplexer assigned to this group with sixteen information outputs,

Fig. 2 shows a circuit arrangement according to the invention with five adjacent groups of sixteen writing electrodes each and five each assigned to a group Demultiplexers with sixteen information outputs each,

3 shows a pulse diagram for the circuit arrangements according to Figures ^Λ and 2. ·

In FIG. 1, the electrosensitive paper used as a recording medium is designated by 20. _{A group 21 of sixteen juxtaposed writing electrodes S 0} , S ^, Sp, S ^ c-) which are electrically isolated from one another is used to record the information on the electrosensitive paper 20. The write electrodes Sq, S ^ ₁ , Sp, ... S ^ ₁₁ - are controlled via _{write transistors T Q} , T ,,, Tp, ... Ty ₁ C. The collectors of the write transistors are connected to the write electrodes, the emitters of the write transistors to Rasse. The electro-sensitive paper 20 'is connected to the writing voltage via a resistor 26: -35 volts. The electrode group 2 ^ is a demultiplexer. · J ' ¹ ·. assigned. The demultiplexer 3 ^ is provided with i'6 information outputs, which are designated with 0,% 2, ... ^ 5, and also has four binary inputs A ^, B ^, C ^, Dy serving as information inputs. and two release inputs G ^, _Λ and G _{0 Λ} . The demultiplexer 3 * ¹ can be a commercially available TTL demultiplexer implemented using integrated technology. The information outputs 0, ^, 2, '... 15 of the deniiltiplexer 3 ^ ¹ are via protective resistors Ra, P- ^ ₁ , Rp, .... R ^ c to the bases of _{the write transistors T Q} , T,., Tp , "... t ^ t- connected.

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Furthermore, there is a MANUAL _{with two inputs E. n} and E _{0 n}

¹ , U / i, U

Gate ITq provided. The output P _{Q of} this ITAND gate Nq is connected to the input 41 of a mono-flop 40, the output pulses of which have a variable pulse duration t _c , this pulse duration being adjustable on a potentiometer (not shown). The output 42 of the mono-flop 40 is connected to the first release _{input G 7} , _{Λ of} the demultiplexer 31. The second entrance Ep _. of the NAND gate Nq is connected to the clock input 5 ″: of a 4-bit binary counter 50, the information outputs Aq, Bq, Cq, Dq of which are connected to the information inputs A ^, B ^, C ^, D ^ of the demultiplexer 31. The second release input G _{0 Λ of} the demultiplexer 31 is connected to ground and is thus held in the "LOW" state. A second mono-flop 60 is also provided, the non-inverting output 61 of which is connected to the reset input 52 of the 4-bit Binary counter 50 is connected.

The mode of operation of the arrangement according to FIG. 1 is as follows: The information to be recorded on the electrosensitive paper (VIDEO) is applied to the first input Έ _{Λ Q of} the NAND gate N _Q (FIG. 3 »second line). At the second input Ep q of the NAND gate Nq there is an externally applied write clock Cp which also controls the 4-bit binary counter 50. The pulses at the output Pq of the NAND gate N _Q are shortened in the Μσηο flop 40 i * i of their pulse duration to a value that corresponds to the switch-on duration tg of each individual writing electrode S _Q , S ^, Sp, ... S ^ ₁ - This value can be adjusted using the potentiometer not shown in the drawing. This duration tg of the impulses generated at the output 42 of the mono-flop 40 is set so that it is shorter than the time after which the burnout process ends by itself were. These pulses picked up at the output 42 of the mono-flop 40 are applied to the first release input G ^ ^ of the demultiplexer 31, while the second release _{input G 2 Λ is held} in addition ^ and "LOW". The write clock Cp controls

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Robert Bosch GmbH .. 2215519 Fb / Lo

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at the same time to the 4-bit binary counter 50 in such a way that all sixteen possible states running in a logical sequence result _{at its outputs A 0, Bq, Cq, Dq.} These output pulses of the 4-bit binary counter 50 are given to the information inputs A, B ^, C _x ,, D ,, of the demultiplexer 31. It is thereby achieved that the information outputs 0, ", 2, ... 15 cL ^it demultiplexer 31, in cycle on the first release G ^, _Λ entrance lying write pulses in each case for the duration to a single pulse on the" are LOV / "connected A write pulse appears only at those information outputs that simultaneously receive the information determined by the video signal. The write pulses generated at the information outputs 0, 1, 2, ... 15 of the demultiplexer 31 are transmitted via the protective resistors Rq, R ^, Rq, ... R / in the bases of the write transistors Tq, T ^, Tp, ... T ^ c, which switch through the write voltage for the duration tg of the pulses. After all write electrodes Sq, S ,,, Sp, ... S ^ c are run through, the 4-bit binary counter 50 is reset to the initial state by a reset pulse, which receives its defined duration in the mono-flop 60.

Fig. 2 shows a second embodiment of a circuit arrangement according to the invention. To record the information. The writing electrodes of the first group 21 are _{denoted by S n} ,,, S .. _Λ , S ₀ ,,, ... S ^ t- _Λ

U, ¹ 'ι ¹ * - ϊ ^{1 1} Pi'

net, that of the second group 22 with S _n ->, S _x , _o , S _{0 o} , ... Sx ₁₁ -. _o , ... those of the fifth group 25 with Sq, -, S ^ 51 ^ 2 5 '* * *' - ^ 15 5 * The writing electrodes S _n . , S _x ,., S ₀ ...... S _x ,, -. every givppe

U, l 1.1 C ₁ - IP1J-

are written via write transistors T _n . , T _x . . , T ₀ . , ... T ^ ₁₁ - ^ an-

U, l 1) 1 c:, l '?) L

controlled, v / obei i takes on the values 1, 2, 3i ^ i and 5 depending on whether the write electrode or the write transistor in the

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Eobert Bosch GmbH? ? 1 R R 1 Q Fb / Lo

Stuttgart

first group 21, the second group 22, the third group 23 and so on. The collectors of the write transistors are connected to the write electrodes, the emitters of the write transistors to ground. The electrosensitive paper 20 is connected to the writing voltage of -35 volts via a resistor 26. Each of the five electrode groups 2i, 22, 23, 2-4-, 25 is assigned to one of five identical demultiplexers 31, 32, 33, 34-, 35. Each demultiplexer is equipped with two release inputs G "., G ₀ . and

ι, 1 d. , 1

provided with four binary information inputs A ·, B-, C, D-, where i takes on the values ^, 2, 3, 4-, 5 depending on whether the demultiplexer, the first electrode group 21, the second electrode group 22, the third electrode group 23 and so on. Each of the demultiplexers also has sixteen information outputs j, each labeled 0, ^, 2, ... 15. These information outputs are each via protective resistors R _n .,

υ, ι

1? . , E ₀ . , ... E ^ c-. to the bases of the write transistors T _n . , T /, _π ·, T ₀ ^, ... T ^ t-. connected.

Furthermore, a NAND with two inputs E ,, _n , E _{0 n}

. , u ti , u

Gate Nq provided. The output P _{n of} this NAND gate IT _n is connected to the input ^L 'A of a mono-flop 40 whose output pulses eir-e have a variable pulse duration to, this pulse duration being adjustable on a potentiometer, not shown. The second input Ep q of the NAND gate Nq is connected to the clock input 5 ″ of a 4-bit binary counter 50, the information outputs of which are designated Aq, Bq, Cq and Dq. These information outputs are connected to the information inputs A-, B., C .., D. all demultiplexers 3 ^, 32, 33, 34-, 35, whereby the output Aq with all inputs A- (i = 1 to 5) output B _{Q is} connected to all inputs B. (i = 1 to 5), output Cq to all inputs C. (i = 1 to 5) and output Dq to all inputs D. (i = 1 to 5) .

Each of the five demultiplexers 31, 32, 33, 34 ·, 35 is one of five each with three inputs E ""., E,> . , E,. provided NAND

i, 1 c , 1 p, 1

3 0 9 8 41/0637 " ₉ _

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Robert Bosch GmbH 9 91RRIQ Fb / Lo

Stuttgart _x - ';

Associated with gates N ^ ₁ Np, N ,, K. and Np-, the outputs of which are labeled P ^ (i = 1 to 5). The first release input G ^ _{Λ of} the ■ first demultiplexer 31 is to the output P ^ of the NAND gate N ^, the first release input G ^ _{o of} the second demultiplexer 32 to the output P _{2 of} the NAND gate Np, the first release input G _-1 -j. of the third demultiplexer 33 to the output P ^ of the NAND gate N ,, the first release input G _x , ^ of the fourth demultiplexer 34 to the output P ₂ , the NAND gate N ^ and the · first release input G ^ c of the fifth Demultiplexer 35. the output P _n - of the NAND gate N _n - connected. The first input Έ, _{Λ i of} the five NAND gates N ^ ₁ , N ₂ , M. ,, N ^, N ^ is connected to the output 42 of the mono-flop 40. ■

Furthermore, three flip-flops F ^ ₁ , F ₂ and F are provided. The input 70 of the first flip-flop F ^ ₁ is connected to the output Dq of the 4-bit binary counter 50. The input 80 of the second flip-flop Fp is connected to the non-inverting output £ L of the first flip-flop F. The input 90 of the third flip-flop F is connected to the non-inverting output Qp of the second flip-flop F ₂ . The inverting output £ L of the third flip-flop F ^ is connected to the second enable input Gp π of the fifth demultiplexer 35. The non-inverting output Q- of the third flip-flop F ^ is connected to the second release inputs G _{0 Λ} , G _{0 o} , G _{0 7} , G _{0 A of} the other four demultiplexers 3 ″ 32, 33j 34 . The second input Ep ^ of the NAND gate N ₄ is connected to the inverting output ζ ^ of the first flip-flop F. The third input E ^ _{Λ of} the NAND gate N ^ is connected to the inverting output £ L of the second flip-flop F ₀ . The second input E _{2 2 of} the NAND gate N ₀ is connected to the non-inverting output Q ^ of the first flip-flop Έ _Λ . The third input E _{xo of} the NAND gate Np is connected to the inverting output Q ^ of the second flip-flop F ₂ . The second input E ₂ ^ of the NAND gate N_. sn is the inverting output Q ₁ ^ of the first flip-flop F ^

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Robert Bosch GmbH 2215519 Fb / Lo

Stuttgart

connected. The third input E ₇₂ . _{x of} the NAND gate N- is connected to the non-inverting output Qp of the second flip-flop Fp. The second input E ~ ^ of the NAND gate K ^ is not at the; inverting output Q ,, of the first flip-flop F ^ connected. The third input E ^ ^ of the NAND gate K. is connected to the non-inverting output Qp of the second flip-flop Fp. The second input E _{9 r of} the NAND gate N ₁ - is connected to the non-inverting output Q ^ of the third flip-flop F ^. The third input E-, j- of the NAND gate Kr is in the "HIGH" state by being applied to the operating voltage U

CC

keep.

A second mono-flop 60 is also provided. The non-inverting output 61 of the mono-flop '60- is connected to the busy input of the 4-bit binary counter 50. The inverting output 62 of the mono-flop 60 is connected to the set inputs 7 " ¹ » 8 * ¹ , · 9 ^ of the flip-flops F _-1 , F2, F.

The mode of operation of the arrangement according to FIG. 2 is as follows:

The information to be recorded on the electrosensitive paper (VIDEO) is applied to the first input E „ _{0 of} the IJfAlTD gate N ₀ . Such a video signal is shown in the second line of FIG. 3 as an example. At the second input E _{0 n of} the NAND gate Nq there is a write clock Cp applied by aaßen, which also controls the 4-bit binary counter 50. The pulses at the output F _{0 of} the NAND gate N _Q are shortened in their pulse duration in the mono-flop AO to a value which corresponds to _{the switch-on duration tg of each individual writing electrode Sq, S ^ 1} , Sp, ... S ^ _{1 -} , this value being adjustable on the potentiometer not shown in the drawing. This duration tg of the impulses produced at the output 42 of the mono-flop 40 is set so that it is shorter than the time after which the burn-out process takes place

309841/0637

8 3 3 Robert Bosch GmbH .. 9 9 1 c: c 1 Q Fb / Lo

Stuttgart

would have ended alone. These pulses picked up at the output 42 of the mono-flop 40 are sent to the first inputs Έ _Λ . the NAND gate N_. placed, whose outputs P. to the first release inputs

A. -X "

courses Gy,. the demultiplexer are connected, -ι, χ.

The write clock Cp simultaneously controls the 4-bit binary counter in such a way that "all sixteen possible states running in a logical sequence result at its information outputs Aq, Bq, Cq, Dq. These output pulses from the 4-bit binary counter 50 are based on the each parallel information inputs A, B., C., D, of the demultiplexer 31, 32,? 34, added 33 35th if the two enable inputs G and _Λ · G _0th the demultiplexer would thereby at the same time "LOW", so the information outputs O, ^, 2, ... 15 of the demultiplexers 31, 32, 33, 34, 35 one after the other at the rate of the write pulses each for the duration tg of a single pulse to ¹¹ LOVi "switched. The outputs 0 of all demultiplexers would be switched to "LOVi" at the same time, then all outputs 1, then all outputs 2, etc., until with the sixteenth write pulse all outputs 15- are switched to "LOV /" and then all outputs 0 start again .

However, the second release inputs · G ₀ . the demultiplexer is switched so that only one demultiplexer is enabled at a time. The signals at the output 42 of the mono-flop, 40 were linked in the NAlTD- ¹ ~ i at tern N- with the output signals of the lip-flops F ^ ₁ , F ^, F, and transferred to the first enable inputs G ^, . given the demultiplexer. This ensures that only the output of a demultiplexer writes which has been selected by the counters 50, F _x ., Fp, F ^ and at the same time receives the information determined by the video signal. The write pulses generated at the information outputs 0, 1, 2, ... of the demultiplexers 31, 32, 33, 34, 35 are transmitted via the protective resistors E _0. , E. _i5 H ₀ ,, ... E ^ ₁ . the bases of the write transistors T _n -, T-., T ₀ -, ... T ^, -. supplied, ax the write voltage for the duration tg cer pulses

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switch through. After the writing electrodes S _n . , S _x,. , S ₀ . , ... S ^ c-. of all groups 2% 22, 25, 24, 25 have been run through, i.e. after eighty clocks in the selected exemplary embodiment, all counters 50, P ^, Fo, F ^ reset to the initial status.

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309841/0637

Claims (1)

8 3 3 Bosch GmbH ^{ζζια3! 3} . _: Fb / Lo ■ Stuttgart Claims ■ M J Procedure for recording information on electrical * S sensitive paper, especially on registration metal paper Use of a group of individual, arranged side by side. Neten writing electrodes, which are electrically insulated from each other are each individually controlled via a controllable switch are, characterized in that the individual writing electrodes are driven one after the other and that the duty cycle Each individual writing electrode is chosen to be shorter than the time after which the burn-out process ends by itself is. . Method according to Claim 1, characterized in that the group (21) of writing electrodes (Sq, S _x ,, Sp, ... Sy | c) arranged next to one another is assigned a demultiplexer (J1) whose number of information sau κ gang en (θ, 1-, 2, ... 15) equal "'. the number of writing electrodes (S _Q , S _x ,., S ₂ , ... S / jc) their ■ electrode group (21) is that the information (VIDEO) to be recorded on the electrosensitive paper is applied to the first:} input (Ξ> _Q ) of an ITAND gate (Nq) with two inputs (E ^ _Q , Έ ^ q) and through the second input (Ep q) of this NAND gate (Nq) placed at equal time intervals successive clock pulses (Cp) are rasterized, 309841/0637 8 3 3 Stuttgart that the rasterized information lying at the output (Pq) of this RAITD gate (Nq) is applied to an enable input (G,. *) of the demultiplexer (31), that the _{information at the second input (E 2 0} ) of the ITAITD gate (1T _Q ) lying clock pulses (c _p ) are also applied to the clock input (5 ^) of a binary counter (50) so that the pulses generated at the information outputs (Aq, Bq, Cq, Dq) of the binary counter (50) are sent to the information inputs (A ^, B ^, C ^, D ^) of the demultiplexer (31) and that the write pulses generated at the information outputs (0, 1, 2, ... 15) of the demultiplexer (31) are sent to the control electrodes of the controllable switches (T _Q , T ^, T ~, ... T ^ r-) supplied to ground. 3. Circuit arrangement for performing the method according to claims 1 and 2, characterized in that between the Output (Pq) of the ITAND gate (Nq) and the enable input (G "") of the demultiplexer (31) a mono-flop (40) with adjustable Duration (tg) of its Ausgarigsimpulse is placed. 4 .. Circuit arrangement according to Claim 3 for recording information (VIDEO) using five electrode groups (2'1, 22, 23, 24, 25) arranged next to one another. each of which has the same number of writing _{electrodes (S n} ., S "., S"., ... S ^ c.), characterized in that each of the five electrode groups (21, 22, 23, 24, 25) has one of five of the same, each with two release inputs marked a (G ^., G _0. ) 309841/0637 ^ll ^ ^{? 1} Eöbert Bosch GmbH. Fb / Lo Stuttgart - Demultiplexers (31, 32, 33, 34, 35) is assigned, the information _{outputs (A n} , B _n , Cq, D _q ) of the binary counter (50) to the information inputs (A., B ^, "C., D .) of all five demultiplexers (3 ^ i 32, 33, 34, 35) are connected and where also the information outputs (0, 1, 2, ... 15) of the five demultiplexers (3 ^, 32, 33, 3 ² I -, 35) with the writing electrodes (S _n -, u, -x Si ς ν S ₀ -, ... SC-) one electrode group each (21, 22, 23, ι, 1 cL, ± I ρ, Χ 24, 25) are connected so that each of the five demultiplexers (31, 32, 33, 34, 35) has one of five HMD gates _{each with three inputs (E 71} ^, E _{2 i} , E ₅ ^) (H _-1 , Kg, N ,, H ^, N ₅ ) is assigned, where the first event inputs (G _x ,. ") Of the demultiplexer (31, 32, 33, 3 ^, 35) G ^ewei l ^s to the Output (P ^) of one of these NAHD gates (W-) are connected, that in each case the ercte input (E.- ") of these five NAND gates (W-) to the 1.1 1 Output (42) of the Kono-IMops (40) is connected, that three ITlip- ^ flops (I ¹ ^ ₁ , I "p, F ^) are provided that the input (70) of the first flip-flop (F ^) to _d.en; most-significant output (DQ) of the binary counter (connected 50) that DTR input (80) of the second flip-flop (Fp) of the non-inverting output (Qp) of the second flip-flop (m.p. ) is connected, that the inverting output (Q ^) of the third flip-flop (F,) is connected to the second release input (Gp, -) of the fifth demujtiplexer (35), that the non-inverting output (Q ^) of the third Flip-flops (F,) to the second release ports (G "^, Gp", ^ ₂ ^, G ₂ ^) of the other four demulti- 309841 / 0637V - Ib- 8 3 3 plexer (3 " ¹ » 32, 33 »34-) is connected that the second input (E ₀ -.). of the first demultiplexer (3Ό associated NAND gate (N ^ ₁ ) to the inverting output (CL) of the first flip-flops (F / i) is connected that the third input (E, ^) of this NAND gate (N ^) is connected to the inverting output (Q ₂ ) of ^the second flip-flop (Fp) that the second input (E ~ p) of the second demultiplexer (32) associated NAND gate (Np) is connected to the non-inverting output (Q ,,) of the first flip-flop (F ^) that the third input (E ₇ . _o ) this NAND gate (N ₀ ) is connected to the inverting output (Qp) of the second flip-flop (Fp) so that the second input (E _n ^) of the NAND gate assigned to the third demultiplexer (33) ( N ^) is connected to the inverting output (Q ^) cl ^it first flip-flops (F ^) that the third input (E _7. S) of this NAND gate (N _7. ) To the non-inverting output (Qp ) of the second flip-flop ( Fp) is connected that the second input (Ep ^) of the fourth demultiplexer (3 * 0 zxxordinated NAND gatex ^ s <J $, ) to the non-inverting output (Q. *) of the first flip-flop (F ^ ) is connected, that the third input (E ₇ -,.) of this NAND gate (N ^) is connected to the non-inverting output (Qo) of the second flip-flop (Fp), that the second input (E ₀ , -) of the fifth demultiplexer (35) associated NAND gate (Kr) is connected to the non-inverting output (O _l7j ) of the third flip-flop (F ₇ -) and that the 3098A1 / 0637 - ^Λ Ί- ■ -17-. ■ - * ■ 8 3 3 Robert Bosch GMBH . . £ b / Lo Stuttgart - third input (E ^ t-) of this KAKD gate s- (Nr) by applying to the operating voltage (TI) is held in the "HIGH" state. CC 5. Circuit arrangement according to claim 4, characterized in that that one or more electrode groups (21, 22, 23, 24, 25) are housed in an electrode comb, which consists of individual segments that both the writing electrodes and contain the write transistors as well as the demultiplexer. 6. Circuit arrangement according to claim 5? characterized, that the writing electrodes are made of tungsten wires » 7. Method for producing a circuit arrangement according to Claim 6, wherein the circuit-side ends of the Writing electrodes on the coil connection terminals of the writing Are, transistors fastened by means of soft solder, characterized in that, this ends before soldering the .an. "Collector terminals galvanically copper-plated, gold plated, are silvered 'or tinned. 309841/0637 Blank page