DE2208892B2 - Digital memory for telephony - has storage elements controlled via AND:gates, diodes, transistor switches and common line from allocator - Google Patents

Abstract

The digital memory, for telephony, retains information used for setting up a connection (and also for monitoring and metering. The information is repeated and the memory fills in the gaps (due to noise) in the first transmission with the corresponding information in the repeated second transmission. Storage elements are provided and their number depends on the code employed. Each element is controlled via an AND-gate arrangement, a diode and a transistor switch, and via a common line from an allocator and from write-in pulses via a gate. Each row of element has a monitor that prevents more data entering when an element is already occupied.

Description

30th

When transmitting information, inter alia digit memory used in telecommunications technology, in which a series of digits (information) are stored, the primary di »-m connection establishment are used, but are saved for a period of time for further evaluation (e.g. control, billing) Need to become.

When information is transmitted over failure-prone transmission paths, e.g. B. over radio, can intermittently Parts of the information fail. It is already known to secure the transmission of the information several times in a row. The object of the invention is to provide a memory arrangement in the memory gaps that occurred during the first information transfer during the second Transfer to be populated.

The object is achieved with a circuit arrangement for a repeated transmission of information Digit memory that can be filled via failure-prone transmission paths, identified by each digit assigned series of individual memories, the number of which depends on the type of coding and of which each Single storage via a; UN D gate arrangement, one further diode and a switching transistor both from an input circuit and via a common one Line can be controlled by a digit allocator and by a write-in pulse via a gate circuit is, each row is assigned a monitoring device, the storage in the individual storage, releases or blocks depending on their occupancy via the gate circuit.

The inventive circuit arrangement of the Digit memory, its mode of operation and further refinements are described below with reference to the Circuit diagrams of an exemplary embodiment described and explained in more detail.

The circuit arrangement of the exemplary embodiment is designed for coding “two out of five” and is shown for the storage of two digits. The circuit arrangement contains two rows of five individual memories I ... V each; Γ ... V (sheet 1, memory I, II, Ι ', ΙΓ; sheet 2, memory II, III, ΙΓ. III *: sheet 3, memory IV, V, IV, V). The number of individual memories 1 ... V; Γ ...

V of each row thus corresponds to the number of places in the code used. Should have more than two digits are stored, the number of memory rows must be increased accordingly. Each row of individual memories I ... V; Γ ... V is also a gate circuit 73 or 73 '(sheet 1) and one each Monitoring circuit Zbzw. Z '(sheet 1) assigned.

Each individual memory I ... V; Γ ... V contains an AND gate arrangement, which is here by two AND diodes D5, D6; DIl, D12 ... D29, D30 or D5 ', D6'; DU ', D 12' ... D29 ', D30', another diode D4, DlO ... D28 or. D4 ', D10' ... D 28 'and a switching transistor 74, 77 ... 716 or 74', TT ... 716 'is formed.

The circuit arrangement of the example is thus designed for positive logic, but it can be used without Difficulties can be built up according to known rules, even for a negative logic.

The input inputs 3,5 ... U or 3 ', 5' ... 11 of the Individual memory I ... V or Γ ... V of each row for entering the information to be saved (digits) are with the corresponding outputs of the memory locations of an input circuit, not shown, z. B. a shift register. The input inputs 3,5 ... 11 or 3 ', 5' ... 1Γ are corresponding to the Content of the input circuit either on plus potential or on minus potential. The memory contents of the Input circuit is at the same time parallel to the corresponding input inputs 3, 5 ... 11 or 3 ', 5 '... 11' the individual memory I ... V or Γ ... V. Im In the present case, a plus potential indicates information to be stored.

Is the input circuit, e.g. B. the shift register, filled, so one or two digits stored, this generates a write-in pulse. This can also be delayed for a short time due to a code check of the content. The write-in pulse, which is fed to the write-in input 1, acts on the AND gate arrangement D5, D6 via the gate circuit 73 or 73 '; DIl, D12 ... D29 D30 or DS ', DS ¹ ; DW, D12 '... D29', D30 '; D4 D 10 ... D28 or D4 ', D10' ... D28 '; 74, 77 ... 716 or 74 ', 77' ... 716 'of the individual memories I ... V or V ... V. However, the write-in pulse is only effective if the gate circuit 73 or 73' is triggered by the associated Monitoring device Zbzw. Z 'released, i.e. not blocked.

In which row the individual storage tanks I ... V or Γ ..

The information to be stored at the input inputs 3, 5 .. 11 or 3 ', 5' ... 11 'is determined by a digit pulse - plus potential - which is given by a digit allocator, also not shown, to the digit pulse input 2 or 2' . The digit pulse is on the common second line b or b ' to one of the UN D diodes D 6, D12 ... D 3 (or D6', D 12 '... D30' of the AND gate arrangement from the AND -Diodes DS, D6; D 11, D12 ... D29, D3 (or DS ', D6'; D11 ', D12' ... D29 ', D30', the other diodes D4, D10 ... D28 or . D4 \ DIO ' ... D28 and the switching transistors 74, 77 ... 716 or 74' 77 '... 716'.

For a precise explanation of the feed-in processes

rather than a piece of information, it is assumed that in the selected code "two out of five" the number "1" to be stored. Also that it was the first digit. In this case, the input scenario lies permanently Plus potential at the input inputs 3 and 7 of the individual memories 1 and HI of the first row. To the Storage access points 5, 9 and 11 of the individual storage units 11, IV and V is always negative potential. At the same time, the digit impulse from the digit allocator is also available as Plus potential at digit pulse input 2 of the first row. In addition, the is also at the same time Write pulse at the write input 1.

The positive potential of the input inputs 3, 7 is via one of the AND diodes D5, D17 at the base of the associated switching transistor 74, Γ10. At the same time, the positive potential of the digit pulse from digit pulse input 2 is also applied to the base of the switching transistors 74, 710 via the other AND diode D6, D18. The UN D condition is thus fulfilled for the switching transistors 74, Γ10 of the individual memories 1,111. The AND condition is not for the switching transistors 77, Γ13, T16 of the other individual memories 11, IV, V of the series, at whose base only the positive potential of the digit pulse input 2 is also applied via one of the AND diodes D 12, D 24, D30 Fulfills. The respective other AND diodes DH, D 23, D 29 have negative potential from the input inputs 5,9,11. Since the positive potential of the write input 1 is at the same time at the base of the transistor of the gate circuit 73 via the resistor R 8, this is now switched through.

Via the Zener diode D 3, the low-resistance emitter-collector path of the transistor of the gate circuit TZ, the common line c and the further diodes D 4, D 7 ... D 28, the operating voltage is therefore negative at the switching transistors TA, TT ... T16 of the individual memories 1 to V. However, only the switching transistors TA, T10, whose base the AND condition is fulfilled, are switched through. The minus of the operating voltage is therefore only via the low-resistance emitter-collector path of the switched-through switching transistors 7 * 4, 7 * 10 and a further resistor RIl or R 21 on the ignition electrodes of the assigned thyristor tetrodes Ti 5, TiW of the individual memories 1 and III. These thyristor speeches 7/5, 7711 ignite and carry current; the information is thus stored in the individual memories I and 111.

If there is no digit pulse - plus potential - at digit pulse input 2, and consequently at the base of the Switching transistors Γ4 ... Γ10, this is the AND condition no longer fulfilled for the switching transistors T4, T10; they are now blocked again.

If the transistor of the gate circuit 7 * 3 is blocked again after the write-in pulse has ceased to exist at the write-in input 1, the minus of the operating voltage at the emitter of the switching transistors TA, 710 is also eliminated; they are also locked again.

The thyristor tetrodes Ti 5, 7711 remain ignited and continue to carry current, as they are directly between the plus and minus of the operating voltage via a resistor. The stored information (number) is retained.

The second gate circuit T3 \ D 3 'assigned to the individual memories Γ ... V is also switched through by the write-in pulse on write-in input 1, but it does not trigger any further switching processes. Since there are no pulses either at the input inputs 3 '... W or at the digit pulse input 2', the AND conditions for the switching transistors TA '...

7 * 16 'of the second row not fulfilled.

If the thyristor tetrodes Ti 5, Ti 11 of the individual memories 1, III are ignited, the operating voltage is connected to the minus via an OR circuit, each consisting of a diode D 9, D 21, and via a common additional decoupling diode D 2 Monitoring circuit Z Via a delay element, consisting of a series connection of a resistor and a capacitor, the minus continues to be at the base of the first

ίο transistor 7 * 2 of a two-stage transistor circuit 71, 72. The first transistor 72 switches on and in turn switches the second transistor 72 again by. The minus of the operating voltage is now applied to the base of the transistor via another diode Gate circuit 73. The gate circuit 73 is thus against being switched through again when there is a renewed issue of a write pulse at write input 1 blocked. In the individual memories 1 ... V, therefore, no Information to be registered more. The monitoring device Z responds with a delay so that the corresponding individual memories 1 ... V are already safe are occupied.

If an item of information (digit) arrives garbled and is therefore in the input circuit, e.g. B. the Incomplete shift registers, this is determined by the code check. The input circuit in this case does not trigger a digit pulse or a write pulse. The faulty one Information is therefore not stored in the individual memories I ... V or Γ ... V inscribed. The same applies if a piece of information (number) is completely lost. In both cases remains the whole row of the relevant individual memories I ... V or Γ ... V "empty". When repeating the first transmission of disturbed information and now complete storage in the input circuit however, the row of the previously "empty" individual memories I ... V, I '... V is filled.

Information that was already entered in one of the rows of the individual memories 1 ... V or Γ ... V during the first transfer is not stored again. As described, the corresponding individual memories I ... V, Γ ... V are dzw by the associated gate circuit 73. 73 'blocked.
In the same way as described, the second information (digit) is also written into the individual memories Γ ... V of the second row if it is at the input inputs 3 ', 5' ... 11 ', as well as the digit pulse at the digit input 2' and the write-in pulse is applied to the write-in input 1.

Are other digits to be stored and the positive potentials of the input circuit are at other input inputs 5, 9, 11 or 3 ', 5' ... 11 'of the individual memories I ... V or Γ ... V, the storage takes place analogously as described.

For targeted retrieval of the information (number) stored in the individual memories I ... V, Γ ... V of a row, the individual memory I ... V or Γ ... V plus potential is applied to the query input 13 or 13 ' . In the case described, the positive potential of input 13 is connected via a diode and a common first line a in parallel to the base of each query transistor 76, Γ9 ... 718 of the individual memories I ... V. Of the interrogation transistors 76, 79 ... 718, however, only those 76, 712 are switched through, the emitter of which is connected via a diode to a thyristor tetrode 7/5, 7711, which is triggered because information is stored. Only the emitters of these interrogation transistors 76, 712 are connected to the thyristor

tetrodes Ti 5, 7711 to minus the operating voltage. During the interrogation, minus the operating voltage is applied to the output outputs 15 and 17 via the low-resistance emitter-collector path of the interrogating transistors 76, 7 * 12 that are switched through.

Via a decoupling diode D 7 and D 9, the stored information is also available at the outputs 4 and 8 for other purposes, e.g. B. for selective evaluation, available as a permanent potential.

To delete the information stored in the individual memories I ... V, Γ ... V, the The operating voltage is switched off during the occupancy breaks between two storages. The deletion can also take place automatically, for example by the final character at the end of the transmission of information take place.

The outputs 14 and 14 'are for test purposes intended.

For this purpose 3 sheets of drawings

Claims (1)

Claim: Circuit arrangement for a digit memory that can be filled up by repeated information transmission over failure-prone transmission paths, characterized by a series of individual memories assigned to each digit (I ... V or Γ ... V), the number of which depends on the type of coding and of which each individual memory (1 ... V or Γ ... V) via an AND gate arrangement (AND diodes D5, D6; DU, D12 ... D29, D30 or DS ', D6'; DIl ', D12'. .. D29 ', D 30'), another diode (D 4, D10 ... O 28 or D 4 ', D10' ... D28 ') and a switching transistor (74.7 7 ... 716 or . 74 ', 77' ... 716 ') both from an input circuit (input inputs 3, 5 ... U or 3', 5 '... 1Γ) and via a common line (b or k') can be controlled by a digit allocator (digit pulse input 2 or 2 ') and by a write-in pulse (write-in input 1) via a gate circuit (73 or 73'), with each row being assigned a monitoring device ( Z or Z ') that enables storage in the single store cher (I ... V or Γ ... V) according to their occupancy via the gate circuit (73 or 73 ') releases or blocks.