DE2206630A1 - MULTIPLEX TRANSMISSION DEVICE - Google Patents

Description

PURE

F 6048 '""'

COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS

CIT-ALCATEL 12, rue de la Baume, PARIS (8), France

MULTIPLEX TRANSMISSION DEVICE

The invention relates to a multiplex transmission device, in particular for use in automatic or semi-automatic electromechanical or electronic systems equipped with a signaling system.

Such a system is provided with a central logic unit which encrypts in the form of binary code signals Receives information representing the states of the terminal devices that it scans in a certain cycle, after which this information is sorted and given at the same time to the inputs of the device according to the invention, the serves to transfer the information to the relevant signaling devices forward the system.

The control and signaling devices of such a system can be from the terminals and the central logic unit be attached at any distance, such as the control panels of a remote control or remote control

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nalization system or the attendant consoles for setting up remote connections. The device according to the invention is suitable especially for use in a system with operator stations, connected to a telecommunications exchange as described in French patent 70-44562, the on December 10, 1970 by the applicant and what the terminals are trunk connectors and at the signaling devices around indicator lamps of the operator stations of the plant.

The device according to the invention offers the advantage that it reduces the circuit complexity between the central logic unit and the signaling devices are reduced to the maximum.

The invention relates to a multiplex transmission device, which is intended to transmit information locally or at any distance, which information is periodic reflect the state of central facilities, characterized in that it is equipped with a transmitting part, consisting of from devices for converting the information given at the same time into successive information, from devices for counting the sums of information, from devices for synchronizing the information in dependence from the timer pulses and their transmission to a receiving part, from devices for resetting the system Zero at the end of the transmission cycle, from devices for outputting additional information for monitoring parity, and that the receiving part is equipped with devices for

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Reception or decoding of the information sent, with devices for counting the information received during each cycle Number of items of information and devices to reset the count to zero if the number is incomplete received information is available.

According to one feature of the invention, the transmitting part of the device is connected to the central logic unit, and the receiving part is with the signaling devices connected, both parts consist of integrated circuits that are connected to each other by at least one two-wire coaxial line are connected.

According to another feature of the invention, the information emitted at the output of the receiving and decoding part to the input of a first group recognition register, which is assigned to a decoder, and to the inputs of Shift registers, which are assigned to matching circuits, are given, which are, for example, with the lamps of the switching stations in connection, the assigned registers as Display memories are used, the first register only processes the first three 'cycle information' and the inputs of the display memory remain blocked for the first three pieces of information, which specify, for example, the operator console that is the series of to receive subsequent information of the cycle.

The description of an exemplary embodiment contains further features and advantages of the device according to the invention according to the invention with reference to the drawing. Show it:

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1 shows the transmitting part of the device according to the invention;

2 shows the receiving part of the device according to the invention;

FIGS. 3 and 4 each show an example of the successive state signals which are produced at the output of the parity flip-flops (BP1 and BP2) of the transmitting or receiving part of the device are issued, as well as the state of the last one issued at the output Information, depending on an odd or even number of status signals 1 that are sent to the input of the Flip-flops are given;

5 shows a diagram of the mode of operation of a parity flip-flop as a function of the status information 1 and of a calibrated timer pulse;

6 shows the diagram of the signals at the input or output of the transmitter and the diagram at the output of the receiver and signals received by the decoding circuit.

In Fig. 1, which illustrates the transmitting part of the device, multiplexers MX1, MX2 ... MXi receive information from the buffer memory MT, which is shown in dashed lines because it does not belong to the device according to the invention.

This information, which is each characterized by the presence or absence of a potential, is in increasing order, i.e. the multiplexer MXl receives the information of order 1, 2 ... η to the corresponding Inputs EO, El ... Em, the multiplier coupler MX2

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receives the information of the order η + 1, η + 2 ... 2n the inputs EO to Em ..., which the multiplexer MXi receives for example the last information of the order in + 1, in + 2 ... in + k at the corresponding inputs EO, El ... Ej, and the buffer memory thus outputs a total of N pieces of information.

The only output Sl, S2 ... Si of each of them is at the input DO, Dl ... Di of a multiple coupler MX Via the connecting lines Ll, L2 ... Li, and the output S of this multiple coupler is connected to an input El of the transmitter EM connected via the information carrier line SIF.

With those used in the device according to the invention Multiple couplers are their selection control inputs on four limited (inputs A, B, C, D).

When the memory MT is full, it enters cyclically Cycle start signal DC to the input of a NOR circuit PO, the output of which is connected to the input El of a bistable multivibrator BB. An output Sl of this flip-flop is at one Input of a timer HL, the output of which is connected to the input E of the counting unit Cl.

The outputs A, B, C, D of the counting unit Cl are connected to the information selection inputs A, B, C and D of the Mshrfachkoppler MXl to MXi. The output D of the first counting unit Cl is also connected to the input E of a second counting unit C2, whose outputs F and G are connected to the information selection inputs F and G of the multiplexer MX. The exits F and G of the counting unit C2 and certain outputs of the

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Counting unit Cl are connected to the inputs of the NAND circuit PE tied together. The output of this circuit is at a second input E2 of the bistable multivibrator BB; the second output S2 This bistable multivibrator is on the one hand at the RZ inputs of the counting units CI and C2 and on the other hand at the P input the parity flip-flop BPl. The counting units Cl and C2 together form the counter CE. The inputs J and K of the parity flip-flop are in parallel with the information carrier line. SIF connected, and the output Q of this flip-flop is on Input EK of the multiplexer MXi, which receives information of the order N + 1 via this line. The output of the timer HL is at the input of the monostable multivibrator.BMl, the output of which is connected to the input dor monostable multivibrator BM2, the output of the monostable multivibrator at the Timer information carrier line SIH is the input E2 of the transmitter and the timer input H of the parity flip-flop connects with each other.

The lines Yl and Y2 are shielded. The administration Yl, the shielding of which is connected to ground, connects the outputs Sl and S2 of the transmitter EM with the inputs of the receiver R of 2. The line Y2 connects the output of the power circuit PP2 according to FIG. 2 with the input of the power circuit PPI, the output of which is connected to the second input RC of the gate PO.

In Fig. 2, which illustrates the receiving part of the inventive device, ± at the receiver R via its

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Outputs χ and y assigned to a first L'ecorUerschaltung DI, whose outputs X and Y emit information or timer pulses. The output X delivering the information has a common terminal with the input of the group identification shift register Rl, the inputs of the second parity flip-flop BP2 and the inputs of the memory element groups GO, Gl ... Qx, which are connected in parallel. The output Ύ emitting the timer pulses is at the input of a first monostable multivibrator BlM, the output of which has a common terminal with the first input of the two NAND circuits PEl and PE2, the timer input H of the parity flip-flop BP2 and the input of a second counter CR corresponding to the counter CE of Fig. 1 has.

The counter CR has outputs (connections I) which are at the inputs of the third NAND circuit PE3, and outputs J, which are connected to the inputs of the fourth NAND circuit PE4 are. This applies to all in the example described circuits related to the device according to the invention are NAND or NOR circuits, they are depending on the circumstances marked by the function AND or OR.

The output of the third AND circuit PE3 is at the input of the first bistable multivibrator BlB, the output of which is a at the second input of the circuit PE2 and whose output b is a common terminal with the second input of the circuit PEl, the switching device OC, which is not illustrated in the figure, and the input AD of the second decoding circuit DG, which is assigned to the register RI. The output of the circuit

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PE4 is at the input of a first OR circuit POl and at the input of a second reversing circuit 12, the output of which with the Input of a fifth AND circuit PE5 is connected, the other input of the circuit at the output Q of the parity flip-flop lies. The output of the circuit PE5 is connected to an input of the second OR circuit P02 via a third inversion circuit 13. The output of circuit P02 is connected to the input of a second monostable multivibrator B2M whose output Q is connected to an input of a third OR6 circuit P03, and the second input to this The circuit is at the output of the second inverting circuit, and the output of this circuit is connected to the second input of the first bistable multivibrator BIB connected.

The output of the circuit PE4 is also at the input of a third bistable multivibrator whose output Q with the The input of the power circuit PP2 and the input of a third counter CF is connected. The output of the counter is with connected to the input of a sixth AND circuit PE6, the output of which is connected to the input of a fourth reversing circuit 14 and on the other hand at the input of a second bistable multivibrator whose output is connected to the error indicator lamp LF is, and the output of the fourth inverter is connected to the second input of the circuit P02 '.

The output Q of the flip-flop B2M is also connected to an input RZ of the counting circuit CF.

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The output Q of the monostable flip-flop B3M is connected to an input P of the parity flip-flop BP2. The output of the power circuit PP2 is connected to the input of the power circuit PPI according to FIG. 1 via the line Y2.

Each output SO, SI ... Sx of the decoding circuit DG is each connected to a first input of an OR circuit PGO, PGl ... PGx connected, and every second input of the relevant circuits has a common terminal with the output of the Circuit PE2.

The output of the circuit PGO is connected to the input of the Memory MO connected, the output of which is connected to memory Ml, etc. belonging to the group GO: these consisting of shift registers Memories are assigned to the amplifier circuits CAO, CAl, etc., with each amplifier circuit having a memory element assigned and connected to a lamp L.

In a similar way, the output of the circuit PGl is connected to the input of the units of the arrangement Gl, and the output of the circuit PGx is at the input of the units of the arrangement Gx.

The following is a detailed description of the mode of operation of the transmitter-receiver arrangement described above, for example, namely, first of all, the mode of operation of the illustrated in FIG. 1 Broadcast part.

The filled buffer memory MT issues a control command DC to the transmission part, which is illustrated in FIG. 1

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Beginning of the cycle, i.e. at the input of the circuit PO, which this Forwards command to the input El of the bistable multivibrator BB. When this control command is received, the flip-flop changes their state and controls the timer HL, for example, at two microsecond intervals on the input E the counting circuit Cl outputs. This consists of bistable multivibrators, which are connected in cascade, and gives at the outputs A, B, C, D the status signals O and 1, respectively, which with each Move further in the binary code to denote their position.

These status signals are sent to the selection inputs at the same time A, B, C, D given the multiple couplers MXl to MXi. At The inputs EO to Em of each multiple coupler receive η information in the form of the states 0 or 1 present, i.e. as the absence or presence of an electrical potential, and the relevant information identify the idle or working state of the peripheral devices from the central logic unit to which the buffer memory MT heard, scanned cyclically.

Since the number η of messages received simultaneously from a multiplexer is less than the capacity of the Counting circuit Cl, namely depending on the digit or the binary number which characterize the position of the counting circuit, the multiplexers MXl to MXi give simultaneously to their Outgoing fnSl to Si in each case the information, its order corresponds to the number of steps performed.

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If it is assumed that the counting circuit Cl is in the position O at the given point in time and the selection inputs A, B, C, D of the multiplexer from the counting circuit Cl each receive the status signals OOOO, i.e., the binary digit. which corresponds to the decimal number 0, the multiplexers KXl, MX2 ... MXi switch on their input EO their single output Sl, S2 ... Si at which the status information 0 or 1 of the order 1, η + 1 ... ni + 1 occur. When the counting circuit Cl is in position 1, their outputs have the binary digit 0 0 0 1, which corresponds to the decimal digit 1, and the multiple couplers switch theirs Input El to output and give the information of the order 2, η + 2 ... in + 2 etc. from.

Of these i information, which at each step of the first counting circuit Cl on the lines Ll, L2 ... Li simultaneously issued and received at the inputs DO, Dl ... Di of the multiplexer MX, only one is im delivered at the same moment at the output S of the multiple coupler. This information depends on the binary digit used by the Outputs F and G of the second counting circuit C2 with a similar one Structure how the first counting circuit is determined, and this digit is assigned to the selection inputs F and G of the multiplexer HX given; a binary digit is output of the following order to the same inputs every time the first counting circuit Cl has performed a number of steps with which it sends the status signal 1 to the output

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D, where η is the number of each multiplexer received information is an even digit.

Assuming, for example, that each multiplexer receives sixteen pieces of information from the buffer memory can (n = l6), then the counter circuits Cl and C2 with four ripples and four outputs are used, each have a cycle of 16 steps. In Fig. 1, the counting circuit C2 makes 4 steps, and that of the counting circuits Cl and C2 existing counter CE has a total capacity of 64 steps.

During the first sixteen steps carried out by the counting circuit Cl, the counting circuit C2 is at its outputs F and G from the binary digit O O, and upon receipt of this Digit from the selection inputs A and B of the multiplexer MX, this selects the input O O, which is connected to the inputs EO to E15 received and at the output Sl of the first multiple coupler MXl released information 1 to l6 at the output S lets through.

During steps 7 to 32 of the counter CE, the counting circuit C2 moves to position 1, immediately if it is present the falling edge of the state signal 1, which is emitted from the output D of the circuit Cl at the beginning of step l6 and the circuit C2 outputs the status signals O and 1 at the outputs F and G. By receiving the binary digit 01 the inputs G and F of the multiplexer MX, the input Dl is selected and switched to the output S, whereby the? at the

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Output S2 of the multiplexer MX2 output information 17 to 32 are allowed through.

If the number of items of information output from the buffer memory is equal to the counting capacity of the counter CE, for example N = 64, 4 multiple couplers with l6 inputs (MXi = MX4) are used, each of which has l6 information at the inputs ED to Em. Only four information inputs (Di = D3) of the multiplexer MX are used. Otherwise, only the first two outputs F and G of the circuit C2 with the first two selection inputs F and G are available of the multiplexer MX. C2 counts each cycle of Cl, Cl scans 16 steps, and outputs F and G of C show 2 the following digits in sequence:

the binary digit OO during steps 1 through 16 of CE the binary digit 01 during steps 17 through 32 of CE the binary digit 10 during steps 33 through 48 of CE the binary digit 11 during steps 49 through 64. of CE, these binary digits with two values eb only require two output lines F and G to process all of the information.

When the total number of information is less than the counting capacity of counter C, i.e., for example, N = 55 (N = in + k = 4 x. L6 + 7), then a command to reset to zero is required to reset the counter after it has decayed the last information back to its original position

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bring to. In the device according to the invention, this command for resetting to zero is only available after an additional item of information N + 1 has been output to the input Ek of the last multiple coupler MXi possible, which immediately follows the input Ej, which has received the Nth information from the memory. This information N + 1 is passed on from the parity flip-flop BFl to the input Ek of the multiple coupler and to the receiver, where the information is a 0 or a 1 depending on the parity or non-parity of the status information output 1 acts.

The trigger stage BPl only changes its state at the output after the status information 1 has been received at the input, as described in part EPII (transmission of odd-numbered Signals) of the diagram illustrated in FIG. 3. As can be seen, for example, if there are three pieces of status information, 1 takes place one after the other on the inputs J-K of the flip-flop BPl in the order O, 1, 0, 0, 1, 1, G are given, their Output Q one after the other the states 0, 1, 1, 1, 0, 1, 1.

The flip-flop BP1, the output Q of which is in the state 0 at the beginning, remains when the first information is received of state 0 in this state. The output Q then arrives when receiving the second state information 1 in the state It remains in this state 1 when the third or fourth state information 0 is received, and it then arrives when it is received the fifth state information 1 in the state 0. By the sixth status information 1, the output Q enters again

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the state 1, and the seventh state information 0 changes not the state of the output, which remains in state 1.

If this information of order 7 is the last information N arriving from the memory, then information becomes of the order N + 1 and the state 1 at the output Q of the flip-flop BPl and passed to the receiving part. The state 1 of this Information denotes an odd number of status information items 1 to be sent out (three items of information from the State 1 in the present example).

In the case of an even number of status information items 1 to be sent out, as is the case with the transmission section MP for even-numbered signals 4 of the diagram according to FIG. 4, an even number (2) of status information 1 to be sent leads to the output Q of the flip-flop BPl in the state O when the Nth information has been issued, and the status signal 0 of the information W * * - 1 occurs at the output Q of the flip-flop and is delivered to the receiver, whereby an even number of status information 1 arriving from the memory is displayed will.

In the example the N = 55 delivered by the buffer storage Information, being the fifty-sixth (N + 1) on the input Ek of the multiplexer MXi given information can be a 1 or O, depending on whether the information contained in the 55 information Number of states 1 is even or odd.

When the fifty-sixth piece of information occurs on

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The counter CE has 56 steps at output S of the multiplexer MX executed. The state signals emitted at the output Q of the flip-flop BP1 are synchronized with the timer pulses HL. These delayed and calibrated pulses are sent to input H of the parity flip-flop BPl via the monostable flip-flops BMl and BM2 received, which make a delay or a calibration of the pulses. This ensures perfect operation the parity toggle guaranteed. This flip-flop only takes into account the information on the rising edge of the calibrated Timer pulse and, if necessary, changes the state only on the falling edge of the pulse in question. This becomes a unwanted operation of the multivibrator in the event of interference pulses avoided.

The diagram in Fig. 5 illustrates the operation of the parity flip-flop BP1 as a function of the at its input H calibrated timer pulses received. It can be seen from this that status information 1, its duration, for example 2 microseconds and corresponds to that of a non-calibrated timer pulse, the change in state of the output Q of the flip-flop at the end of the calibrated timer pulse. This one microsecond pulse, for example is delayed by half a microsecond and temporally superimposed on the information pulse in the same axis of symmetry.

The circuit PE, whose inputs are connected to certain outputs of the counter CE, opens when the Counter CE is in the step position N + 1 and triggers the bistable multivibrator BB, the outputs of which change their state,

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one holding the timer HL and the other setting the counter (inputs RZ of the circuits Cl and C2) to the zero position as well as the parity flip-flop in its initial state at the beginning of the cycle brings back (input P of BPl).

If the binary digit of 555 equals 1110 11 and that of 56 is 0 0 0 111 and the corresponding There are states at the outputs A to G of the counter, the inputs are used to determine the fifty-sixth item of information the PE circuit is connected to the last three wired outputs of the CE circuit (output D of Cl and outputs F and G of C2), and the circuit opens when the status signals 1 are received through all three inputs at the same time.

The calibrated timer pulses emitted at the output of the monostable multivibrator BM2 are also sent to the input E2 of the emitter EM given, while the information is given to the input El; the information and the timing signals are delivered mixed at the outputs S1 and S2 of the transmitter, namely in the in the diagrams of the signals of the emitter EM specified manner (Fig. 6). As can be seen from this, the signals of the inputs El and E2 are between 0 and + e, where e is a few volts, while the signals of the outputs Sl and S2 are between - e and + e and the transmitter acts as an amplifier at the same time.

The hatched pulses at El represent the status information 1 and that shown as a continuous line Impulses represent those of the state 0. The

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Status information 1 is at output Sl and the status information 0 are canceled at output S2, according to the duration of the timer pulses.

The receiver R in Fig. 2 receives the transmitter signals and these are at its outputs χ and y according to the. Diagrammer R of FIG. 6 delivered.

The decoding circuit DI separates the information signals from the timer signals and outputs them at the X outputs and Y ab (diagram DI, Fig. 6).

The timer pulses that the monostable multivibrator BlM delayed, are given on the one hand to the input of the counter CR and on the other hand to the input H of the register RI; the circuit PEl opens when the status pulse 1 of the timer occurs at its first input, because its second The input is also, as a result of the output b of the bistable multivibrator BlB, in state 1. By each of the The timer pulse received from the shift register RI is used by the shift register for storing one from the decoding circuit Information originating from DI released.

When the third timer pulse occurs, the counter CR moves to position 3 and thereby opens the door the circuit PE3 and the change in state of the outputs a and b of the flip-flop BlB. The output b reaches the state 0, the Circuit PEl closes and prevents storage the following information in the register RI, the

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only retains the first three pieces of information. As a result of the state 0 at output b, these three first pieces of information are simultaneously transmitted to the decoding circuit DG, and the first three pieces of information are output from the register RI, which in binary code designate the number of the element group to which the subsequent information of the cycle is to be routed . The decoding device DG converts the digit received at its inputs in the binary code ^% into a digit in the decimal code. For this purpose, it emits a status signal 0 at one of its outputs numbered in decimal code, with all other outputs being brought to status 1, and the output of status 0 is the one whose number corresponds to the binary-coded number.

If, for example, the register RI has transferred three binary-coded items of information into the decoding circuit DG, which correspond to the Ps.nimal digit O is entered at the output SO State control signal O to the first input of the circuit PGO, and the other outputs emit a state control signal 1, as shown in the following table, with inputs A, B, C of the decoding circuit DG are not illustrated in FIG.

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ϊ p

9 ϊ

9 9

I decoding circuit DG «

P. 1

9 9 9

9 9 9

J inputs | Outputs |

9 9 9

999 '. 9999 Γ

ξ C j B ν A \ SO j Sl j S2 ϊ S3 j S4 Sx ϊ

9 9 9 9 9.99 9

9 9 Ii ■ i n 9 . I II. Ill ■ I ^ ■ ■ Ϋ II V 9 I 9 HIIIII II « I 9

999 9 9999 ϊ

999 9 9999 9

^Λ 9 V 9 9999 9

\ ο j ο j ο j ο j ι j ι j ι j ι ι ι

ΫΫ9 9 9999 ϊ

SOjOJi j ι ο j ι ι ι ι ι

999 9 9999 9

V 9 9 9 9999 9

, ovi? o? ι? ι? o? ι »ι ι ι

99S 9 9999 ϊ

I o? ι S ι? ι I ι J ι! ο j ι ι I

999 9 9999 ϊ

999 9 9999 9

iljOJO? 1 ? 1 j 1? 1 J 0 1 I.

After the occurrence of the third piece of information, the
Output a of the bistable multivibrator BlB has passed into state 1, the circuit PE2 receives the signal of state 1 at its second input and opens after it has reached its
first input has received the fourth timer pulse. Her
Opening takes place only during half a status period 1
of each timer pulse, and the NAND circuit PE2 there
thus at the output Zuotandsimpulse 0 on all second inputs of the NOR ~ circuits PGO, PGl ... PGx, which work as NAND circuits. Only the first input of the circuit PGO
is held in the state 0 by the output SO of the decoding circuit DG; the PGO circuit opens, canceling the locking signal at the input of the GO group and the storage
the fourth item of information and the subsequent information output at the input X of the decoding circuit DI.

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The storage takes place in the memory MO, MI ... etc .; these memories, the number of which depends on the number of information per Cycle dependent consist of shift registers. The status information 1, which indicates the presence of an electrical potential are amplified by the circuits CAO, CAI ... etc. and control, for example, the lighting of the L lamps of the group.

The output b of the bistable multivibrator BlB · is at Occurrence of the third item of information changed to state 0 (opening of circuit PE3 during step 3 of the counter). By this change of state, a switching element OC, which is not illustrated in the drawing, is controlled and feeds the Lamps L of the groups concerned from the moment the information is stored in these groups. Through this this prevents the lamps from being undervoltage during reception.

The groups GO, Gl the operators to intervene in the connections and their sequence according to that of the subscriber connectors to monitor the assumed states of the self-connecting device. These subscriber connectors are centrally operated terminals that represent the extensions that form the subscriber devices. The connectors become cyclical scanned by a central logic unit, and their states are periodically stored in the buffer memory.

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Each delayed timer pulse which is given to the input H of the parity flip-flop BP2 is thus sent to the adapted to the inputs J-K of the flip-flop received information pulse; the operation of the flip-flop is the same as that the flip-flop BPl.

While receiving the N items of information of the cycle, the flip-flop BP2 outputs the same status signals at the output Q as are output at the output Q of the flip-flop BP1 (FIGS. 3 and U) .

These states have no influence on the circuit PE5, which remains closed as the second input of the circuit is not fed (circuit PE4 closed).

When the information N + 1 is received from the output Q of the flip-flop BPl and which is either a 1 or a 0, depending on the odd or even Number of states 1 contained in the N information to be sent, the flip-flop BP2 gives state information 0 at the output Q, as can be seen from the part REI (reception of odd-numbered signals) of the diagram of FIG. 3 and from the Part REP (reception of even-numbered signals) of the diagram of FIG. 4 emerges.

The status signal 0 output at output Q and accordingly the status signal output at output ζ} of flip-flop BP2. d-h- after the flip-flop BP2 received the information N + 1 has, thus overall indicates the perfect receipt

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catch the information. Because of this parity or not " parity control is any interference information or loss that may have been added to the sum of the received information information determines in which case the output Q of the flip-flop BP2 in the state 1 and the output Q in the state 3 passed.

Simultaneously with the receipt of the information of the order N + 1, the counter CR, the N + 1 timer pulses, goes has caught, to the state N + 1, whereby the opening of the circuit PE4 via the wires of the line J takes place.

Opening this circuit will be simultaneous on the one hand the resetting to zero of the counter CR via the circuit POl and on the other hand the change of state of the bistable Flipper BlB by the switch 12 and the circuit PO3 causes. The output a of this flip-flop goes from state 1 to state 0 and locks the circuit PE2, whereby the Closure of the circuit PG takes place, which prevents any new storage of interference pulses in the G-rappe G.

When the state change of flip-flop BP2 when receiving of the information N + 1 (1 at the output Q of the flip-flop) during the idle time of the counter CR in the position N + 1 is, the circuit PE5 opens, with its first input through the flip-flop BP2 in state 1 and its second input is brought to state 1 by the switch 12 «, The Circuit PE5 is via the changeover switch 13 and the circuit P02 oinon control pulse to the input of the flip-flop B2M, the

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changes its state for several milliseconds (Q arrives from O to 1 and Q from 1 to 0) j through this change of state is the opening of the power circuit PP2 through the Flip-flop B3M reduced, which emits a status pulse 1 at output Q as a result of the opening of circuit PE4, whereby the counter CF is advanced by one step. When the astable state of flip-flop B2M begins, it is reset of the payer's CP to zero.

If the parity or non-parity of the received Information is not correct, the output Q of the circuit BP2 is in the state 0, and the circuit PE5 remains closed, its second input having the state I during the opening of the circuit PE4. The output Q of the multivibrator B2M is in state 1, and output Q is the Trigger stage B3M gives as a result of the determination of step N + 1 of the counter CR (opening of the circuit PE4) a status signal 1 and the power circuit PP2 opens. The one at the exit The pulse emitted by this circuit is transmitted through the line Y2 applied to the input of the power circuit PP1 of FIG. The circuit opens and gives a command Repetition of the cycle on the input RC of the circuit POj by opening this circuit results in a change of state of the Flip-flop BB and the activation of the timer HL causes, the Irapulee cause the repetition of the information cycle. The attachment of this information to the inputs ED to EK the multiplexer MX1 to MXi remains during

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unchanged for several milliseconds. As can be seen from Fig. 2, the monostable multivibrator B3M is previously in the idle state arrives, and its output Q has changed to state 1 and has the flip-flop BP2 in the zu.Beginn of the cycle brought the existing state ^ the output Q of this flip-flop is achieved by a control pulse given to its input P. back to state 1.

Simultaneously with the opening of the circuit PP2 takes place by the change of state of the flip-flop B3M the advancement of the Counter CP in position 1.

If at the end of the reception of the information after the first repetition of the cycle, the parity or the non- " Parity of the information is still not correct, the flip-flop B3M opens the circuit PP2 again, so that a The second new information cycle begins while the counter CF moves to position 2.

When the parity or non-parity of the information is still not correct, the counter CF moves to position 3, the circuit PE6 opens and is operated via the Changeover switch 14 and the circuit P02, the flip-flop B2M, whose Output Q is brought from state 1 to state O for a few milliseconds and thereby every new opening of the circuit PP2 through the flip-flop B3M and consequently prevents any restart of the cycle. The output Q of flip-flop B2M temporarily goes from state Q to

309831/1086

State 1 above and causes the counter CP to be reset to zero »The change in state is due to the opening of circuit PE6 the second bistable flip-flop B2B takes place, which lights up the error lamp LF and then after elimination of the Error is returned to its original state by manual control.

It should be noted that the information provided by the buffer memory is renewed every ten milliseconds and the transmission time of an information cycle is 120 microseconds so that the start of a cycle in the event of an error in the interval between two from the memory given information sequences lies. The time of astability of the monostable flip-flop B2M of around 8 milliseconds with the time interval defined above.

In the event of an undesired interruption of the reception of the information or time pulses during a cycle in which the counter CR does not reach the position N + 1, it cannot be reset to the zero position by the circuit PE4 which remains closed. The monostable multivibrator BM4, which is constantly regenerated by the clock pulses during normal reception of the information, is triggered when the pulses are interrupted and brings the counter back to the zero position via the circuit P01 in order to be able to process the subsequent information cycles.

The processes that produce a status signal

309831/1086

O or · 1 at the output of the individual circuits of the device can also be triggered due to the opposite States 1 "or O, depending on the type of positive or negative logic unit used, run.

-Patent attestations-

309831/1086

Claims (12)

PATENT CLAIMS Multiplex transmission device, which is intended to "locally or at any distance information to transmit, which periodically reflect the state of central facilities, characterized in that, that it is equipped with a transmitting part, consisting of devices (MX) for the implementation of the simultaneously delivered Information in consecutive information, from devices (CE) for counting the sums of information, from devices (BM) for synchronizing the information as a function of timer pulses and for their transmission to a receiving part, from devices (BB) for resetting to zero at the end of the transmission cycle, from devices (BP) for outputting additional information for checking the Parity, and that its receiving part is equipped with devices (R, 01) for receiving or decoding the sent Information, with devices for counting the number of information received during a cycle Devices (DG) for separating the first information and devices (PGo-PGx) for forwarding the following information functions on register groups (Go-Gx), which are determined by the first information, as well as with devices (B3M) for Resetting the count to zero if there is an incomplete number of received information. 309831/1086 2. Apparatus according to claim 1, characterized in that its receiving part also is equipped with devices (Rl) for separating the first information from the information sequence of a received Information cycle, with devices (DG) for decoding the first pieces of information that designate a memory group (Go, Gx), which is intended to receive the following information of the information cycle, with devices (Mo, M1) for Storage and devices (L) for displaying the following information of the information cycle in the identified Storage group (Go), with devices (BP2) for checking the parity or IT non-parity of the information (B2M, B3M), which remain on hold until the following information cycle and a requested retransmission of the information cycle in the case of correct reception of the information forbid, and with devices (CF) that are used to assist If the parity is not correct, several requested successive information cycles to carry out the counting received cycles and displaying the error, if it persists. 3. Device according to one of the claims for counting the sums of the simultaneously delivered, periodically from the buffer memory supplemented information and an additional one, on the spot at the end of the cycle depending on the Sum (N) of the scanned information produced information, characterized in that 309831/1086 that it has a parity flip-flop (BP1} whose inputs (JK) are connected to the output of the last multiple coupler stage (MX) and whose output (Q) is at an input (Ek) of the last multiple coupler (MXi), the input being one order (k) which is immediately above the order (j) of the input (Ej) which receives the Nth information of the buffer memory, the outputs of the counter (Ce) being connected to the inputs of a circuit (PE) whose Output at the input of the bistable multivibrator (BB) is connected in such a way that the message N + 1 given to the input of the first multi-coupler stage is scanned at the output of the last multi-coupler stage and that at this moment after the counter E + 1 has carried out steps, the The circuit opens, causing a change of state of the flip-flop stage, which stops the timer, ie the advancement of the counter, via a first output and the reset via a second output causes the counter to zero, and the additional information N + 1 has the state O or 1, depending on the parity or non-parity of the state information 1 contained in the information sum (N) that is output from the memory and during a Cycle of the counter is scanned. 4. Device according to one of claims 1 to 3 for synchronizing the information as a function of the Timer pulses and their transmission to the receiving part, characterized in that they have two 309831/1086 has monostable multivibrators (BM1, BM2) connected in series, where "at the input of the first flip-flop with the output of the timer and the output of the second flip-flop with the input (H) of the parity flip-flop (BP1) and the input (E2) of the transmitter (EM) whose other input (E1) is common to the inputs (J, K) "of the parity flip-flop, the outputs (S1, S2) of the transmitter are connected to the receiving part of the device by a coaxial line, and the first monostable multivibrator the timer pulses delayed and the second monostable multivibrator calibrates the timer pulses so that the Axis of symmetry of each timer pulse with that one each sampled information coincides, whereby the operation the parity flip-flop and the transmitter is carried out synchronously when each scanned information occurs and the calibrated Timer pulses which coincide with the scanned status information 1, after their amplification on the output (S1) of the transmitter and the sampled information, which coincides with the sampled state information O, after amplification to the other output (S2) of the transmitter, which further transmits this information to the receiving part. 5. Device according to one of claims 1 to 4 for receiving and decoding the transmitted information, characterized in that its receiving part has a receiver (R) which is a decoding circuit of the information (DI) is assigned, whereby the receipts! the signals emitted by the special after amplification at the output 309831/1086 outputs and the decoding circuit at an output (X) the scanned information and at another output (Y) emits the calibrated timer pulses, and the pulses on a first monostable delay flip-flop (B1M) is given are in such a way that the timer pulses at the output of this flip-flop are delayed in time and with respect to the decoded Information to be adjusted. 6. Device according to ejnem of claims 1 to 5 for Separation of the first information from the information sequence of a received information cycle, characterized in that that it is equipped with an identification slide register (Rl) whose information input with is connected to the output of the information decoding circuit (DI), and to two logic NAND circuits (PE1, PE2), whose first input has a common connection point with the output of the first monostable multivibrator (B1M) and with the Has the input of a counter (CR) and its second inputs each at a corresponding output of a bistable multivibrator (B1B) lie, the second input of the first circuit at the second output (b) of the flip-flop and the second input of the second circuit at the first output (a) of the flip-flop, one input of which is connected to the output of a third NAND circuit (PE3) is connected, the inputs of which are connected to the outputs of the counter (connections I) with which a step is determined whose number corresponds to that of the first information to be stored, the output of the 309831/1086 first circuit via a first reversing circuit (11) at the input of the timer (H) of the identification register is connected, so that during the first steps of the counter the first information, which contains the output of the group to be reached in binary code, is stored in the identification register e ingas as their storage is due to the opening of the first circuit during the first steps of the counter is enabled, the circuit then closes and the second circuit closes as a result of the change in state of the bistable flip-flop opens due to the opening of the The step is determined which corresponds to the last item of information to be identified in the group. Device according to one of Claims 1 to 6, for decoding the first information identifying the group intended to receive the following information of the cycle, characterized in that it has a group decoding circuit (DG) associated with the group identification register (Rl) is, as well as group circuits (PGO-PGx) which are assigned to the groups (GO-Gx) of the corresponding order, namely one circuit for each group _y with the second input of the circuit each having a common terminal with the output of the second ITAND Circuit (PE2) and whose first inputs are each connected to an output of the decoding circuit (DG) in such a way that the order of the output corresponds to that of the circuit, the second output (b) being the bistable 309831/1086 Flipper (B1B) with a decoding release input (AD) of the Decoding circuit (DG) is connected such that through the first change of state of the flip-flop (B1B) simultaneously the opening of the second ITAND circuit (PE2) and the release of the The group number is decoded using the group decoding circuit at the outputs the group number stored in binary code in the identification register in a decimal code converts, with a single output of the group decoding circuit emits a state control signal O, which indicates the opening of the Circuit causes the access to the identified group, and with the two inputs only this circuit are in state O, while the first input of the other circuits has state 1 in each case. 8. Device according to one of claims 1 to 7 for storing and displaying the following information of the Cycle in the identified group ,, thereby characterized in that each group has a number of memories consisting of shift registers (MO, MI ...) whose The number is sufficient to include the following information of the cycle and has the same number of amplifiers (CAO, CA1. ".), which are assigned to the memories, each memory element of a memory for storing information serves and each assigned amplifier element at its output connected to a lamp (L) the display of an information, -tion makes each group arrangement a storage release input (AE) and the inputs have a common terminal 309831/1086 with the output of the corresponding circuit of the group, and each group has an information storage input and the inputs have a common terminal with the output (X) of the information decoding circuit (Dl), and the second output (b) of the bistable multivibrator is connected to a switching element (OC) in such a way that the opening of the Switching of the group, the storage of the information is released and the first change of state of the bistable multivibrator of the switching element that feeds the indicator lamps of the stored information. 9. Device according to one of claims 1 to 8 for counting the number of information received per cycle and for monitoring the parity or non-parity of the information, characterized in that it has a fourth NMD circuit 0? E4) for determining the end of reception of each received information cycle and a parity flip-flop, (BP2) similar to that of the transmitting part, the inputs of the circuit for determining the end of the cycle are connected to the outputs of the counter (CR) (lines J) which are used to determine step N + 1> in accordance with the information received Έ - ¹ - 1, the output of the determination circuit being at an input of a first NOR circuit (P01), the output of which is connected to the input (RZ) for resetting the counter to zero, and the output of the detection circuit via a second reversing circuit (12) on the one hand with an input of a fifth NAND circuit (PE5) 309831/1086 is connected, which simultaneously monitors the number and parity of the information, and on the other hand at an input of a third ITOR position (PO3), the output of which with the second Input of the bistable multivibrator (BIB) is connected, another input of the monitoring circuit (? E5) with the Output (Q) of a parity flip-flop (BP2), similar to that of the transmitting part is connected, and that the inputs (J, K) of this flip-flop with the output (X) of the information decoding circuit (Dl) and its timer input are connected to the output of the first monostable multivibrator (B1M) in such a way that the detection circuit upon receipt of the information (F + 1) of step N + 1 opens and thereby the reset of the counter to zero and the change in state of the bistable multivibrator as well as the opening of the monitoring circuit causes if the parity or non-parity of the received information is correct, in which case state 1 of the output of the parity flip-flop with that of the output of the second inverting circuit (12) during the opening of the detection circuit (PE4) of step N + 1 of the counter coincides, and the state change of the bistable multivibrator one after the other closes the second NAND circuit (PE2) and one circuit of the group (PG) that provides the input the group locks, so that the storage of StSrimpuls is prevented from entering the group that has stored the information intended for display. 309831/1086 10, device according to one of claims 1 to 9 for delaying the following information cycle and to prevent a requested transmission of the information cycle when the information is received properly, characterized in that it has a second and a third monostable multivibrator, the input of the second monostable multivibrator (B2M) is connected to the output of the monitoring circuit (PE5), namely via a second M) R circuit (P02) and a third switch, the output (Q) of the second multivibrator at an input of a power circuit (PP2 ), the output of which is connected to the transmitter, and the output of the third monostable multivibrator (B3M) at the output of the determination circuit (PE4) of step Έ + 1 of the counter and the output (Q) of this multivibrator with a second input of the power circuit is connected in such a way that the second monostable multivibrator during the opening of the monitoring circuit The dead time between the normal reception of two successive information cycles, the opening of the power circuit (PP2) is prevented by a third monostable multivibrator and this circuit prevents any new cycle from running due to its blocking. 11. Device according to one of claims 1 to 10, with the presence of a reception error of the information (Parity or non-parity not in accordance with the transmitted or received information) of the information 309831/1086 cycle can be repeated, characterized in that its transmitting part has a power circuit (PP1) whose input is at the output of the power circuit (PP2) of the receiving part and whose output is connected to a second input of the ITOR circuit (PO) in such a way that, when the output of the parity flip-flop (BP2) of the receiving part emits a status signal (0) as a sign of the parity or non-parity of the entire received messages, which does not match the information sent, the monitoring circuit (PE5) is closed and the second monostable flip-flop (B2M) ) remains in the rest position and thereby the third monostable multivibrator (B3M) is caused to return this multivibrator to its initial state via its output (Q), which is connected to the input (P) of the parity flip-flop (BP2), and via the normal output ( Q) the third flip-flop to 'open the second power circuit (PP2), which the first power circuit (PP1) actuated, which gives a control signal to the NOR circuit (PO), which is similar to the control signal . The beginning of the cycle that is output from the buffer memory is effective, causing the renewed transmission of information during the fraction of an interval of the dead time that lies between two successive normal information cycles, i.e. during an interval in which the simultaneously transmitted information is present. the outputs of the buffer memory. 309831/1086 12. Device according to one of claims 1 to 11 for Execution of several repeated successive cycles (for example two), if an incorrect parity monitoring is present, for counting the received information cycles and for signaling nasty errors, if this has not been remedied is, characterized in that it has an error counter (CP), the input of which with the Output (Q) of the third monostable multivibrator (BiH!) Is connected and its output to the inputs of the sixth NAND circuit (PE6) is to determine the third step of the counter, the output of this circuit via the fourth changeover switch (14) and the second input of the second ITOR circuit (P02) is connected to the input of the second flip-flop (B2M) and the output of the sixth circuit (PE6) is at the input of a second bistable multivibrator (B2B), the output of which is connected to the Error lamp (LF) is connected, and the output (Q) of the second monostable multivibrator at the input for resetting the error counter (CF) is on ITuIl, in such a way that at each end of the cycle of the information counter (CR), if the parity monitoring fails is correct, the third monostable multivibrator controls the advance of the error counter into the next position, with the Advancement is made possible by having the second monostable Flip-flop (B2M) is in the idle state and the error counter at the end of the second repetition cycle in the position three arrives and causes the opening of the circuit (PE6), which is used to determine this position, as well as the excitation of the 309831/1088 brings about a second random flip-flop that locks the power circuit (PP2) and resets the error counter to zero "caused after as a result of the opening of the circuit to determine the third position, the change in state of the bistable flip-flop (B2B) has occurred that caused the error saves and lights up the error lamp, Device according to one of Claims 1 to 12 for resetting the information counter (CR) to zero as soon as an incomplete information cycle is received (number of information less than Ή + 1), characterized in that it has a fourth regenerable monostable multivibrator ( B4M), whose input has a common terminal with the input of the counter and whose output is connected to the input of a first NOR circuit (P01) in such a way that this flip-flop, its more stable. Quiescent state is maintained during the reception of the timer pulse train of a complete or incomplete cycle, is triggered at the end or when the cycle is interrupted, which in the former case has no effect, since the reset to zero by the circuit (PE4) for determining the step (N + 1) of the counter, while in the second case it causes the counter to be reset to zero so that the receiving section processes the following information cycles. 309B31 / 1086 Blank page