DE2205176C3 - Circuit arrangement with a control for keeping the target speed of a direct current motor constant - Google Patents

Description

(18; 50) reset to the starting position - 25 speed, there is no motor supply, i. H. it exists

the input (line 33; line 67) of the counter idle mode.

The known device is controlled d) the control signal derived from the speedometer signal generator (12) with control signals of variable duration and control signal with a constant delayed, -. 'Or-sign amplitude. An output signal from the decoder (27; 56) to the output signal from the decoder (27; 56) to the transmission of a deceleration when the nominal speed is exceeded is not provided. This results in a low motor supply (32) and the time constant of the control speed for the counter (18; 50),
It is the object of the present invention, which is portable (lines 24, 25, 26). Control to keep the speed of a

2. Circuit arrangement according to claim 1, to form 35 DC motor so that speed error marked that this corrected by the speedometer signaler with the greatest response speed encoder (12) derived control signal to which one can be.

output of a first oscillator-controlled counter The task mentioned is performed in a circuit

(17) is transferable, in the counting positions arrangement for keeping the target speed constant Control signals can be generated which lead to a single 40 DC motor according to the generic term of Angang (Ltg. 21) of a second oscillator-controlled saying 1 by those mentioned in its identifier Counter (18; 50), to an input (line 24, 25, features solved.

26) of a decoder (27; 56) and to a These enable control signals, their amplitude

Reset input (line 20) of the first oscillator and sign depending on the speed error of the controlled counter are transferable. 45 motor drive can be changed, d. H. the engine will

3. A circuit arrangement according to claim 2, wherein the speed occurring below the target speed characterized that len with increasing speed error with increasing

a) a first output (line 54) of the second os- the signal amplitudes driven and above oscillator-controlled counter (50) with one of the target speed occurring speeds at an increase input a third oscillator-controlled 50 mendem speed error with increasing signal counter (51) is connected, the counting amplitudes of which are braked. The time constant of the rain start the second oscillator-controlled treatment is considerably improved.

Counter can be switched on in its end position. The invention is described below with reference to in

b) an output (line 54) of the second oscillator- the embodiments shown in the figures Counter (50) explained with input 55 ago. It shows

a decoder (56) is connected, by Fig. 1 is a block diagram of a first embodiment

in the end position of the second oscillation form of the circuit according to the application

gated counter the decoding process order,

can be switched on, Fig. 2 is a flow chart which is used to explain the

c) Counter outputs (line 61,62,63) of the third r> o function of the device according to Fig. 1 is used,
oscillator-controlled counter (51) on Fig. 3 is a block diagram of a second Ausfüh-Dccoder (56) with the motor drive approximate form of the circuit according to the application, depending on the count of the third oscil-

'lator-controlled counter adjustable Mo- Fig. 4 is a flow chart used to explain the

gate supply (32) are connected. 65 function of the circuit arrangement according to FIG. 3 is used,

FIG. 5 shows the circuit arrangement according to FIG.

more detailed presentation,

Fig. 6 is a logic diagram for explaining the

Operation of the decoding network in Fig. 5, and

7 shows a feed circuit for a motor which is controlled via the four output AND gates in FIG will.

Fig. 1 shows a digitally operating control device in which the supplied to a DC motor Electricity is controlled. The motor 10 drives a load 11 and a digital speedometer signal transmitter 12. The output signals of the speedometer signal receiver 12 on the line 13 have a relatively low frequency, which also increases as the speed of the motor 10 increases. The signals on line 13 thus give the actual speed of the motor again.

The frequency of an oscillator 14 is assigned to the desired speed. This oscillator owns a high output frequency compared to the maximum frequency that occurs on line 13 Speedometer signals. The output of the oscillator 14 is via lines 15 and 16 to a first counter 17 as well connected to a second counter 18. The output signals of the oscillator can be dependent on of further control signals the two counters 17 and

18 advance.

The digital control device in Fig. 1 keeps the speed of the motor 10 essentially constant, only slight deviations from the target speed occur. The first counter 17 is like that built up that he after his release by a speedometer pulse on a line 23 up to its final value counts up and then on an output line

19 emits a signal. Between two tachometer impulses the counter 17 reaches in each case, i. H. also at maximum engine speed and thus maximum frequency of the speedometer signals, its final position. By the The signal then occurring on the output line 19 is reset again via a line 20 of the counter 17. In addition, this signal prevents the counter 17 from advancing again. The signal on the line 19 is still carried via a line 21 to an input of the second counter 18, which can now be switched on via the line 16 by the output pulses of the oscillator 14. This counter is only released when the first one after the occurrence of a tachometer pulse Counter 17 has been fully counted. The length of time between the occurrence of a pulse on the line 19 and the following tachometer pulse is a measure of the speed of the motor 10. If the status of the Counter 18 is relatively low when the following speedometer pulse occurs, then the speed of the Motor 10 too high. On the other hand, if the reading of the counter 18 is relatively high at this point, then the speed of the motor is below the setpoint.

The occurrence of a tachometer pulse on line 13 also causes a blocking signal for counter 18 on a line 22. The level reached by the counter 18 when this signal arrives is recorded. Furthermore, the speedometer pulse on line 13 causes the first counter to be released via line 23 17, as already mentioned. Thus, this counter can through the outputs of the oscillator 14 can be forwarded again. The outputs of the lower stages of the counter 17 are on lines 24, 25 and 26, which are connected to a decoding device 27. Which when switching of the counter 17 changing signals on lines 24, 25 and 26 and the invariable signals on the output lines 28, 29 and 3ö of the blocked Counters 18 are used to decode the status in the counter 18.

For the sake of clarity, there are only three stages of a counter with the decoding device tied together. Of course, any number of outputs from a counter can be sent to the decoding device, depending on the requirements be connected. Since the rotor of the motor 10 between two speedometer pulses a predetermined Angular distance covered and since the output pulses of the oscillator 14 have a fixed time relationship create, the recorded state in the counter 18 is a measure of the time that the rotor of the motor 10 needs, to cover a certain angular path. Thus, by decoding the reading of the counter 18 it can be determined whether the engine speed is too high, too low or at the desired speed Setpoint is.

The output signal of the decoding device 27 appears on a line 31 and acts on the motor supply 32 until the next speedometer pulse occurs. It also causes the reset of the second counter 18 via a line 33, so that it is ready for the next payment process. the The counter 18 is reset before a signal on the line 19 occurs.

Another way of decoding is to scan lines 28, 29 and 30, for example in connection with a digital-to-analog converter whose output signals supply the motor 32 control and reset the counter 18.

FIG. 2 serves to facilitate understanding of the mode of operation of the device in FIG. 1. The block 34 indicates the occurrence of a speedometer pulse. This impulse releases the first one Counter 17, as can be seen from block 38. This counter is therefore incremented, as in block 35 shows. The speedometer pulse also causes the second counter 18 to be held at the one just reached Stand as indicated by block 36. The decoding of the Status of the second counter 18 while the counter 17 is incremented instead, as indicated by the block 37 is indicated. The next operation is to reset the second counter 18 upon completion of the Decoding process (block 39). The motor 10 is also supplied as a function of the output signal the decoder 27 (block 40).

The first counter 17 next reaches its final reading, as shown in block 41. This will make the triggered in the blocks 42,43 and 44 processes shown. These are the resetting of the first counter 17 to its initial value, the release of the second counter 18. so that it begins to count, and the blocking of the first counter 17. The second counter 18 is switched on until the next tachometer pulse occurs, as shown in block 45. The span between blocks 34 and 45 corresponds to a certain, angular path covered by the moving part of the motor 10. For example the speedometer signal generator Deliver 12 500 impulses when the rotor rotates through 360 °. The frequency of the oscillator 14 is 2.25 MHz, for example.

Fig. 3 contains the block diagram of a second embodiment of the claimed device, in which the second counter 18 from FIG. 1 is replaced by two separate counters 50 and 51. As far as the individual

5 6

nen parts in FIG. 3 in their mode of operation with such parts is indicated by the dashed line 70. Here

from Fig. 1 match, if they are identical, the next tachometer pulse occurs before the counter

Provided with reference numerals. The output of the oscillator 50 has reached its final state and the counter 51

14 is via lines 52 and 53 with inputs that begin to count. This means that the speed

Counters 50 and 51 connected. The counter 50 will be 5 above the setpoint. For the decoding,

by means of a signal on the line 21 for the counting advance, the status of the counter 50 is selected and it

gear released, d. H. when the first counter 17 is active, the motor 10 is correspondingly supplied.

has reached the final score. In the same way, the second possibility is indicated by the dashed line

Counter 51 indicated by a signal on a line 54 released 72. The engine runs too slowly here, like that

give when the counter 50 reaches its final reading io that the counter 50 has reached its final reading before

Has. the next speedometer pulse arrives. This will make the

As has already been explained with reference to FIG. 1, selection of the counter 50 for the decoding is canceled.

If the speed of the motor 10 is too high or too low (block 74), the selection continues now

be low. The signal on line 19 is also used by counter 51 for decoding (block 76) and

Via a line 55 to an input of a deco 15, the counter 51 begins to count (block 77). The next

diervorrichtung 56 out. This signal brings the ste event in the described time sequence

Decoding device in a state in which one is then the occurrence of the next speedometer pulse,

It is assumed that the engine speed is too high. On as block 78 indicates.

this state is explained in more detail below. Between blocks 34 and 71 and 34 and 78

went. 20 has the movable Ten of the motor 10 each

When the next speedometer pulse occurs before the same distance traveled. However, the time interval counter 50 has reached its end and a signal is valle different. For the case of the block 71 indicates via the line 54, then a short time interval indicates that the motor has run too rapidly changing signals on the lines 24, 25, 26, while for the case of the block 78 and the fixed signals on lines 57, 58 and 25 longer time interval means that the speed is low to 59 for decoding the fixed position. The decoder 56 is able to use the counter 50. If, on the other hand, the current state is to be recognized and the motor speed of motor 10 is lower than required, feed 32 should be controlled accordingly,
then before the arrival of the next speedometer in the Fi g. 5, further details of the Einrichpulses of the counter 50 are brought to its final state, 30 device according to FIG. 3 shown. In addition to the means by which a signal appears on line 54. These are for regulating the motor 10 while it is running. There is not only the counter 51 for the counting process in FIG. 5, but also means for the start-up process of the Moffrei, but it is also shown via a line 60 on gate. During the start-up process, an input of the decoding device 56 remains in place for as long as a bistable trigger circuit 88 is transmitted. As a result, the decoding device is in a 35 th state until a counter 91 is no longer brought to the state in which too low a speed is at its highest level. During the Andes engine is assumed and thus the signals running process, the engine is constantly fed, so that on the lines 24, 25 and 26 with the signals, its speed quickly from standstill to about the desired on the output lines 61,62 and 63 of the counter Value increases.

51 used to decode the counter reading 40 If during the subsequent regulation of the speed

will. the motor is running too fast, then a bistable trigger

If the motor 10 runs too fast, for example, then gerschaltung 103 is set and a counter 105 is in Bewird the motor supply 32 from the decoding device when a tachometer pulse arrives. Through the getung 56 influenced via the line 64 in such a way, set trigger circuit 103 the section 119 that the motor 10 is braked. The strength 45 of the decoding device 56, which at too high a rotation Braking is dependent on the size of the numbers that is effective in being able to stand Deviation from the prescribed speed. Is to be decoded in counter 105. When the speed is too on the other hand, the speed is too low, then depending on is low, then there is a bistable trigger circuit 90 The speed of the state in the counter 51 of the motor 10 is set stronger and the counter 91 carries out the counting process driven. 50 when a speedometer pulse arrives. The set

Via a line 65, which leads to the lines 66 trigger circuit 90, it enables the section 118

and 67 are divided from the output of the decoder of the decoding device 56, which is too low

Device 56 also returns pulses to the speeds effective, the status of the counter 91

Counters 50 and 51 supplied. This provision has to be decoded.

follows before the occurrence of a signal on line 55. The input signals for the device follow

19 so that the counters 50 and 51 for the next Fig. 5 are given by a start signal on a

Are ready for counting. Line 81, a forward signal on line 82

Referring to the flowchart in FIG. 4, a reverse signal on line 83 will now be up

the operation of the device in Fig. 3 in more detail. A signal appears on line 81 when the engine is running

explained. The individual blocks are to be put into operation with the same 60 10. At the same time will

Reference numerals such as those in FIG. 2 denote a signal on one of the two lines 82 and 83

if they have the same function. According to given that determines the direction of rotation of the motor.

Block 68 in FIG. 4 is used to select the counter. A feed circuit for the motor 10 is in the

50 for decoding when the counter 17 is shown in FIG. The engine 10 can by a

Has reached the end position, ie a signal on the line 65 bridge circuit with the four transistors A ₃ B, C

55 in FIG. 3 occurs. The block 69 indicates that the and D are fed in both directions, so that

Counter 50 then starts counting. For the further he can run both forwards and backwards.

There are two options. One of them The conductivity state of the transistors in Fig. 7

is determined by the output signals of the four AND gates 84, 85, 86 and 87 in FIG. An output of AND gate 84 means "forward slow", which brings transistors A and D into the conductive state to drive motor 10 in the forward direction. The output of the AND gate 86 means "backward slow" and it brings the transistors B and C into the conductive state, so that the motor 10 is driven in the reverse direction. The output signal of the AND gate 85 means "forward fast" and causes the forward speed of the motor 10 to decrease 5, by changing the direction of the energy supplied to the motor by making transistors B and C "conductive. The signal at the output of AND gate 87 means" reverse fast "and brings transistors A and D in the conductive state, whereby the reverse rotation of the motor 10 is slowed down.

When starting, it is necessary to continuously supply energy to the motor 10 so that the duration of the Acceleration to about the desired speed is as short as possible. The start-up process is carried out by the bistable trigger circuit 88, which is set by a start signal on line 81. Through this a further trigger circuit 89 is actuated in such a way that depending on the desired direction of rotation one of the AND gates 84 or 86 becomes transparent. The trigger circuit is also activated by the start signal 90 is set, thus enabling one of the two AND gates mentioned to be switched through.

Another effect of the start signal is that the counter 91, which corresponds to the counter 51 in FIG is brought to its highest level. As long as this counter maintains this level, the trigger circuit 88 remains in the set state, i. H. the start-up process continues. Through the As the motor accelerates, the tachometer pulses follow at ever shorter intervals. As long as the speed is less than 95% of the desired value, the counter 91 remains in the state that no signal is generated on line 92 when a speedometer pulse arrives on line 93. The AND gate 94 therefore remains blocked. However, when 95% of the desired speed is reached, that will AND gate 94 permeable, whereby the trigger circuit 88 is reset and thus the start-up process is terminated. The control of the motor 10 is now carried out under the action of the described Control device.

The output of the speedometer signal generator 12 is fed to a pulse-shaping network 95, the Output is connected to an input of an AND gate 96, via which the pulses from the oscillator 14 are fed to an eight-stage counter 97. The speedometer pulses are still transmitted over the network 95 and an OR gate 98 are fed to the reset inputs of the counter 97. By the speedometer impulses the bistable trigger circuits 89, 99 and 100 are also set.

The increment of the counter 97 takes place until it is its Has reached the end position and generates an output signal on line 101. This creates the trigger circuit 99 reset again, so that the AND gate 96 for the oscillator pulses via line 102 locked and the counter 97 is no longer incremented. By the output signal on the line 101, the trigger circuit 103 is also set and the trigger circuit 100 is reset. The AND gate 104 thus becomes permeable to the oscillator pulses, which are now transmitted via an AND gate 106 the three-stage counter 105 advance.

If the engine runs too fast, the next one hits

ίο Tachometer pulse on before the counter 105 reaches its final reading has reached. The speedometer pulse sets the trigger circuit 100, which thereby sets the AND gate 104 blocks and thus prevents the counter 105 from advancing. Furthermore, the trigger circuits 89 and 99 set by the speedometer pulses. Switching the trigger circuit 99 opens the again AND gate 96, as a result of which the oscillator pulses can reach the counter 97 again. The changing The reading of this counter is decoded together with the recorded reading in the counter 105 so as to determine the period of time in which the trigger circuit 89 remains in the set state. This State causes one of the AND gates 85 and 87 to be conductive and the feed circuit in Fig. 7 is controlled accordingly.

The mode of operation of the decoding device 56 is described below with reference to FIG. The upper section 119 is used to decode the status of the counter 105, while the lower section 118 is provided for decoding the status of the counter 91. The output line 108 of the Decoder 56 is fed to one input of an AND gate 109 (FIG. 5), while the other The input of this AND gate is connected to the output of the trigger circuit 99 via a line 110 is. As long as the AND gate 109 is conductive, the trigger circuit 89 is not reset. After completion of the decoding process and when a signal appears on line 111 at the output of AND gate 109 becomes that of the two trigger circuits 90 and 103, which are set in State is, reset again, and thus the assigned counter 91 or 105 is also reset. If, in the normal course of counting, the counter 91 is turned on, i. H. the counter 105 its final reading has reached, the counter 105 is already reset via the line 115. A signal on the Line 112 connected to the input of section 119 of decoder 56 indicates that the trigger

circuit 103 is set. The reading of the counter 105 is transmitted via the line 113 to the decoding device entered. This sets up various AND gates in section 119 of the decoder prepared. The outputs of the lower stages of the counter 97 are via a line 114 to the decoding device 56 out and connected there to one input of all AND gates. To this The reading held in the counter 105 is decoded as the counter 97 is incremented, and it appears an output on line 108 which turns AND gate 109 on. In this way the motor 10 is braked until the counter 97 has reached 5.

If the engine speed is below the target value, then the counter 105 generates a signal on the line 115 when it reaches its final state which blocks the AND gate 106 and thereby prevents the counter 105 from being incremented any further

will. The signal on the line 115 also resets the trigger circuit 103 and the trigger circuit 90 is set. This makes the AND gate 116 permeable to the pulses of the Oscillator 14, so that now the counter 91 is incremented. By a subsequent speedometer pulse the trigger circuit 89 is set, whereby one of the two AND gates 84 and 86 is turned on will.

The motor 10 is now fed, which lasts until the counter 97 reaches the status of the counter

10

91 has reached. When the trigger circuit 90 is set, a signal appears on the line 117, which all AND gates in the section 118 of the decoder 56 is supplied (Fig. 6). The stand in Counter 91 is entered into the decoding device via line 120. It is believed that the reading of the counter 91 should be twelve. There is therefore a drive of the motor 10 via one of the AND gate 84 or 86 until counter 97 reaches the value

ίο has reached 12. Then the trigger circuit 89 becomes reset again.

For this purpose 4 sheets of drawings

Claims (1)

1 2 The invention is based on a known scarf patent claims: tiiRgs arrangement with a control for keeping constant the drive speed of a magnet 1. Circuit arrangement with a regulation band (IBM Technical Disclosure Bulletin, Vol. 9, to keep the target speed of a 5 No. 10, March 1967, pp. 1315-1317). This facility DC motor by a connected from the motor contains a motor-driven speedometer signal transmitter driven speedometer signal generator and an oscillator and an oscillator-controlled counter, the counter-gate-controlled Counter whose counting periods are interrupted by periods caused by tacho signals. Tachometer signals are switched on, thereby If the oscillator-controlled counter marks its end position, that ίο tion achieved, it generates an output signal that one a) a constant drive current derived from the speedometer signal generator (12) for the drive motor control signal to a first, a counter is ineffective as long as the oscillator-controlled counter does not interruption-controlling input (line 22) to its starting position by a speed signal. and is reset with a constant delay. In this way a counting effect second period of the oscillator-controlled counter that controls the start of counting is a time nor input (Line 21) of the counter (18; 50), which enables a motor supply when a is portable, the period of the speedometer signals lasts longer than the counting b) Counter outputs (28, 29, 30; 57, 58, 59) over the period of the oscillator-controlled counter. This one Decoder (27; 56) with a state results when the engine speed is lower gate drive depending on the count on 20 as the target speed. The scheme works so long connected to the motor supply (32) are pulse-shaped drive signals of constant amplitude, tude until the motor reaches its nominal speed c) from the output of the decoder (27; 56) is enough. Between the individual drive signals and Control signal to a third, the counter at an operating speed that is higher than the nominal