DE1289871B - Circuit arrangement for comparing a reference frequency pulse train with a signal frequency pulse train - Google Patents

Description

1 2

The invention relates to a circuit arrangement frequency pulse and a signal frequency pulse equal to

to compare a reference frequency pulse train with occur in time. The circuitry is on

a signal frequency pulse train, in particular to respond to a pulse, and it can then be the case

Control of drives. occur that the engine accelerates even further

An electrical control device for 5 is known, although it has already reached its target speed. a drive, the two bistable multivibrators The next pulse will then contain in any case, the reference frequency pulse train being the one signal frequency pulse, so that the speed of one and the signal frequency pulse train of the other is immediately corrected again and the motor only for multivibrator is fed. The reference frequency - the duration of the time span between two pulses. Pulse train is supplied by a control generator. io was incorrectly accelerated further.
The signal frequency pulse train is z. B. from a tachometer generator, which is unaffected because of the shortness of its occurrence, or another significant but incorrect acceleration or pulse generator, which is coupled to the motor to be controlled, possibly also decelerating the motor. avoid, the invention provides that between the

The invention has for its object to provide a 15 source of the reference frequency pulse train and the

such a circuit arrangement in particular for regulating the first input of a flip-flop circuit and between

development of drives so that the speed of the source of the signal frequency pulse train and the

and the phase position of a motor, d. H. the rotary second input of the other toggle switch each on

position of its shaft at the speed 0, in the dependent delay element lies.

ity of a setpoint or the reference frequency ao now occur a reference frequency pulse and a can be adjusted precisely. In particular, if the signal frequency pulse is to be applied simultaneously, both can can be achieved that the drive power is not at the same time pulses to a flip-flop low speed is only switched on until it occurs, as there is a pulse from a VerMotor has reached its target speed, and that delay element is delayed. The first on the too high speed either no drive power or a braking power is switched on. switch the circuit and select the desired

Initiate using two bistable tilt or delay.
Circuits, with the reference frequency pulse train The invention further provides means which are intended to prevent the one and the signal frequency pulse train from hitting the other trigger circuit in a known manner, which will switch it into a state , the invention solves this problem by, would, in which it is currently located. This could lead to ambiguities and instabilities because the first input of one of the flip-flops. This means, the source of the reference frequency pulse train, must contain a feedback from the output of the switches and the second input of these flip-flops to their input, with a first coincidence gate connected upstream; 35 which is indicated at the input, in which addition the first input of the other flip-flop the flip-flop is currently located. Next upstream a second coincidence gate and which must be a gate at the input that evaluates this information-wide input of this flip-flop to the source tion and decides whether the relevant signal frequency pulse train is switched on; that pulse is fed to the flip-flop or back the first input of the first coincidence gate to the 40 is held.

Source of the signal frequency pulse train and the first. In detail, the invention provides that Input of the second coincidence gate to the source the first input of a flip-flop the reference frequency pulse train is connected; additional coincidence gate is connected upstream, its that the second output of the one flip-flop circuit is at an input to the source of the reference frequency second input of the second coincidence gate 45 leads pulse train, while the second input to connected; that the first output of the other is connected to the output of this flip-flop, Toggle switch to the second input of the first and that to the second input of the other toggle coincidence gate is connected and that the circuit also has an additional coincidence gate first output of a flip-flop and which is connected upstream, one input to the source of the the second output of the other flip-flop carries the 50 signal frequency pulse train, while the second Pulse sequences corresponding to the comparison value can be taken from the input to the output of this flip-flop are. is closed.

In this circuit arrangement, the two delay elements explained above

Pulse trains are compared with each other, and it can be replaced by advance circuits that

determined whether z. B. two or more reference 55 are in the path of the other pulse. Because it is

frequency pulses without interruption by an indifferent whether the reference signal pulse is delayed

Signal frequency pulse occur one after the other. This or the signal frequency pulse is accelerated. There

State means that the motor to be controlled is switching the acceleration of a pulse

Has not yet reached the target speed, so that it is technically not possible, it is provided that the

further drive power is supplied. If two 60 polarity of the impulses are reversed and after-

or several signal frequency pulses without subordinate gates either on the front or on

interruption by a reference frequency pulse behind - the trailing edges of the pulses respond,

each other, this means that the engine is its In detail, the invention provides that between

Has exceeded the target speed. In this case, the source of the reference frequency pulse train and the

the further supply of drive power under- 65 the first input of the second coincidence gate and

broke. Under certain circumstances, a brake can also be applied between the source of the signal frequency pulse train

be switched on. and the first entrance of the first coincidence gate

It can happen that there is a reference circuit in each case and that the first

3 4

two coincidence gates to increase the leading edges and speed. Until the arrival of the

the two additional coincidence gates on the backward first 5-pulse do not have the following i? -impulses

flank the further effect supplied to them by the sources on the state of the comparator

Addressing impulses. 10 according to FIG. 1 or the one controlled by it

The circuit according to the invention is described below.

arrangement in its structure and in its radio The first incoming 5-pulse, however, is after

tion using the example of a short delay by the timing circuit 14 shown in the drawing

Embodiment further explained. passed through gate 22 to use the

In the following description of the drawings, flip-flop26 is switched to the state /). In order to

the circuit arrangement according to the invention in general the drive power of the motor is switched off,

called my frequency comparator. The Kippschal- A 5 "pulse does not arise because the gate 18 is only

These are called flip-flops. The coincidence is opened when the flip-flop 26 through the

gates are simplified gates and the delay 5 'pulse is flipped. Since the timer 14 safely

members are more generally called timers. indicates that the 5 "pulse does not appear until the

Fig. 1 is a block diagram of the frequency 15 5 pulse at gate 18 has decayed, this retains

comparison circuit of this invention; Flip-flop 24 remains unchanged in its state.

Fig. 1A is a block diagram of an application because the motor is still running at one speed

the circuit of Figure 1 in a motor control; runs below the setpoint, the

F i g. 2 is a block diagram of a second motor- following input pulse being an iMmpuls, which is the

control for the circuit of FIG. 1; 20 opened gate 20 and as i? "- impulse that

Fig. 3 is a timing diagram of the pulse and flip-flop 26 toggles to state C, whereby the

Signal sequences at various points when the block circuit breaker to the motor is switched on. With

Circuit diagrams of Figures 1 and 2; every incoming 5-pulse the drive

Fig. 4 is an electrical diagram showing the power cut (the flip-flop 26 is in the

complete set-up for a frequency comparison as state D switched) for the time between

circuit according to FIG. 1 shows. a 5-pulse (if the delay is due to the

The description of the operation of Fig. 1 timing circuit 14 is neglected) and the and 2 can be best understood when one passes the following / i pulse. Thus, it is also referred to the pulse time diagram according to FIG. 3 refers. increasing speed of the motor, the subsequent For this description, it is assumed vallen that of the 5 pulses and 30 frequency, the number of inter-frequency comparator 10 of FIG. 1 used to increase, in which abgewird the driving power, a reference sequence of pulses R with one is switched. The power output signal is filtered at a constant repetition frequency with a motor speed before it is fed to the motor. As a result, the pulses 5 supplied to the motor by a transducer 29 35 power will steadily decrease when the speed, which is mounted on a motor 30, approaches the setpoint in the motor.
F i g. 2 is shown. Furthermore, the output C of the At full speed, the 5-pulse flip-flops 26 are used to lag the drive the .R-pulses just by the time to deliver the energy for the motor to be controlled. When it is necessary to supply the motor with power, in this case the frequency comparator 10 of 40 will correspond to its load. That is, R and Fig. 1 for regulating a motor speed 5 pulses have the same repetition frequency are used. Of course, however, the output C des is out of phase by an amount which the flip-flop 26 does not normally determine the required load on the motor. Can deliver a phase shift energy. However, it can be used to practice with the λ-pulses, that the phase will be changed, a circuit breaker on and off 45 with the 5-pulses changes by the same amount; th, so that a power is supplied to the motor, so the phase relationship remains constant as long as it corresponds to the state of output C. the load is not changed. So that both

Assume that the flip-flop 24 is in the phase and speed of the motor

stood A and the flip-flop 26 is in state D , so precisely regulated.

the first .R-pulse through the gate 16 with a 50 is the speed above the specified

small time delay corresponding to the setpoint, so is the repetition frequency of the 5 pulses

Timing circuit 12 can be passed through. This larger than that of the λ-impulses; so there will be two

Impulse forms an i? 'Impulse and switches the 5 impulses to occur, which are not caused by an .R impulse

Flip-flop 24 in state B. By being interrupted. The first of these two 5 pulses

Flip-flop 24 is switched to state B , 55 the drive power is switched off as explained above.

the gate 20 is opened, so that the following i? pulses switch and the flip-flop 26 in the state D

be let through and result in! {"- impulses. The bring. The second 5-impulse becomes the now opened

However, the first λ-pulse could not pass gate 20, form a 5 "pulse and that

happen because the timing circuit 12 brings the toggling of the flip-flop 24 into state A. For the

Flip-flops 24 in the state B until the decay 60 following λ-pulse, the gate 20 is blocked (because the

of the ^ -pulse delayed. Flip-flop 24 is in the A state and gate 20

Since the motor initially locks at too low a speed), so that the drive power is not

running, the next input pulse will be switched again. The motor can only be switched on

be a .R-impulse. This second .R-impulse will become that when two Ä-impulses immediately

Now open gate 20 pass and follow as i? "- pulse 65. The first iMmpuls switches the flip

Flip the flip-flop 26 to the C state. On flop 24 in state B, the second switches that

Transition of flip-flop 26 into state C, flip-flop 26 into state C, causing the motor

drive power is supplied to the motor in order to supply its power again. That way will

5 6

achieved with this circuit arrangement that the flip-flop26 switches to the state!) or not No power is supplied to the motor when it is running at (too low a speed assumed). the end running at excessive speed. F i g. 3 it can be seen that in this way a switching

It should be mentioned at this point that the process at output C can fail. That means output A for the operation of a brake for the to 5 only that a very small additional part controlling motor can be used, since the drive power was switched on for a short time A is only given if it becomes too high. The effect on the operation of the speed has set. If the entire circuit can be almost neglected, a DC motor can be turned off. Since only two S-pulses, which are used in a sequence, gear A , the motor receives a voltage io not interrupted by an i? can bring up speed by reducing the drive power for the desired value. It should generally be switched off for an appreciable period of time, it should be noted that there is no risk of the coincidence of a F i g. 1 four outputs are provided, namely the 15 R and a 5 pulse the state of the outputs that are too high. (4, B, D and C. These four outputs can trigger speed. This is understandable and can be used in different ways In comparison, it is of particular importance when different types of regulation for the motor are watching the motor being braked at too high a speed.

the in F i g. 1 is shown, used very flexibly 20 In the same way, in the case of the excessive will. Speed, the drive power is not

From the above description it can be seen that it switches before two impulses in a sequence is important that the flip-flop 24 do not hit the state A that is not interrupted by an S-pulse than one that is too high is. When an S-pulse has stopped at a speed at the same time. In particular, when a pulse occurs, it can mean that the flip-flop 24 in state B must hold the ambiguity the flip-flop 24 for a period until two successive ones work differently than in Fig. 3 is shown. The 5 pulses that arrive that are not interrupted by a jR pulse flip-flop 24 will only be a superfluous one. The delay circuit 14 perform switching operation. This, however, is necessary to ensure that the flip-30 drive power is not switched on, since this is not toggled into state A by the flop 24 before output C of the flip-flop 26 is switched. To such a condition occurs. Without the timing circuit, a signal for the drive of the motor at output C 14 there is the risk that the gate 22 and the flip-flop will be received, two impulses do not have to work under flop 26 so fast that the gate 18 is opened and broken by an S-pulse appear. But that is when the 5-impulse is still pending at this gate. 35 is only the case if the speed is too low. In this case, the flip-flop 24 would be activated by a. The timing circuits 12 and 14 are switched to their states for the individual S-pulses. In a similar manner, the timing circuitry is particularly useful, and is normally used every 12 at excessive speed, that the drive speed control system for a motor is not turned on until two ^ pulses 40 are used. The timers 12 and 14 are due to arrive, which may not be interrupted by an S-pulse under practical use. Without the timing circuit 12, if the repetition rate of the R and 5 pulses were some, there would be a risk that a single pulse would be the flip kilohertz. The timing circuits will, however , not be required to switch flop 24 to state B as quickly as it would if the switching speed that the same i? -Flop 26 in state C for duration of the occurring pulses. If the time the switch, whereby the drive power of the motor is required, an i? Pulse through the gate 16 would be switched on. to let, plus the time it takes to

The circuits according to FIG. 1 and 2 provide logic the flip-flop 24 from state A to state B circuits in the combination that such 5 ° to switch is greater than the duration of the λ-pulses, coincidence problems are avoided. That is, the gate 20 cannot be opened until the simultaneous occurrence of an R and A pulse has subsided. The timing circuit 12 would therefore not be required for an S-pulse at any point in time in the system.

does not cause any malfunctions or the described When taking into account the above detailed working method changes. The essential characteristic, 55 spelling, is understandable that im assumed by the circuit shown in FIG. 1 coincidence application of the simple motor control die Problems are solved is that either two of the functions of the timer circuit 14 are to do it S pulses or two λ pulses in a sequence ensure that the amount of the must occur to the state of the regulation essential performance a steady function of the motor speed to change. 60 speed is assumed (assumed to be too low

It is true that in the case of the too low amount). In a similar way, the timer circuit 12 speed of every 5-pulse the drive power to ensure that no drive power is input turns off. However, this power is switched on if the engine is running at too high a genur for the time between a 5-pulse and the speed is running. This ensures that the following Ä-pulse switched off. If a 5-pulse occurs, the motor has only been brought to too low a speed with a JR pulse at the same time, then it must be switched on before the power is switched on again the mode of operation of the drive control is not significant. In the arrangement of FIG. 1, in which the change can occur, regardless of whether the drive power is only controlled by output C,

7 8

will always work with the falling edge or by ramping up 16 and 22 synchronism

too low speed reached. The effect of the trailing edge of the pulses. Thus appears behind

of these two delay circuits is that an open gate 16 at the end of a / ^ - pulse

Disturbances of the motor speed very quickly and a 'signal. However, if instead of the

are precisely regulated. 5 delay circuit 12 an inverting circuit

Timers 12 and 14 are desirable between the source of the / Ü pulses and gate 20 and functional, but not essential. (note: not gate 16) switched and gate 20 like this The time switches are supposed to prevent that it is set up with the front edge of the one at the same time If a JR- and an S-pulse hitting i? -Pulse occurs, a '-pulse becomes ses both pulses are generated simultaneously on a flip-flop an- io with the trailing edge of the input pulse come and this creates an ambiguity and thus later than a ii "impulse. That would be worth it. The flip-flop would not indicate at all or would indicate that the i? "Impulses precede the i? 'Impulses overturn wrong state. In the case of short impulse rushes, which has the same effect as lagging sen and / or slow-working flip-flops with the i? 'pulses. In addition to the one just mentioned 15 reverse circuit becomes a second reverse circuit Probability that two impulses occur simultaneously between the source of the 5 impulses and the gate 18 kick and cause any damage. The delay circuit 14 is then omitted. small amount. The function is the same as above

The shorter the impulses, the smaller the amount that has been described.

Probability that an R and an S pulse 30 The frequency comparison circuit 10 of FIG

enter at the same time. was previously used in an engine

A speed control system is described for slowly operating flip-flops. The incoming one Impulse has no effect until the multiple description has been assumed Flip-flop from one state to the other so that output C is the only power control signal is switched. Is a short impulse before ending »5 is. That would be exactly true if an engine was too this switchover time has already subsided, it remains to regulate, at which there is also enough friction forces without effect. pedal to reduce the speed of the motor

But even if an S and a / M pulse decrease equally, if the drive power is switched off and arrives at a flip-flop in good time and then z. B. was. However, if the circuit is to be applied inadvertently to an S-pulse when accelerating the motor, the relatively high inertia deliberately tilts the flip-flop and has deceleration and low friction, it may switch desirably, this will have no adverse effects. The only consequence is that the circuit breaker has to be operated from the brake if it has switched too high and the power supply to the motor has reached speed. For this purpose, for the arrival of the next i? Pulse, output A can be used to prevent a break. Because of the braking mechanism due to the S-pulse control, as shown in FIG. 1A representing the delay will this next}? - im- is set.

pulse arrive the faster, so that the motor This braking mechanism 27 can either a

then is accelerated again. The only consequence will be mechanical brake or a switch that controls the

is only the one that the motor reverses the polarity of the current in the motor coils when it reaches 40. In Fig. 3 is closed

do not continue to observe its setpoint speed that a signal is only generated at output ^

accelerates, but is decelerated briefly until it appears when the motor 28 is too high speed

accelerated again. achieved.

For the circuits according to FIGS. 1 and 2, it is used in connection with the arrangement according to FIG

exact operation is important that the input 45, the logic of the frequency comparator 10 is visible-

pulse trains R and S borrowed from sharply delimited pulses, which is provided in order to avoid the errors

exist. This can be done by standard pulse shaper - by coincidence between R and S pulses -

circuits that cannot be shown or described here. If output A for the control

ben are achieved, which is used the tion of a brake 27 shown here, it is very important

Stages are connected upstream. In practice, it is 50 tig that no signal appears at this output,

Width of the R and 5 pulses about V2 micro- if the speed is too slow. The logic

Seconds if the repetition frequencies in the Be of the frequency comparator 10 ensures that there

range from 200 kHz or less. If the two S-pulses are in a sequence without interruption

Repetition frequency of the signals in the range of 1 MHz by an i? Pulse must occur before the

the width of the R and 5 pulses can be switched to state A on an un- 55 flip-flop 24. if

be decreased by 0.1 microsecond. If the speed is too low, the coincidence between

Delay circuits 12 and 14 are appropriately provided that an R and an S pulse occurs

measure, if they are designed for a delay, only the flip-flop 26 unnecessarily in the

which corresponds at least to the pulse width. State D switched with an insignificant

From the way in which the coincidence gates work in relation to the 60 effect on the average output,

on the impulses it is evident that the lead is also switched from the output. The flip-flop

circuits in place of the delay circuits 24, however, does not change its state, and that is

Can be used to achieve the desired impact. Since the engine with too

to achieve. Advance gearshifts that are to run at low gearshift speeds must follow the

are technically not feasible, are due to the situation that an R and an S impulse at the same time

Reverse shifts and a certain work occurrence, one pulse before the next 5 pulse

wise the gate circuits formed, which occur the reverse. This initially following iWmpuls switches

circuits are connected downstream. The gates back to the entire frequency comparator

Claims (4)

9 10 correct state for too low speed. point 34 to +10 volts and the output voltage E0. Accordingly, there is no risk that the brake is 0 volts. Accordingly, if the speed is too low, the output E0 can be switched analogously to the signal C in due to the coincidence between R and S pulses, this coincidence being considered during FIG. Time to low speed inevitable 5 However, if the speed is too high this will occur. Output B alternately to ground and to a transducer 29, which is normally connected to +20 volts, while it includes outputs in a tachometer, which constantly carries ground potential on the motor 28 of this operating mode, outputs the pulse train 5, which is a measure is the voltage at junction 34 for the speed of motor 28. io fluctuate between ground and + 10VoIt. If there are some conditions in which there is a voltage at connection point 34 earth, the motor speed control system only decreases the output of output E0 by 10 volts (applied from the right is desired, which switches on the braking power to the left) and can thus be used as an output -Under these conditions only the output A voltage of -10 volts will be considered. Not used to apply the brake. This corresponding will occur at too high a speed in the conditions can occur if the regulated time in which the state is switched on and thus the motor drives a system whose load is decreasing, the state B is switched off, a negative span when the speed increases. This occurs if there is a voltage at output E0. This voltage has some applications in the chemical industry. an opposite or braking current. It is obvious that in such a case ao through the winding of the motor 33 will result. Thus, the comparator 10 according to FIG. 1, the output arrangement according to FIG. 2 is an example that can be used in this system in that the braking power to be controlled is simply connected to both the drive and the controlled motor at the output ^ Motor is supplied. Every time the engine can run too fast. When the speed is reached, a signal A is output, which is shown in FIG. 4 is a complete circuit diagram of a comparator 10 which can be used to switch on any braking mechanism. 1 are can. shown in FIG. 4. However, FIG. 4 shows the from the above description of the various uses of advance circuits 12.4 and 14 Λ, outputs which can be used according to FIG. 1, instead of delay circuits. The advance can be seen that the frequency comparator 10 of these 30 circuits 12 ^ t, 14 A are simple inverted scarf invention can be used very flexibly. In lines through which the gate circuits with the connection with F i g. 1, three arrangements of the rising edge of the input pulse were described instead of the one for the motor control: switch falling edge. 1. The use of output C for switching on. Although this invention has been described in connection with its drive power, whereby the motor is applied to the control of speed and the desired speed, phase of a motor, this is intended 2. the use of the output A to describe a motor to be understood in such a way that the frequency comparator circuit 10 with a negative load on the desired frequency comparator circuit 10 has an output which is used to control an oscillator or each 3. The use of outputs C and A, so that any frequency generator can be used, the motor drive and braking power. In general, this invention is a simple guide, whereby the motor is both at frequency comparators with a logic that the high as well as low speed error that is governed by coincidence between the two. to be compared input signals occur A fourth operating mode is to be reduced to a minimum in connection with 45 and various outputs are shown in FIG. In FIG. 2, four resistors are provided, which stand alone or combined with one another, R1, R2, R3 and R4 , which can all be used to have a large number of pre-exactly the same resistance value. To regulate directions. The device can be one of the resistors R 3 and R4 is a voltage arrangement that directly generates a frequency of 20 volts, so that at the junction of the 50 such. B. an oscillator. The arrangement of both resistors can also be +10 volts. The outputs have a property, the size of which is connected directly to the winding of any transducer converted into a frequency by a motor 33 through the use of output E _{0 of the comparator.} In the can be described.
The arrangement is the voltage at outputs B.
and C of the comparator 10 in the switched-on connection 55 stood + 20 volts. Patent claims: So if the speed is too low the
Voltage at the output constantly +20 volts, and the Voltage at output C alternates between 1st circuit arrangement for comparing a +20 volt and ground. If the output C has 60 reference frequency pulse train with a signal of +20 volts, the voltage at the frequency pulse train, in particular for the control binding point 34, is obviously also + 20VoIt (because of drives, using two the voltage at the outputß + 20 volts), while flip-flops, the reference being the voltage at junction 31 +10 volts frequency pulse train of the one and the signal. Correspondingly, the output voltage E ₀ 65 frequency pulse train of the other flip-flop can be assumed to be +10 volts (is supplied from the right to the left, thereby marked on the left). If the output to ground net that the first input of the one toggle switch, the voltage at the connection circuit (24) to the source (R) of the reference frequency pulse train is switched on and the second input of this flip-flop (24) is preceded by a first coincidence gate (18); that the first input of the other flip-flop (26) is preceded by a second coincidence gate (20) and the second input of this flip-flop (26) is connected to the source (S) of the signal frequency pulse train; that the first input of the first coincidence gate (18) is connected to the source (5) of the signal frequency pulse train and the first input of the second coincidence gate (20) is connected to the source (R) of the reference frequency pulse train; that the second output (J3) of the one flip-flop (24) is connected to the second input of the second coincidence gate (20); that the first output (D) of the other flip-flop (26) is connected to the second input of the first coincidence gate (18) and that the first output (/ 1) of a flip-flop (24) and the second output (C) of the other ao Flip-flop (26) the comparison value corresponding pulse sequences can be taken. 2. Circuit arrangement according to claim 1, characterized in that between the source (R) of the reference frequency pulse train and the »5 first input of a flip-flop (24) and between the source (S) of the signal frequency pulse train and the second input of the other Toggle circuit (26) each has a delay element (12 or 14). 3. Circuit arrangement according to claim 1, characterized in that the first input of the one flip-flop (24) is preceded by an additional coincidence gate (16), one input of which leads to the source (jR) of the reference frequency pulse train, while the second input leads to the output (A) this flip-flop (24) is connected, and that the second input of the other flip-flop (26) is also preceded by an additional coincidence gate (22), one input of which leads to the source (S) of the signal frequency pulse train, while the second input is connected to the output (C) of this flip-flop (26). 4. Circuit arrangement according to claim 1 and 3, characterized in that between the source (R) of the reference frequency pulse train and the first input of the second coincidence gate (20) and between the source (S) of the signal frequency pulse train and the first input of the first Coincidence gates (18) each have an inversion circuit and that the first two coincidence gates (18, 20) respond to the leading edges and the two additional coincidence gates (16, 22) respond to the trailing edges of the pulses delivered to them by the sources (R, S). For this purpose 2 sheets of drawings