DE2204144A1 - Method and device for the automatic detection of counting errors - Google Patents

Description

220AU4

310-18.238P January 28, 1972

SOCIETE ΰ'OPTIQUE, PRECISION, fiLECTRONIQUE ET MEOaNIQUE- SOPELEM

Paris (France)

Method and device for the automatic detection of counting errors

The invention relates to a method for the automatic detection of counting errors in an arrangement for Measurement of displacements by means of coded counting according to patent ... (patent application P 21 35 212.5) as well as on a Device for the automatic detection of counting errors in an arrangement for measuring displacements by means of coded counting, which is particularly suitable for carrying out such a method.

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Arrangements for displacement measurement by means of coded It is well known that machine tools are counted, for example with numerical control application that have a material or non-material measuring scale, for example is in the form of a split lane. A reading device consisting of a sensor moves in front of this measuring scale is constructed, which contains at least one analyzer, which emits a signal by moving it in front of the measuring scale, which, after being appropriately shaped in a device known per se, supplies a read signal. Such an arrangement is for example described in the main patent (in the main application). In particular, this arrangement has several impedance adapters, which form examples of signal conditioning stages.

If the sensor contains an analyzer, it is known that the combination of the η occurring at the output of the reading device provides Signals a measure of the position of the sensor relative to the measuring scale, that is, a measure of what is read by the reading device Kote / Ο-, in a reading code with η moments, which the Differentiation of 2n increments within each sub-step of the measuring scale is possible.

The measuring systems for displacement measurement also have a grid that generates pulses based on the read signals, each of which corresponds to a displacement of the sensor relative to the measuring scale by one increment. These impulses are in summed up by a digital counter to which a determination circuit to determine the direction of counting, taking into account the direction of displacement of the sensor and, if applicable, the position of the zero point is connected upstream on the measuring scale. Such a device forms the actual subject of the main patent (the main application). As is well known, the digital counter is made up of a series of binary flip-flops that are cascaded

+ (Measure)

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are arranged to one another and the output _{terminals of which supply a Kote C E} registered in the counter in a binary code, each output terminal corresponding to a bit for this Kote. Depending on the design and the use of the counter, the registered Kote can be represented in a pure binary code, in which the weight of each bit corresponds to the rank position for the output terminal, whereby this Kote can then be processed directly in a computer, or it is used in decimal counters with a decimal number that can be displayed via an indicator, in which the flip-flops are grouped by four per decade, with four outputs being connected to an indicator with ten positions via an adapter, represented as a binary coded number in decimal code.

The grid for the pulse generation can be constructed, for example, from a code converter circuit that transmits the read code with η converts moments into a code 1 from 2n and which is a determination grid for determining the direction of displacement subordinate, which emits an impulse in one sense or in the other with every change in the code.

Such a system obviously does not indicate the Kote C _T actually read by the reading device, but rather the Kote Cg registered in the meter; the position of the sensor is thus reflected by the number of pulses accumulated in the meter. It is therefore necessary to switch off faults that can lead to a registration of pulses in the meter that do not correspond to any displacement of the sensor.

Numerous systems have already been proposed for eliminating these disturbances. So is for example been tried, in particular the disturbances occurring at the input of the code converter through the use of

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avoid reflective codes. The strongest disturbances, however, occur at the input of the meter, and this one Disturbances are very difficult to suppress. It is therefore very important to identify the errors, i.e. the additional impulse registrations in the counter, which is not an actual displacement of the reading device, but rather non-eliminable disturbances on Input of the counter to be able to recognize.

Now that the counter commonly used operate in synchronism, it has been found that the errors occur in practice only in the decade with the lowest weight since the other decades are accessible only ¹ for very brief periods.

Therefore, for the elimination of counting errors, it is generally sufficient to use pulse registrations due to disturbances recognized in the decade with the lowest weight. On the other hand, it is advantageous if the operator receives information as soon as a Interference pulse is detected.

The invention is therefore based on the object of providing a possibility for automatic detection of counting errors in a Arrangement for measuring displacements by means of coded To create a count that sends information to the operator as soon as an erroneous interference pulse occurs added or subtracted.

According to the invention, the object is achieved by a method for the automatic detection of counting errors of an arrangement for measuring displacements by means of coded counting, which is characterized in that a read-off level C ₁ . from a registered note C _{77 is} deducted that the differer: between these two notes at the moment

BATH ORIGINAL

7 0 9 WU Ü / Ü ßR A

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of the measurement origin is stored and then permanently compared with a stored difference and that an alarm is triggered if the current difference and the stored difference do not match.

_{If a reading code with five moments and a decimal counter is used, the reading C T} supplied by the reading device and indicating the position of the sensor within one step on the measuring scale varies in the same way

L

Like the number of units of the level CL registered in the meter and displayed on its indicator, since this level C _E changes by one unit up or down each time the sensor is moved by one increment in one direction or the other.

If there is a difference between the reading C- and the number of units for the registered Cg at the start of the measurement, this difference must subsequently remain constant regardless of the movements of the probe, and a variation of this difference shows the registration in each case of glitches from the meter.

The invention therefore works with a permanent comparison of the Kote C _T read with the number of units for the

Lj

registered note CL. or in the case of one not decimal working counter with the digits with the lowest weight for the registered note, which is a note of the same format as the reading CL gives *.

A device constructed according to the invention has for this purpose a subtractor for subtracting the read-off note CL from the registered note C _E , a memory for storing the difference C _E -C _{L between} these two notes in one

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point in time selected as the measurement origin, a coincidence circle for determining the coincidence between the instantaneous difference C " - C- and a stored difference, and an alarm device which can be actuated by this coincidence circle in the event that there is no coincidence.

According to the invention, therefore, a device for the automatic detection of counting errors in an arrangement for measuring displacements by means of coded payment, in particular when carrying out the method according to the invention, with a measuring scale, with a reader with η analyzers, each of which emits a read signal when passing in front of the measuring scale , with a grid for generating counting pulses corresponding to a shift by one increment from the read signals, with a determination stage for determining the /, counting direction and with a counter for the counting pulses with a plurality of output terminals that jointly the Kote Cp, registered in the counter in a binary code and each correspond to one bit, the combination of the read signals j "indicating the reading Cote C _{1 by the} reader. In a reading code with η moments for the differentiation of 2n increments within each sub-step of the measuring scale, characterized in that it has a subtracter for the subtraction n of the read level Cj. from the registered note Cn, a memory for storing the difference C ₁ , - C, of these two notes in one as the origin for the '

Γι L

Reading selected point in time, a coincidence circle sum determining a coincidence between the instantaneous difference C _v - C _T and a stored difference and an alarm device that can be actuated by the coincidence circle in the event that there is no coincidence between the two differences.

According to a further feature of the invention, the

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registered note Cg, from which the read note CL is deducted is formed by the signal appearing at the first outputs of the counter ρ, where ρ is an integer that corresponds to the relationship Pp - 1 ^ η obeys.

In an arrangement for displacement measurement in which the reading code on the one hand and the code at the output of the counter on the other hand are compatible with one another, there is an advantageous one
Further development of the invention is that the registered Kote Cp and the read Kote C _T directly at the inputs of the
Subtract apply.

On the other hand, for a measuring arrangement for displacement measurement in which the reading code and the code at the output of the counter are not compatible with one another, it is preferred within the meaning of the invention that one of the registered notes C and the read off C. others through a code converter: u converting them into one with the representation of the first
Kote compatible code is present at the inputs of the subtracter.

In the case of a measuring arrangement with a floating zero point and a display ring: for the sign of the registered level Cg, finally it is preferred within the meaning of the invention that the registered KoI e Cp be actuated by the change in sign Complementary circles to complete this note C- on di® Basis of the counter output code is present at the input of the subtracter.

For the ". -Eii ere explanation of the invention is now
on a '"i -' ^ nr ^ ugte A ^ iifuhrungrlx-- 'games for an inventive aurrohHdetp device, which is shown in the drawing

BATH

, (j 'J ι: ■ - ν i ü! - ". ü /:

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are shown. Show in the drawing:

1 shows a diagram for the structure of a device designed according to the invention for recognizing counting errors in application to a measuring arrangement for measuring displacement without a floating zero point and with an even number of analyzers;

FIG. 2 shows a corresponding diagram for an analog device designed according to the invention for recognition of counting errors in application to a measuring arrangement with floating zero point;

3 shows a similar diagram for a device designed according to the invention for recognizing counting errors in connection with a measuring arrangement with floating zero point, which operates with a code of five moments and a decimal counter;

4 shows a corresponding diagram for the construction of an according to the invention trained device for detecting counting errors in a measuring arrangement for the Displacement measurement with a moment and

Fig. 5 shows an example of a with a erfindungsge.nS ¹ ? trained device usable adapter.

In the embodiment shown in Fig. 1, the measuring arrangement has a divided measuring scale 1 and a reading device 2 with four analyzers a, b, c and d and a shaping stage for the signals emitted by these analyzers, which are transmitted to their Output provides a code with four moments. The one from the reader The signals emitted are converted in a code converter matrix J5 into a code 1 from 8, the output signals of which a discriminator 4 for determining the direction of displacement of the reading device are fed, depending on the Direction of displacement emits a pulse at one or the other of its outputs, which is sent to the input of a binary counter 5 is fed. The trigger levels of the binary counter 5 can be set in Groups of three f. Η each be arranged, with the first three

BAD OBtGIMAL Ί O 9 O U O / O 5 8 k

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Flip-flops deliver the digit with the lowest weight for the Kote C _{E registered in the counter in an octal code at their output.}

In this case, the reading is obviously C, -in a code with four moments and the registered note C " expressed in an octal code. These two codes are not compatible with each other and therefore the reading code must be in one Code converter matrix 6 are transformed, which also brings the read Kote C, into an octal code.

Then the two nodes C " and C _{T are assigned to} the two

JSj L

A subtracter 7 is fed to it, which supplies _{the absolute value for the difference C E} - C _{L at its output.} The three bits of the difference CL, - C ₁ expressed in octal code. are fed on the one hand to the input of a coincidence circle 8 and on the other hand each to a memory 9, which in turn applies the stored difference to the other input of the coincidence circle 8. The memory 9 is actuated via control buttons for advancing or resetting the counter. Therefore, every time the counter for a certain position of the reading device is set to zero or preset to a certain Kote, as often happens in machine tools with numerical control, the memory 9 takes the current difference C _E - C, on and passes it on to the input of the coincidence circle 8. If the reading device then shifts, the instantaneous difference Cg - Cj. in the coincidence circuit 8 continuously compared with the instantaneous difference stored at the beginning of the measurement, in the event of a lack of coincidence between these two differences, which occurs when a glitch is recorded in the counting sense or counter to the counting sense in the counter

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occurs, the logic level at the output of the changes Coincidence circle 8 and actuates an alarm device 10, for example by a light indicator or by " a sounder can be formed. In this way, the operator is automatically informed as soon as a Counting error occurs. He can then easily determine the direction of the error that has occurred and this error consider.

In the more complete scheme of FIG. 2, for the Construction stages 6, 7 and 8 each illustrate useful embodiments.

For example, the four-moment reading code may be of the following type:

0 : 0 0 0 0 1 : 1 0 0 0 2 : 1 1 0 0 3 : 1 1 1 0 4th : 1 1 1 1 . 0 1 1 1 6 - 0 0 1 1 7th '0 0 0 1

2 ² 2 ¹ 2 ° 0! : 0 0 0 1 y • 0 0 1 2 ! 0 1 0 3 ' s 0 1 1 4th ! 1 0 0 5! 1 0 1 6! 1 1 0 7 s 1 1 1

The transfer T takes place in the code converter matrix 6 convert this reading code into an octal code according to the following logical equations:

S ² . d,

2 ¹ = bd + db

f \ mm «™

2 = from + cd + from + cd

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In Fig. 2 is an exemplary embodiment for the code converter matrix 6 shows a form of implementation with an AND-NOT logic within the dash-dotted frame.

As indicated in FIG. 2, the subtracter 7 can contain an adder 71 which forms the sum of the registered note Cg and the complement Cj- of the read off note C _L. If the level Cj- is smaller than the level Cg, so the difference Cg - Cj- between these two levels is positive, the sum C "+ C _T results in a remainder of weight 2. This remainder is fed to the input of an EXCLUSIVE-OR circuit 72, which is also fed with the sum C "+ Cj, and this remainder is also fed to the input of an adder 73, which is also fed to the output of the EXCLUSIVE-OR circuit 72 switched on 1st. If there is a remainder, the EXCLUXrV-OR circuit 72 allows the sum Cg + C _L to pass to the adder 73, which adds a 1 and thus _{supplies at its output the sum C £} + C ^ + 1, that of the difference Cg - C ^ equals. If, on the other hand, the Kote Cj. greater than the level C _w , the difference Cg - Cj_ so negative and the sum Cg + Cj. less than 8, there is no remainder, and the EXCLUSIVE- ^ OR circuit 72 inverts the sum Cg + Cj ^ which appears at the output of the adder 73 without further modification. Therefore, the subtracter 7 delivers the absolute value for the difference C ₁₇ - C ₁ .. at its output in each case.

The memory 9 is made up of three type D flip-flops, each at its input D one bit of the difference Cg - Cj formed in the subtracter 7. received fed. These Difference is also applied to an input of the coincidence circuit, which for example consists of an EXCLUSIVE-OR circuit 8l

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is constructed with three gates, each on the one hand with an input of the subtracter 7 and on the other hand with the output Q the corresponding flip-flop in the memory 9 are connected. The logic level at the output S of an EXCLUSIVE-OR circuit is known to be coupled with the logic levels at their inputs a and b according to the table below:

a b S. O O 1 t-l 1 1 O 1 O 1 O O

This occurs at output S of the EXCLUSIVE-OR circuit logic level 1 always occurs when both inputs a and b have the same logic level, while the logic level Level 0 always occurs at output S when the two inputs a and b are at different logical levels lie.

If one counter by actuating a button 11 on a particular Kote or by operating a knob 12 to zero, a, one puts through an adapter I ^ a rising pulse edge to the input \ of the three flip-flops in the memory 9 at which the Let the logic level present at input D reach output Q. In this way, the inputs a and b of the three flip-flops in the EXCLUSIVE-OR circuit 81 are each at the same logic level, and if an AND-NOT gate 82 is connected to the outputs of these three flip-flops, the gate is located Output of this gate at logic level zero.

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change the logical levels at the outputs Q of the flip-flops not in memory 9, and the three bits of the difference Cg - Cj. remain so saved.

If a glitch occurs in the counter 5, the difference Cg - C, - changes by one unit, and one of the three am Output of the subtracter 7 bits output therefore changes its logic level. The exit of the corresponding gate in the EXCLUSIVE QDER circuit 8l therefore goes to the logical Level zero above, since its two inputs a and b are no longer on the same logical level, and it arises a logic level 1 at the output of the AND-NOT gate 82, which leads to the alarm device 10 being actuated. The operator can then count without stopping the machine tool for the registration of the glitch and take it into account, and it can be increased by creating a new one The pulse edge at input T of the flip-flops in memory 9 stores the new difference that is present at input D.

Fig. 2 illustrates the case of a measuring arrangement with a floating zero point. In this case the measuring arrangement is with a display circuit 41 for displaying the sign of the Kote read by the reading device, that of the respective corresponds to the position selected for the zero point, and equipped with a determination stage 42 for determining the direction of counting, which takes into account the sense of the displacement of the reading device and the sign.

As long as the reading device is in the positive range of the measuring scale and is moving towards the zero point, the counter must, as is well known, subtract the incoming measuring pulses, but after the zero point has been exceeded it must consider the same impulses as positive, so the counter must then count again and at this moment one kote

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specify the complement to the number based on the source code that would be displayed if the zero point had not been exceeded. The corresponding Devices for the counter are known and described in detail in particular in the main patent (in the main application).

Since the passage through the zero point the absolute value of the stored for a certain position of the reading device Difference Cg - CL does not change, the change in sign is allowed do not invert the counting sense for the Kote. One must therefore take into account for the Kote C ", which in the detector device will restore a constant counting sense from one end of the measuring scale to the other. This is the reason that a complementing device is used for the complementation on the basis which the Kote C ^, if the value is positive allows it to happen, but at .. negative value in its complement converts on the same basis.

In Pig. 2 also shows such a device, which in this case is made up of an EXCLUSIVE-OR circuit 51 and an adder 52. In the octal code illustrated in FIG. 2, the EXCLUSIVE-OR circuit 51 has three gates which, on the one hand, receive one of the bits of the code C _£ and, on the other hand, the indicated sign. The output of the EXCLUSIVE-OR circuit is connected to one input of the adder 52, the other input of which receives the inverted signal for the indicated sign.

In this way, as long as the reading device is in a positive zone of the measuring scale, the sign is Plus with the logic level 1, and this logic level is applied to the gates of the EXCLUSIVE-OR circuit 51, which then-

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the three bits of note C-. lets pass unchanged. Of the second input of adder 52 receives the logic level Zero, and therefore the level Cg goes through unchanged and arrives to the input of the subtracter 7

These processes take place down to the level zero, so they apply to the area of the measuring scale that is regarded as positive.

As soon as the level is exceeded zero, the line takes for the display of the sign, the logic level zero is displayed, and the sign minus is then displayed, and the Kote at the output of the counter 5, which should be 9, becomes 1. This Kote is applied to the input of the EXCLUSIVE-OR circuit 51, whose three goals are given a logic level of zero. The EXCLUSIVE-OR circuit 51 therefore inverts all bits the Kote at the output of the counter 5 »if this is negative.

The level zero corresponding to the negative sign is, however, transformed into a level 1 by an inverter 53, which is fed to terminal 2 of the second input for adder 52. This then forms the sum Cg +

For all codes with a base corresponding to the valence 2, the number Cg + 1 is known to be equal to the complement the base for the number Ck. When you have bits of greater weight when the Easis is not taken into account, the value that should appear at the output of the counter 5 is recovered, if there had been no complementation inside the meter as a result of the change in sign.

This difficulty does not, of course, arise in circuits without a change in sign as in FIG. 1.

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3 illustrates an embodiment for a device for counting error detection for a measuring arrangement that works with a decimal counter. In this case a reading device with five analyzers a, b, c, d and e is used, which gives a code with five moments. This read code is by a code converter 3 into a Code 1 converted from 10, and a discriminator 4 for the shift direction supplies the for each shift Reading device by an increment equal to one tenth of the step size ρ of the measuring scale one pulse.

As in the embodiment of FIG. 2, the measuring arrangement according to FIG. 3 has a determination circuit 42 for the Counting direction, which takes into account the direction of displacement and the sign indicated by the display circle 41 and the Counting pulses feeds the counter 5 either in the adding sense or in the subtracting sense. The counter 5 consists of a "" »Ige of decades, each having four toggle stages, which are each connected to an indicator 54 with ten positions, which is operated via an adapter 55, which each code coded in binary decimal code at the output of a decade the corresponding Can correspond to a decimal digit.

The code converter circuit 6 is connected to the five outputs of the reading device, the code with five moments in binary decimal code. The illustrated embodiment for the code converter circuit 6 works again with an AND-NOT logic.

In this way one obtains the reading C _T , the

J-I

corresponds to the position of the reading device within one step of the division of the measuring scale, at the output of the code converter circuit 6 in a binary decimal code

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speaking representation. This code corresponds to the one at the exit of the decade with the lowest rank for the counter 5-Hence the levels Cg and C- read off in the binary decimal code can be compared directly.

In the case of measuring arrangements without a floating zero point, the four outputs of the decade with the lowest rank for the counter 5 are directly connected to the subtracter 7.

The subtracter 7 in turn is as for the in Fig. illustrated case of an octal code composed of an adder 71, an EXCLUSIVE-OR circuit 72 and another Built up adder 73, which is the sum of the number appearing at the output of the EXCLUSIVE-OR circuit 72 and one possible remainder.

It goes without saying that this includes the EXCLUSIVE-OR circuit in the case of a code with five moments, four flip-flops. The same also applies to the memory 9 and the EXCLUSIVE-OR circuit 8l.

In the usual case that the measuring arrangement has a floating zero point, a complementing circuit similar to that described above in connection with the exemplary embodiment of FIG. 2 is used for the complementation to the base. This circuit is composed of an EXCLUSIVE-OR circuit 51, which allows the Kote C _E to pass unchanged when the value is positive. However, as soon as the reading device exceeds the zero point and enters the negative scale range, a logic level 1 is present at the inputs of the EXCLUSIVE-OR circuit 51, which causes the display of the negative sign, so that the EXCLUSIVE-OR circuit 51 the four at the end of the decade

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with the lowest weight in the counter 5 bits output inverted, and this level is applied to input C of adder 52 on the one hand and to terminals 2 on the other and 2- ^ of the second input of the adder 52,

O 2
whose terminals 2 and 2 are connected to ground.

In this way, if the value is positive, the value Cg passes through the EXCLUSIVE-OR circuit 51 and the adder 52 without any change and arrives at the input of the subtractor 7. If the value C _{1 is} -, on the other hand negative, the

js _ _

Adder 52 the sum 10 + C-, + 1. Since the quantity C-. known-

ü Ji

borrowed by inverting the bits from the size Cg, the expression 10 + C-, + 1 represents the complement of C _x

egg Jl

10. The feces have therefore been restored in this way, which at the output of the decade of the counter 5 would have the lowest weight if there was no change in sign would have given.

The above examples show that the described device for counting error detection can be used for all measuring arrangements can be used to measure displacement regardless of the code used.

Of course, the device can be very simplified if a code with one or two moments is used.

In Fig. 4 is an exemplary embodiment for such Device for counting error detection shown in which a Code is used with a moment. Such an arrangement can be used, for example, to count the revolutions of a itself always be used in the same sense rotating disk. In this case, the reading device has only a single one Analyzer, and there is no discriminator for the determination

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of the sense of entanglement, since the impulses through differentiation be won. The pulses are added up in a binary counter whose output 2 is connected to an adder 71 whose other input is simply connected to the output of the reading device via an inverter.

The adder 71 gives the expression C ~ + C _{T at its output}

on, and as in the embodiments described above, the EXCLUSIVE-OR circuit 72, which here contains only a single gate, inverts this sum in the event that there is no remainder, while there is no change in such a remainder Sum undertakes, the adder 73 forms the sum C _E + C ^ + 1, which, as is known, corresponds to the expression Cg-CL _{for the case that C E is greater than CL.} As in the exemplary embodiments described above, the output of the subtracter 7 therefore always has the absolute value for the difference

^C E " ^C L ^{available and} S ·

The remaining part of the device is of course also included Simplified in a similar manner, for example, the memory 9 contains only a single flip-flop and the coincidence circuit 8 contains only a single EXCLUSIVE-OR gate that goes over an inverter is connected to the alarm device 10.

Such a device for counting error detection would enable a parity check, which guarantees the detection of disturbances that lead to a registration of Run pulses in the counter and thereby change the parity for the number displayed at the counter output.

In the event that the reading device contained 2 analyzers which supply a code with two moments the reading code is still compatible with the code at the output of the counter without the use of a code converter device

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would have to find. Therefore, as in FIG. 4, the adder 71 would be connected directly, on the one hand, to the two outputs of the reading device and, on the other hand, ι
of the counter 5 be connected.

device and on the other hand with the outputs 2 and 2

The rest of the circuit would have to be modified slightly, and the EXCLUSIVE-OR circuits 8 and 72 would have two gates, while the memory 9 would contain two type D flip-flops.

This dual analyzer reader could be used in a simple counting system. The device the verification of the position of the reading device within an increment would then be used to detect counting errors the measuring scale and the detection and consideration of disturbances.

The circuit for the pulse generation could be built analogously to the corresponding circuit in Fig. 1 and 2, A recoding grid for recoding the code with two moments into a code 1 from 4 would have to be used.

In the case of a measuring scale with a floating zero point, a complementing circle could be used for complementation on the basis of an analog type to the type illustrated in FIG. 2, which are corresponding to the The above explanations can be used for all measuring arrangements that work with a code whose basis is the valence 2. is equivalent to.

In Fig. 5 an example of an adapter 13 is shown, which enables actuation of the flip-flop in memory 9. This adapter 13 is made up of two monostable tilting stages 131 and 132 with time constants Theta I and Theta 2 built up, the rebound phenomena at the contacts of the

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Suppress buttons 11 and 12 and deliver a falling signal with a constant level and from the falling signal Plank of this signal gain a pulse that allows the memory 9 to take into account the difference Cg - C_, which occurs at the output of the subtracter 7 at this moment. The adapter 13 is connected to the buttons 11 and 12 connected switches operated, which are connected to the input of the counter and one of the setting of the zero point and the other setting the counter on one as a baseline enable selected Kote.

The exemplary embodiments described above each relate to various commonly used codes, however, the counting error detection device constructed according to the invention can be used easily and independently of the code used in each case set up for any measurement set-up. Likewise, the device designed according to the invention can be used in any measurement arrangement, with the type of pulse generation and the type of meter used are irrelevant.

Likewise, those in FIGS. 2 and 3 can be illustrated Adapt schemes for logic circuits for code conversion to the respective application cases without further ado. In the same way can do that indicated in Fig. 3 using AND-NOT gates Construction scheme for the EXCLUSIVE-OR circuit 51 without further replaced by any other type for such a circuit. Finally, there are still a few in FIGS. 2 and 3 simple examples for the construction of complementing circuits to complement the registered Kote Cg on the basis shown, these circuits can easily be replaced by other circuits of this type, which are not necessarily provide a positive sign with respect to zero.

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The alarm device 10, which is designed in the form of a light display in the exemplary embodiments, can also be used without further designed differently and designed, for example, as a sounder.

. ¹ U Ii-U Ί / U 584

Claims (1)

.23-22CHU4 Claims. 1. Procedure for the automatic detection of counting errors at an arrangement for measuring displacements by means of coded counting according to patent ... (patent application P 21 35 212.5), characterized in that a read note CL is subtracted from a registered note C— that the difference between these two points is stored at the moment of the measurement origin and then is permanently compared with a stored difference and that in the event of a mismatch between the instantaneous Difference and the stored difference an alarm is triggered. \ 2.J Device for the automatic detection of counting errors in an arrangement for measuring displacements by means of coded counting, in particular when carrying out the method according to claim 1, with a measuring scale, with a reader with η analyzers, each of which when passing in front of the measuring scale Outputs read signal, with a grid for generating counting pulses corresponding to a shift by one increment from the reading signals, with a determination stage for determining the counting direction and with a counter for the counting pulses with a plurality of output terminals that jointly record the Kote Cg in the counter a binary code and each correspond to one bit, the combination of the read signals applying the code C _T read by the reader in a reading code with η moments for the differentiation of 2n incrementals within each sub-step of the measuring scale, characterized in that it has a subtracter (7) for the subtraction of the read level C _T from the registered note C _£ , a memory (9) for storing the difference Cp - C _{T of} these two notes in one as the origin 209840/0684 -24-2204U4 Tent point chosen for reading, a coincidence circle (8) for plaguing a coincidence between the instantaneous difference Cg - C ,. and a stored difference and an alarm device which can be actuated by the coincidence circuit (8) in the event of a lack of coincidence between the two differences (10) owns. 3. Device according to claim 2, characterized in that the registered index C ^ for the subtraction of the read index C _{L is} the signal occurring at the ρ first output terminals of the counter (5), where ρ is an integer such that the expression 2p - l £ η becomes. 4. Apparatus according to claim 2 or 3 for an arrangement with compatibility between the reading code on the one hand and the counter output code on the other hand, characterized in that the registered Kote C _£ and the read Kote CL. right away at the inputs of the subtracter (7). 5. Apparatus according to claim 2 or J> for an arrangement without compatibility between the reading code on the one hand and the counter output code on the other hand, characterized in that of the registered Kote C _£ and the read Kote CL one directly and the other via a code converter (6 ) for their implementation in a code compatible with the representation of the first Kote at the inputs of the subtractor (7). 6. Apparatus according to claim 2 for an arrangement with a floating zero point and a display circle for the sign of the registered Kote Cp, characterized in that the registered level C ^, via a sign change actuatable complementing circle (51, 52) to complete 0/0884 this Kote is present on the basis of the counter output code at the input of the subtracter (7). 7. Apparatus according to claim 5 * characterized in that the complementary circle to complete the registered Kote Cg from an EXCLUSIVE-OR circuit (5I) with ρ gates, each of which on the one hand with one of the bits of the Kote Cg and on the other hand with the sign indicating signal is fed, and is composed of an adder (52), one input of which is connected to the outputs of the EXCLUSIVE-OR circuit (51) is connected and its by a .zum sign display signal inverse signal excitable other input receives the base of the reading code. 8. The device according to claim 2, characterized in that the subtracter (7) has a first adder (71) for adding the registered and read nodes C ₁₇ and C _T represented in compatible codes, the outputs of which are each at a Egg. Yy Gate of an EXCLUSIVE-OR circuit (72) are switched on, which in turn is connected to the remaining output of this first adder (71) is connected, and a second adder (735) for adding the at the output of the EXCLUSIVE-OR circuit (72) and the any residual signal from the first adder (71) contains. 9. The device according to claim 2, characterized in that the memory (9) contains a plurality of flip-flops of the D-type, which are each connected to one of the outputs of the subtracter (7) and their T input either by switching or by resetting the counter (5) to zero. 209840 / Q584 - 2υ - 220AU4 10. The device according to claim?, Characterized in that the coincidence circuit (8) has an EXCLUSIVE-OR circuit (Sl), each of whose gates is connected to one of the outputs of the subtracter (7) and to the corresponding output of the memory (9) and an AND-NOT gate (82) which is connected to the outputs of the EXCLUSIVE-OR circuit (8l) and which in turn supplies the excitation signal for the alarms inr ich tune (IC '). BAD ORIGINAL 2Ü984Ü / 058A ft Blank page