DE2160327C3 - Device for analog-digital conversion of analog signals obtained by means of converters - Google Patents

Description

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TSmg according to claim 1, characterized in that the clock signal generator (48) has a pulse generator (46) which is coupled to the body that is thrown, st and the clock gj
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T ^ rSL ^^ the claims, und2,> 5 characterized in that the Analog-Dig: - I ₁ converter (54) has an addressing circuit (49) which is sent to the clock signal generator (48) for generating an addressing signal connected in response to a first clock signal, st, and that the analog-digital converter w at a second Takts.gnal with the conversion of the analog signal into a corresponding digital S.gna. begins.

4. Device according to claim, characterized in that that the memory is a digital memory (50) which is connected to the clock signal generator (48) and the addressing circuit (49) is that the digital memory (50) has a plurality of storage elements of which each contains a previously stored digital signal that one of the elements after it selected by the addressing signal and emptied m depending on a third clock signal received the corresponding digital signal, that further to the clock signal generator and

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10 1968 S_ in the »^. _{the present inventor} .

Very ^ "" ^e Allgen periodic eccentricities

Output variable for the duration of the clock penode

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5. Apparatus according to claim 4, characterized in that that the third clock signal from a time delay device triggered by the second clock signal (100) comes from the addressed storage element before the converter (54) has finished his cycle, extinguishes.

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The invention relates to a device for analog-digital conversion of analog signals obtained by means of converters, the periodically recurring eccentricities of a rotating body reproduce.

wenaungMüutii required that at of bodies this rotation takes place as far as possible, the eccentricity being maintained. Due to the ize results very frequently, since parts are only defined within certain areas Can produce and arrange tolerances but unbalance can also be achieved by storage unc 60 temperature influences can be caused in a rotating body, whereby these Ex centricities also do not remain constant and can change from time to time. This problem makes it necessary that a device for detecting eccentricities 65 deviations in the Rotatioi must detect, regardless of the cause or origin of the deviation. Such a device must then the changes in the deviations i

3 4

to the extent required over a period of time. Further advantages and details of the invention

correct, and the device must finally take care of those resulting from the sub-statements. In the now

The following description is an exemplary embodiment!

nen, so that they can be queried or described with reference to the "drawing. Es

can be accessed at a suitable time

nen. Fig.! a general block diagram according to the

There are converters available that are used in the invention.

Turn in connection with rotating bodies F i g. 2 a and 2 b graphical representations of the

generate an analog output signal, which contains the input and output signals in the device according to

Defined eccentricities. The application of this io of the invention occur.

However, the converter is very limited for various reasons. First, the output size of the guide form according to the invention, Converter in a control process on a real time base Fig. 4 a and 4 b. if this is along the displayed can hardly be used directly. Second, the joining line represents a deNatur of an analog signal. Problems relating to the FIG a storage and with regard to the retrieval for F i g. 3 and

later use. As previously mentioned, FIG. 5 a detailed functional block diagram

the eccentricities occur neriodically, which the necessary processes for

and lead to a periodic signal at the execution of the method according to the invention

speed of the converter. This error signal appears as 20 plays.

very irregular sinusoidal wave moving around a F i g. 1 shows a general block diagram

DC voltage value is offset. the invention. The rotating body 10 rotates

The invention listed in claim 1 lies in the direction indicated by the arrow 12 The task is based on a device for the representation of the Tung. A transducer 14 is near the perimeter of the body iodine To create error signal that a memory 35 pers 10 arranged, which is ideally concentric to a Backup and recall of the signal to a late axis of rotation 16 is. An error signal from the converter τη time allows. During each time period 14 passes through an amplifier 18 and appears the scanning signal thus becomes a digital signal, as a periodic analog signal according to the waveform represents, produces and forms the error signal according to FIG. 2a. A typical memory is shown in FIG. 2a. The scanning process is relatively smooth, 30 period indicated between lines 20 and 22. A therefore, the stored signals are also very accurate clock generator 24 generates sampling signals, which and up to date. In addition, a number of time periods are allowed for each period of the The device is used to ensure that the stored digital signals reproduce analog signals. A digital representation the memory synchronously with a subsequent lende device 26 responds to the clock signals Corresponding time period of the error signal is generated 35 and the analog signal to become a digital signal can be. As will be apparent to those skilled in the art. generate which is the size of the analog signal thus the device according to the invention can be reproduced for one during each of the clock periods. One use large number of processes. The counter storage device 28 has inputs with state of the invention can, for. B. used to do this are the clock generator 24 and the digital display, 40 connected to a display and a permanent recording device 26 to the diginung the concentricity of a processing workshop signal at one of the time periods assigned To be provided individually. Next can save the subject of the memory location. With successive invention the dizur Use to get. To control the process, a digital signal is retrieved from the memory location or to eliminate the eccentricities. Generated at a 45 and at the output 32 of the storage element 28 Another general use case exists which will be. If the digital output signals are in a Requirement to record the eccentricities in order to obtain a sequence cumulatively, so Process control signal for adjusting the mechanism, they put a number of values in a real one to be provided. The creation of a predetermined level, as shown in FIG. 2b is illustrated. Dades The device can then generate balance with the aid of the device 50 over any period of time of the invention can be monitored and controlled. digital signals, which the periodic eccentricity

The invention thus relates to a device for generating the rotation of the body,

Gen of digital signals, which a periodic Fig. 3 shows a detailed block diagram of a

Represent an analog signal that is generated by transducers in a further embodiment according to the invention. the

is generated, the periodically recurring Ex- 55 rotation of the body 38 is generated by the scanner 34

address centricities of a rotating body. and 36 scanned. The outputs at the outputs of the

A clock generator speaks to the rotation sters appearing error signals get through

of the body to a number of clock periods amplifiers 40 and 42 and then arrive as input

at each period of the analog signal. input variable to a differential amplifier 44. On

During each period of time an analog digi 60 produces this way the samplers 34 and 36 and the

tal converter (ADU) a digital signal, which amplifier 40, 42 and 44 as a converter circuit. the

corresponds to the analog signal. The digital signal amplifier 44 generates a periodic analog Si

is in a storage element, which this time signal, which the periodic eccentricities at

period is saved. In addition, the rotation of the body 38 reflects. Be it

a previously stored 65 is highlighted by the clock period that any arrangement of the

digital signal from the storage element reprodu- converter can be used. The only Ford

adorned and maintained as the output variable of the device consists in the fact that a relatively periodic

keep. recurring analog signal is generated, which

this defines the eccentricities of the rotation. According to FIG. 3. A rotating body 56 is in the body 38 is mechanically a pulse generator 46 of a construction 58 with the aid of a bearing assembly dome. As mentioned earlier, the pinion 60 is mounted. Transducers 62 and 64 are near the cortex of the analog signal a function of the Utndre body 56 with the aid of brackets 66 and 68, respectively, on hung of the body. Generally corresponds to the construction mounted ι 58th The output field is the period of one revolution of the body. Output signals from the transducers 62 and 64 are dependent on the mechanism that drives the body preamplifiers 70 and 72 and are then combined in one, and as a function of other factors, the dilferential amplifier 74 is added. The output, however, can be a function of several magnitudes of amplifier 74 period is a periodic analog rotation. In this case, the resolution signal, which periodic eccentricities are mechanically varied during some of the clock periods, reproduces the rotation of the body. A clock ring 76 is also attached to the by having the drive between the pulse generator and the body 56, which changes the rotating body. The ring 76 has a number of teeth, the solution can also be varied electrically, by indicating at 75 that the resolution when detecting is provided by a division or multiplication of the pulses 15. A capacitive switch 78 is provided at the output of the pulse generator. Finally, bracket 68 is mounted near the clock ring 76. Thus, when using a computer, the position of the clock ring 76 and the sounder 78 can be defined as a solution for any signal period and a position encoder can be used to decode sample signals by generating the control unit of the>: u, which after amplification properly programmed in a ver computer. The amplifier 80 controls the clock signal generator 48, the pulse generator 46 generates a number of probing signals. The amplifier 80 is connected to a Schmitt trigger 82, which sets the time periods for probing the, which is a very fast switching of the analog signal reproduce. These signals are made by gclan output. The Schmitt trigger 82 is designed as an input variable to a clock signal generator in such a way that it responds to the positive edge of the Aus-48. The Taklsignal-üenerator 48 generates a number of input pulses from the amplifier 80 responds. The clock signals during each time period around the Schmitt trigger generate an operation of the other circuit elements to form a coordinated clock signal at an output 83 during its switching. A first clock signal arrives at output 85 as an input and an inverted clock signal. The variable is sent to an addressing circuit 49, which is a clock signal at output 83 to a counter 84, storage element in a tüaitaien memory 50 30 of the in Γ i g. 4b, supplied and addressed. A second clock signal triggers the same. The output variable from the counter variable to a buffer memory 52 and acts as an input variable to a counter-decoder 86 that is contained in the digital memory 52. This is a standard arrangement for logic digital signals in the buffer memory 52 over- see Galter in order to be a single unified starting-1 tower. The buffer memory 52, the digital size 35 for each uniform state of the counter 84 memory SO and the addressing circuit 49 to generate.

represents a complete storage device. The second note that the counter 84 and the The clock signal therefore has the consequence that a digital Si counting decoder 86 combines an addressing circuit gnal appears immediately at output 32. These form. The operation of such a circuit The output variable corresponds to the analog signal, which is well known to those skilled in the art. Typically that counts chcs during the immediately preceding clock counters during regular operation zyperiodc of the analog signal was determined. Since cliché a number of uniform states or the temporal response of the probing signal c, vergli- counting steps, what of the design and size of the chcn is dependent on the counter required for changes in eccentricity. In the embodiment chcn time is very small, the output signal 45 is shown in FIG. 4 a very general case is shown, a very accurate representation of the magnitude of the analog signal in which the period of the analog signal is an UmSignals represents. At the same time the second clock signal rotation of the body 56 corresponds to Iriggcrt. Next is that an analog-to-digital converter 54, which has a di- number of the uniform states in the counter 84 A digital signal is generated which has the sign and equal to the number of teeth 75 on the clock ring the size of the analog signal during the previous 50 76. Accordingly, one cycle of the counter corresponds to one which clock period reproduces. After the ADC period of the analog signal. Like the expert he-54 has completed its cycle, the clock signal generates, so a much larger counter can Generator a third clock signal to be used to the digital. Using the The signal from the ADC 54 into the memory element of the counting encoder 86 can be used for the counting cycle on any digital Memory 50 to be transferred, which by 55 is a number of the uniform states or counting steps the addressing circuit 49 can be set during this clock pc- which is less than the maximum füi riodc was addressed. As those skilled in the art will recognize, the counter is. In this way the cycle de: is the use of the buffer memory 52 not counting or the period of the sampling cycle conditionally required. The use depends on the or sampling cycle so designed that. relative velocities of the ADC and the an- der 60 er of any period of the analog signal ent Talk time of the device. In addition, lead! his speaks regardless of the relationship between him Use for a uniform operation that matches the period of the analog signal and the reversal on the other hand, an intolerable number of logical hungings of the part or body. This technique came Gate devices at the entrance of the memory card - immediately in the form of a program mentcs would require. 65 when you have a digital computer for everyone

The F i g. 4 a and 4 b result when used for general purposes.

The connecting lines shown are joined together. The outputs of the decoder 86 are connected to the digita

den, a detailed circuit diagram of the embodiment len memory 50 attached. The digital spoke

consists of a matrix of two-state flip-flops. However, Hs can be any Storage device can be used. Every column. which is indicated at 87, limits a storage element, which is uniform with a decoder ausuaii'4 is. As with sirichüerten lines / you wipe " in the second and third columns, any number of counting levels can be used. this is a Question of interpretation based on the abias liquor solution or the desired accuracy. A number of flip-flops are used in each column, to store a digital signal which corresponds to an analog signal. As. with sirichricrlcn Lines between the second and thinner rows indicated by the flip-flops, the number of flip-flops in each column depends on the desired resolution of the digital signals stored there. After the Schmitt trigger 82 has a clock signal at an output 83 has generated. The counter 84 counts by one li d i d

here is a digital signal that shows the sign and the. Represents the size of the error signal. This cycle typically lasts IC microseconds. In addition, when preparing the buffer memory 52 and starting the converter 54, the second clock signal from the multivibrator 90 is used to trigger a time delay device 100 / u . The purpose of the time delay device 100 is zuiicuzicllen or / u delete the storage element

Converter 54 ends its cycle, the clock pulse generator 92 generates an output variable which also got to OR-Galtcr 102. In addition, since at this point in time the delay

is deleted after its content has been transferred to the buffer memory, but before the converter 54 completed its cycle. Therefore, several IOP nano-seconds after the start creates the time delay device a third clock signal for OR gate 102 in memory 50. "Additionally the third clock signal is fed to the return inputs of the flip-flops in the memory 50. the The output of the OR gate 102 sets the

Counter which is decoded in the decoder 86. 20 series of flip-flops, which at this point in time by The decoder generates an output variable that is addressed to the decoder 86, in readiness. Sodcr memory elements in memory 50 are addressed. The outputs of all flip-flops in this output size of the decoder opens an AND gate row driven to zero. After the disappearance 88, which corresponds to the digital signal in this column of the third clock signal, all return signals and signals that set the readiness to the inputs of the buffer memory 42 are removed. When to arrive. The buffer memory 52 contains a single row of flip-flops or storage elements.
To simplify the description, the following is intended
be valid. An AND gate is represented by a triangle

Svmbol shown, which in the Miltc a point 30 direction 100 is low or on a low having. ΕΪη OR gate is located by a three value, the AND gates 104 are open. This

AND gates see a parallel connection between each output of counter 74 and each Row of flip-flops in the memory 5t). The output from the OR gate 102 sets the Row of flip-flops in readiness, which are addressed by the decoder 86 at this point in time, and the digital signal in the counter 94 is transferred to a storage element of the memory 50.

In summary, it can be seen that every time a gear tooth 75 passes the switch 78, a load signal is produced, which is a clock period

Signal from a storage element, which is identified by the. Generated during each clock period first clock signal was addressed to store. According to the clock signal generator clock signals that the Zähdicscr Effect will cause a digital output in 45 lcr 84 to change state, and the buffer memory 52, which cause an upstream decoder 86 to generate a uniform list to generate stored value of the analog signal for input variable, which is a memory element in represents this sampling time. The second clock signal is forwarded to the memory 50 in an addressed manner. The previously saved also the operation of an ADL] «4, which is from the usual digital signal in this memory element in brazen construction is. In the ADLI, the second 5 ° triggers a buffer memory 52 transfer. The content in Clock signal a clock control unit 92 and forwards this memory element is then deleted and with for this one cycle. The clock controller 92 energizes a state-of-the-art signal a counter 94, which sets with a digital-analog, which the value of the analog error signal Converter (DAU) 96 is connected in parallel. The DAU indicates. Therefore, at each clock period 96 generates an analog signal with a magnitude 55 a very precise digital signal, which is the "analog proportional to the size of the digital number expression, error sienal identifies as AmonnocorKR ,. -Γ ,.

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corner symbol, which has a plus sign. An inverter stage is represented by a triangle symbol whose inputs are connected to one another are.

In Fig. 4a the inverted signal triggers at the output 85 of the Schmitt trigger 82 the monostable multivibrator 90. which a second clock signal on Output 91 generated. The second clock signal ar.s the multivibrator 90 performs various functions. Firstly, it serves to set the flip-flops of the buffer memory 52 in readiness to accept a digital

40

in the counter is 94. The output variable from the DAU 96 arrives at a differential amplifier 98, the other input 73 of which leads to amplifier 74. the Amplifier 98 compares the output from the

Fchlersignal identifies as an output variable the buffer memory for the entire duration of the period.

Each element between the inputs 73 and and the output of the buffer memory 52 leads Functions that are or are available in a digital computer for general tasks stand. Fig. 5 shows a flow chart of the Functions that are in accordance with the execution example

Converter 96 with the missing signal, which by the converter 62 and 64 as an output from the Amplifier 74 was detected. If the output from the converter is 96 cim: size that

Corresponding to the size of the analog signal from the Vcr- 65 the Fig. 4 a and 4 h are required. A river diastore 74 is. the amplifier 98 thus generates a program which is generally a graphical representation input variable for the clock control inheil 92. that of their definition. Analyze or solve a problem on the other hand, the ADLI 54 stops. The counter 94 is there. The functions and decisions that

309 681/421

are required to be recorded. The rectangular blocks define the functions required and the diamond shaped blocks define the decisions required. The output variable from the Taklgebervorrichlung is used to initiate the process. The first decision block 106 determines whether the output of the gage device has changed. Decision block 108 determines whether or not a sampling clock is present. If there is no sampling rate, the first two decisions must be carried out again until a sampling pulse and thus a sampling rate occurs. At this point in time, the functions defined by function blocks 110, 112, 114 and 116 must be performed. First, block 110 begins and the counter must be prepared. Second, block 112 requires that a memory element be addressed. Next, block 114 requires that the analog to digilal converter begin its cycle; and finally, block 116 requires that the line delay facility be started. The decision block 118 determines the influence, which depends on the state of the time delay device.

When the time lag is not over. Thus, the operational block 112 makes it necessary that the previously stored digital signal of the addressed memory element is transferred to the buffer memory. After the delay line is over! The flip-flops of the addressed memory element are reset, as is defined by the operation block 122 . Decision block ί24 requires the system to respond to the

ίο Completion of the analog-digital converter cycle is waiting. If the cycle is not completed, the decision is made again. When the converter cycle is completed, the operation block 125 requires that the new digital signal from the converter is input into the addressed memory section. However, this does not affect the content of the buffer memory at this point in time. After the new digital signal has been entered, the process begins again at decision block 106. A translation of the flowchart in Figure 5 into an encoded compule program can be done by a programmer experienced with a particular general purpose digital computer .

For this purpose 2 sheets of drawings

Claims (1)

ES * bfflU. a procedure Pa.en.insprUcne: LCN the recurring Exzentnz.taen a ^P rotating body play, characterized in that an H ktsignal _g ene ° ra.or (24; 48), the cyclic analog signal within the period of the scan signals generated using this Abtastsignalep both an analog -Digital converter (54) (ADU) for the analog signals originating from the eccentricities as well as a memory (28; 50) fires in such a way that the analog-digital converter converts the magnitude of the analog signal that prevails during the cycle time of the respective Abiasts-gnas converts the digital signal, and the memory converts this i » ngp P ^^ _al initially under known, wöbe, d «" ^^^ condenser contain use of a single ^S P ^e * ⁿ _ortio nal temporal the Imegnersufe m emn ^ P ^ _{a stop} j _m . ^A ^ ^z * ^ ^e ^ S "^ _n which the first one im- _se opens and the second C is the lspannung of the MEB _Wechse same-ϊ time at the Integnerstu- I _gk a vorgegebelbperioden the change to a zvveiten step of _{the A} mp.itude of the the payer