DE2143109A1 - DIGITAL EQUALIZATION CIRCUIT FOR EQUALIZATION OF READING PULSE SEQUENCES SUPPLIED BY MAGNETIC LAYER MEMORIES - Google Patents

Description

Digital descaling circuit for equalization of read pulse sequences supplied by magnetic layers

The invention relates to a digital equalization circuit with a variable degree of equalization for equalizing Read pulse sequences supplied by magnetic layer memories, which cause phase shifts in individual read pulses Contain frequency hops and where the first and the last read pulse after the start or before the end of a frequency jump!

For storing large amounts of data, there are magnetic stacking memories wide application. To record information on such magnetic layer storage media, as writing methods for example directional clock script or two-frequency script used. With them, the information is recorded in two frequencies. At the transition points from high to low or lower to high recording frequency, i.e. when a frequency jump occurs, the problem arises, that the distances between the information-carrying read signal peaks do not correspond to those on the writing side, i.e. the actual desired spacing. This shift the read signal peaks compared to the write signals Called tip offset. It has been found that particularly the first and the last change in magnetization of a high frequency recorded on a magnetic layer memory Signal sequence to the outside, so be pushed away from the center of the signal sequence.

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Pig. 1 shows a graphic representation in which the percentage peak offset is shown over a predetermined information sequence. The information sequence is 00000110101. It is shown on the abscissa of the graphic representation. Directional clock script has been chosen as the writing method. In the case of directional clock script, frequency jumps occur when information of different types is followed by several items of information of the same type and vice versa. If several items of information of the same type, for example several binary zeros, have to be recorded one after the other, then an auxiliary flux change on the magnetic layer memory is necessary. This means that the number of changes in storage doubles and thus a frequency priming occurs. This prequency jump is of course also evident in the read signals that are scanned by the magnetic memory. It has now been established that before and after a frequency jump, i.e. when the distance between the magnetization changes and accordingly the distance between the read signals changes, the first magnetization changes after the transition before, the low-frequency and the higher-frequency signal sequence and the last magnetization change before the transition from the higher-frequency to the lower-frequency signal sequence to the outside, that is to say away from the center of the higher-frequency signal sequence. This creates the so-called peak offset between write and read signals. The solid curve in FIG. 1 shows the peak offset over the specified read signal sequence. As can be seen, when the frequency changes from the higher-frequency sn of the ni-wire-frequency signal sequence, in the example from the binary "0" to the binary "1", a considerable peak offset occurs in the read signal before the frequency jump, also in the previous read signal which follows a reading religious of the same type of information,

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there is still a tip offset. The binary zeros are now followed by two binary ones. There is also a frequency jump here and there is again a peak offset at the frequency jump, but in the opposite direction on. The same applies to the transition from the binary ones to the next binary zero. Alternate information of various types, as shown at the end of the read signal sequence in Fig. 1, then the peak offset Zero. The same applies if only "information of the same Kind of like it is shown at the beginning of the curve. Thus, only the before and after a frequency jump lying signals influenced in their phase with respect to the write signal, namely in the above-mentioned Way. Only with them does a peak offset occur.

It is a circuit arrangement from laid-open specification 1 810 499 become known, with the help of which the described peak offset in magnetic layer memories is eliminated shall be. This circuit arrangement has an analogue structure. It contains some complicated and expensive ones Components. It is also difficult to make such an analog circuit work in a stable manner in terms of time and temperature. And finally, the level of equalization is not very high, for example only $ 20 to 30.

The object of the invention is to provide an equalization circuit with which the peak offset of read signals within is eliminated by read signal sequences and which works digitally. It is a prerequisite that the magnetic layer memories sampled read signals, which are analogous in nature, have been converted into digital read pulses are. These digital read pulses are then fed to the equalization circuit.

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The task is solved by a shift register that the read pulses delayed by first circuitry that detects; whether the pulse interval of a Reading pulse to the previous and the next Reading pulse is large or small (same pulse spacing) and in this case the assigned by the slide the registered delayed read pulse passes to a first timing circuit, through a second circuit arrangement, if the pulse spacing of a read pulse is unequal to the previous and subsequent read pulse Presence of a long pulse interval to the previous one Read pulse at least the assigned read pulse delayed by the shift register to a second Timer with a greater delay time than that of the first timer conducts and if a long one is present Pulse interval to the following read pulse at least the assigned read pulse delayed by the shift register to a third timing circuit with a smaller one Delay time than that of the first timer leads.

Thus, with the help of the digital equalization circuit, after a frequency jump from a low frequency to a higher-frequency signal sequence and accordingly before a frequency jump from a higher-frequency to a low-frequency signal sequence lying reading pulse shifted towards the middle of the higher-frequency signal sequence.

In most cases it will be sufficient if the read pulses immediately before and after a frequency jump are shifted in time, because only ^r ; they have a very large peak offset.

The digital equalization circuit η part, determines how long the VPA 9/210/104 4 - 5 -

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Iropulse intervals before and after the read pulse - corresponds to a change in magnetization - are. If the intervals are approximately equal, the equalization circuit does not conduct an equalization process a; "If the intervals before and after a read pulse are unequal, an equalization process is carried out for this read pulse initiated in the right direction with an adjustable amount of disengagement, i.e. amount of time.

Since digital signals are fed to the equalizer circuit, it is possible to use the equalizer circuit of digital building blocks. However, digital building blocks are cheap and straightforward. You can with them Create simple, maintenance-friendly circuit arrangements.

Other developments of the invention emerge from the subclaims.

The equalizer circuit according to the invention is made with the help of of exemplary embodiments, which are illustrated in figures, further explained. Show it:

Pig. 1 is a graph of the percent peak displacement plotted over a predetermined read signal sequence before and after equalization,

Pig. 2 is a block diagram of the digital equalizer,

Pig. 3 the implementation of the block diagram with digital modules,

Pig. 4th

5 and 6 a pulse diagram for the equalization circuit according to Pig. 3.

With the help of the equalization circuit of the Pig. 2 and the Pig. only the two outer ones, before and after a frequency

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jump lying read impulses shifted in time, so equalized. ■

The read pulses LES are first fed to a shift register SCH and are delayed by this this delay time, it is determined in the rest of the equalization circuit whether or not there is a peak offset not and then the read pulses delayed by the shift register in time according to this determination postponed or not postponed the correct position.

The read pulses will continue LES a first scarf ψ processing arrangement fed SA1, which determines if the pulse interval of a read pulse to the preceding and subsequent read pulse either bsidemale large oäer 'beidqmale small. The first circuit arrangement SA1 thus checks whether the pulse intervals before and after the read pulse are approximately the same. It generates an "EQUAL" output signal for this pail.

The read pulses LES are finally a second circuit arrangement SA2 offered. It first checks in a circuit UGL whether the distances before and after a Reading pulse are not equal. In the event of inequality, it then determines whether the pulse spacing in front of the read signal is greater is than. after the read signal or whether the pulse spacing • before the read signal is smaller than after the read signal. in the in the first case it generates an output signal at the output of the circuit GR, in the second case it generates an output signal at the output of the circuit KL.

The read pulses LES delayed by the shift register SCH and the output signals of the first circuit arrangement SA1 and the second circuit arrangement SA2 are fed to a logic circuit VK which establishes the connection between

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the shift register, the first circuit arrangement SA1 and the second circuit arrangement SA2 with three timing circuits ZEB, ZES ₅ ZEF. The first time circuit ZEB has a certain fixed delay time to. The read pulses LESS delayed by the shift register SCH are supplied to it when the first circuit arrangement SA1 emits an output signal, i.e. has established that the pulse intervals before and after the read pulse supplied to the timing circuit ZEB were approximately the same. The. second time circuit ZES has a delay time tO + ts. Your delay time is therefore greater than that of the time circuit ZEB. The delayed read pulses LESS are then fed to it when it has been determined in the second circuit arrangement SA2 that the pulse spacing from the preceding read pulse was greater than the pulse spacing from the subsequent read pulse. The corresponding read pulse is thus delayed longer than the read pulse supplied to the timing circuit ZEB. The third time circuit ZEP finally has a delay time to-tf, that is to say a smaller delay time than the first time circuit ZEB. You are offered the read pulses LESS, of which the second te circuit arrangement SA2 has determined that the pulse interval to the previous read pulse is smaller than the pulse interval to the subsequent read pulse. The corresponding read pulse is thus delayed by a shorter time than the read pulses offered to the timing circuit ZEB. The outputs of the three timing circuits ZEB, ZES and ZEP are fed to an OR circuit 01- and the equalized read pulses appear at the output of this OR circuit.

The puncture of the equalization circuit according to Pig. 2 aoll -with With the help of the pulse plan of FIGS. 4, 5 and 6, this can be made even more clear. In Fig. 4 t-ir-6 are in the ground line the inscribed in the magnetic layer spt-j oherri

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formations, in line 2 the write signal, in line 3 the read pulses. You can clearly see how, when a frequency jump occurs, the corresponding read pulses are shifted in time with respect to the write signal. Such a time shift is given with the read signals 2, 4> 5? 7 · When the second let: e pulse occurs, the equalization circuit determines that the pulse spacing to the preceding, the first read pulse, is greater than the pulse spacing to the following, the third read pulse. Then, in the equalization circuit, the üPig * 2 in the circuit arrangement SA2 will respond to the circuit GR and cause the read pulse delayed by the shift register SCH to be sent to the second timing circuit ZES. The read pulse 2 is thus shifted over time in the direction of the third read pulse, namely by such an amount that it comes to be below the corresponding write signal in terms of time. When checking the third read pulse, the equalization circuit comes to the result that the pulse spacing between the preceding, the second reading pulse, and the following, the fourth reading pulse, is the same. The first circuit arrangement SA1 thus emits a signal and causes the read pulse delayed by the shift register SCH to be passed to the first timing circuit ZEB. It is then only shifted in time by the basic delay time t0. When checking the fourth - "" th read pulse, the equalization circuit determines that the pulse spacing to the preceding, the third reading pulse, is smaller than the pulse spacing to the -following, the fifth reading pulse. Then the circuit KL responds within the second circuit arrangement SA2 and the read pulse assigned to it, which is delayed by the shift register SCH. is offered to the third time switch ZEE, .that these - _;; Read pulse delayed by a smaller delay time than the basic delay time tO. The reading pulse is thus in the direction of the third reading pulse:, temporally, accidentally

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"ben. Correspondingly, the equalization circuit then works hot the further reading pulses.

Since the external read pulses in the direction of a frequency jump must be shifted to the middle read pulse of the higher-frequency signal sequence, so in the pulse plan of the figures 4 to 6 once to the right (see reading impulse 2.) and once to the left (see reading impulse 4), the proportions must also be Read pulses that are correct to the write signal are shifted in time by a timing circuit (ZEB), because only in this way can it be achieved that a read impulse is laterally premature compared to its normal time position v / can earth.

In Fig. 3 the structure of the equalization circuit with digital components is shown. The mode of operation of this circuit arrangement is to be explained in connection with the pulse plan of FIGS. It is the directional clock script was selected and recorded the write signal in line 2. Those derived from the read signal peaks Reading pulses (line 3) represent the information times and include the peak offset that affects the frequency hops is due in the write signal. The digits in Fig. 3 should match the lines in Fig. 4 and Fig. 6 indicate in which the signal occurring at these points is shown.

The first circuit arrangement contains the NAITD elements NB, N9 and 1TG-3, the second circuit arrangement contains the NAND elements H10, im ITI2, N13 and NG4. Common to the first and second circuit arrangements is a selection circuit made up of a pulse separation circuit and a pulse generation circuit. IJie impulse detection circuit gives at its one output the. Reading pulse off _? the γρη have a greater distance from the preceding μηά. a, n yrem a, nder = en

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output the read pulses from the previous read pulses have a short distance. The pulse separation circuit in Fig. 3 consists of the flip-flop EEJ4, the NAND gates IT1, N2, the timing circuits ZE5, ZE4 and the NAND gates 1 * 3, K4 »N5, N6» NG1, NG2. The pulse generation circuit is connected to the pulse separation circuit and consists of the flip-flops FFSPK and FFSPL and the ITAHD-Glled 1Ϊ7 · The pulse generation circuit generates on the one hand, pulses with a duration starting from the trailing edge of the read pulses with a short pulse spacing from one another determined v / ground, on the other hand, pulses with a duration that is determined by the trailing edge of a read pulse that is used for P preceding read pulse has a long pulse spacing ~ and the trailing edge of the next pulse, which is a short Pulse spacing is determined. The first timing circuit ZEB consists of the delay element VEB and the NAIiD gates NI8, N17, N16, the second timing circuit ZEF from the delay element VEF, the NAND element N14 and the flip-flop FFF and the third timing circuit ZES .from the delay element VES, the NAND element N15 and the flip-flop FFS.

With the help of a shift clock I (line 4) the Read pulses LES (line 3) in the shift register SCH fc shifted in time by approximately £ / 4 main flow change periods. The time-shifted read pulses are shown in line 17 of FIGS. you will be Called LESS. The further processing of the delayed read pulses LESS is described later.

From the positive banks of the read pulses LES (line 3) the IQpjpsGhialtung PF 3% (line 5} is tilted, the positive edges dep output, signaleg of the flip-flop

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(Line 5) trigger the timing circuit ZE4 (line 6), the negative edges of the output signal p, of the flip-flop FFJ4 trigger the timing circuit ZE5 (line 7). After approximately one main flow change period, the time switches ZE4 and ZE5 return to their initial state.

With the help of Öev timing circuits ZE4 and ZE5 and logic circuits consisting of NAND gates 115, N4, N5, 1 * 6, NG1, NG2, it is determined whether the distance between two successive read pulses is short or long. In line 8, that is to say at the output of the NAND element NG2, the read pulses of short intervals appear, in line 9 of FIGS. 4 and 6, that is to say at the output of the NAND element HG · 1, the read pulses of long intervals appear.

To determine whether the pulse spacing between the successive Read pulses are equal or unequal and whether the distance between one read pulse and the previous one and is larger or smaller for the subsequent read pulse, additional parameters are required. This is done using the flip-flop FFSPK is flipped by the negative edge of the output signal of the NAND element NG2. (Line 8). The output signal of the flip-flop FFSPK is shown in line 10. The flip-flop FFSPL is on the negative edge of the output signal of the NAND element NG1 (line 9) and of the positive edge of the output signal. of the flip-flop FFSPK (line 10) is reset. In order for the further process to take place correctly, a certain phase relationship between the output signals the IiAIiD-GIieder NG1 and NG2 to the flip-flop FFSPK are produced. The synchronization of the flip-flop FFSPK takes over from the output signal of the NAND element NG1 (line 9) by inversion by the NAND gate N7 derived signal (line 12), which the flip-flop FFSPK is fed.

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Two successive read signal intervals can be the same due to the two short or two long pulse intervals, DaEU becomes the coincidence of the output signals of the MHD-Glides HG2 (line 8), the flip-flop FPSPK (line 10) and the negated output signal.es of the flip -Flops FFSPL determined and on the other hand the coincidence of the output signal of the NAHD element IiGI ■ (line 9), the flip-flop FFSPL (line 11) and the negated output signal of the flip-flop FFSPK. The signal - "EQUAL" (line 13) generated in this way is formed in the pulse diagram of FIGS. 4 to 6 after the fourth read pulse, after the seventh read pulse and after the ninth read pulse. W At these points in time you can see that the two preceding reading pulse intervals are always the same. In the first two cases the read pulse spacing is small, in the third case the read pulse spacing is large.

Two successive read pulse intervals can be achieved by the sequence of a large and a small reading pulse Be unequal in status or in the reverse order.

The coincidence of the output signals of the HAHD element is used to generate the "EQUAL" signal (line 14). HG2 (Line 8), the flip-flop FFSPL (line 11) and the negated output signal of the flip-flop FFSPK on the one hand "" ". and on the other hand the coincidence of the output signals of the NAHD element HG1 (line 9) and the negated output signals of the flip-flops FFSPK and FFSPL are formed. That Signal »EQUAL» (line 14) is after the third, fifth, sixth and eighth read pulse generated. At these times it can be seen that the two preceding Read pulse intervals are unequal. In the first case (3rd read pulse) it is a long / short, in the second case (5th L "eseimpuls) by a short / long, im

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third. Pall (6th read pulse) by a long / short and im fourth trap (8th reading pulse) by a short / long sequence. The sum of the equal and unequal pulses must always be the same as the number of read pulses.

To be able to specify the direction for the equalization process, a distinction must be made "for the signals" NOT EQUAL "(line 14), whether the two preceding ones are unequal Pulse intervals in the time sequence long / short or short / long arise. For the formation of the signal "LARGER" (line 15), i.e. that the pulse spacing is only is large and then small, the coincidence of the output signals of the flip-flop PFSPL (line 11) and the ITAiTD-G-Iiedes NG4 (line 14) and the negated output signals G. of the flip-flop FFSPK detected. The signal "SMALLER" (line 16), i.e. the sequence becomes short / long due to the coincidence of the negated output signals of the flip-flops FFSPK and FFSPL and the output signal of the BAHD-GIiedes NG4 / (line 14).

One now has knowledge of the pulse intervals with which the read pulses follow one another. This is exploited to have an equalizing effect on the read pulses (line 17) which have been time-shifted by the shift register SCH. The basis for the equalization is the knowledge that the external read signals (first and last) of a high-frequency read signal sequence to the outside, i.e. be pushed away from the center of the read signal sequence The first read pulse of a read pulse train must be delayed and the last read pulse of a read pulse train be premature. This is done with the help of the first, second and third timers.

The output signal of the NAND gate N12 (line 15) is set the flip-flop FFS (line 21). The; now next one

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corresponding read pulse that has passed through the shift register SCH (Line 17) resets the "flip-flop FPS. The The trailing edge of the flip-flop FFS causes the delay element VES (line 22) to start up. The running time of the delay element is made up of the basic delay time tO for the read pulses that are not to be equalized + a time ts, which depends on the degree of distortion of the tape head system of the magnetic layer storage device. The trailing edge of the output signal of the delay element VES (22) generates a pulse (line 23), which the OR circuit 01 is supplied and is directed to.ein pulse regenerator MK. This generates on his h Output the equalized read pulse (line 26).

The third read signal (line 17) passed through the shift register SCH does not need to be equalized. No signal has then been formed at the outputs of the NAND gates N12 and N13 and the timing circuits ZES and ZEF have not been activated. The case that a read signal does not have to be equalized, i.e. that the pulse intervals before and after the read signal are the same, can thus be determined by the coincidence of the negated output signals of the timing circuits ZES and ZEF and the delayed read pulse, and the timing circuit ZEB can thus be started (see Sect Line 24). The time- W circuit ZEB runs with the basic delay time tO and forms an output pulse with the trailing edge (line 25), which generates the third read pulse (line 26) without equalization. ■:

It is then determined that the sequence of the pulse spacing is short / long and thus an output signal formed at the output of the NAND gate N13 (line 16). Through this the flip-flop FFS is set. This happens, for example, after the occurrence of the fourth read pulse * Der

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associated fourth read pulse is delayed by the shift register SCH and resets the flip-flop PPS (Line 18). The trailing edge of the flip-flop PPS causes the delay element VEP (line 19) to start up. the period of the delay element VEF is equal to the difference between the basic delay time to and a time tf, which is also according to the degree of distortion of the tape head system of the magnetic layer storage device. The trailing edge of the output signal of the delay element VEP (line 19) generates a: pulse (see line 20), which is the premature, i.e. equalized, fourth reading pulse (line 26). caused.

The procedure described applies analogously to the processing of the further read pulses.

Line 26 contains the processed, equalized read pulses shown. The dashed pulses show the position of the originally distorted read pulses.

In the arrangement of Fig. 3 \ ^r ext ended circuits may include time delay elements which are constructed as dual counter ".

Fig. 1 shows - as already explained above τ the peak offset, based on a main flow change distance, plotted over a read signal sequence. With the same Frequency of the read signals, there is no peak offset. Only when there is a frequency jump, this is shown in FIG. 1 after the 5th bit, the previous bits are pushed aside. This results in the tip offset, which is in the extended Curve is shown.

The letter P on the fifth and seventh bit means that these bits must arrive earlier, i.e.

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that here the timing circuit ZBP must be effective to reduce the tip offset z \ x. ' The letter S in The sixth bit, on the other hand, says that the bit will arrive later must, i.e. that the time switch ZES must take effect here in order to reduce the peak offset.

The degree of equalization of the equalization circuit, i.e. the Time amounts in the time switches ZEF and ZES must so "are dimensioned that the equalized read signals a have the smallest possible residual tip offset, i.e. as close as possible to the "liulline" line of the ordinate. The degree of rectification states the percentage by which a peak offset is reduced «The Time amounts for the time switches ZES and ZEE can immediately chosen wex'den. But it is also quite possible to choose them differently in order to be able to adapt better to the conditions of the system.

The digital equalization circuit intervenes in the. described in a flat manner at the appropriate points and reduced the tip offset. The peak offset that still results after the rectification is given by the dashed line Line in prop. 1. As can be seen, the tip offset has decreased significantly.

To determine the delay times with which the timers ZEP and ZES are running, you can proceed as follows: The arithmetic mean is calculated The maximum and minimum peak misalignment occurring on the bi-parts to be equalized is determined. It results from this a manipulated variable:

Manipulated variable =

Here, Smax mean maximum tip offset, Smin mean minimum tip offset.

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The degree of equalization E for the Spitzer offset is then by definition:

T? - Smax - (Srnax - Stel l size)

Stnax

By inserting the manipulated variable and transformation given above the equation gives:

In this example it is assumed that the delay time of the time circuits ZEI ¹ and ZES is the same.

The amount of equalization can be set in a simple manner by changing the delay time with which the timers run. This means that the time interruptions ZEi ¹ and ZES must be influenced. If dual counters are used as timing circuits ZES and ZEP, then only the amount to which the dual counter counts has to be changed.

The equalization circuit has the advantage that a different Equalization level for goalkeeper or backward direction can be introduced that accordingly the direction of travel a change in the delay times tf of the time switch ZEP or ts of the time switch ZES can be made. Another read signal frequency, for example by changing the tape speed or changing the speed, can be processed by that the supply clock for the shift register and the as Dual counters formed timers are changed together.

13 claims
6 figures

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Claims (13)

Claims 1. Digital equalization circuit with changeable equalization Degree of equalization of read pulse trains supplied by magnetic layer memories, the phase shifts sequence jumps causing individual read pulses ge, in which the first and the last read pulses after the beginning and before the end of a frequency jump postponed by a shift register (SCH), which delays the read pulses, by a first circuit arrangement (SA1) which determines whether the distance of a read pulse to the previous and to the following read pulse either is large or small and for this pail the assigned read pulse delayed by the shift register passes to a first timing circuit (ZEB), through a second circuit arrangement (SA2), which, if the pulse spacing of a read pulse to the preceding and subsequent read pulse if there is a long pulse interval to the previous read pulse at least the assigned read pulse delayed by the shift register to a second time switch (ZES) with a greater delay time than that of the first time switch (ZEB) conducts and, if there is a long pulse interval to the subsequent read pulse, at least the assigned from the shift register (SCH) delayed read pulse to a third timing circuit (ZEP) with a smaller one Delay time than that of the first timer (ZEB) leads. 2. Digital equalizer circuit according to claim 1, marked g by the first circuit arrangement (SA1) to which the read pulses are fed and that for the pail of equality of the pulse intervals VPA 9/210/1044 - 19th 30S 80 9/0993 2U3109 and emits an output signal after a read pulse the second circuit arrangement (SA2), at the input of which the read pulses are applied and the "if the read pulse intervals are unequal before and after a read pulse if there is a long pulse distance to the previous read pulse and a short pulse spacing to the subsequent read pulse emits an output signal at an output and when there is a short pulse spacing to the previous read pulse and a long pulse spacing emits an output signal at another output for the subsequent read pulse, through a shift register (SCH), which delays each read pulse until the first and the second circuit arrangement (SA1, SA2) this Lieseimpuls has checked by a logic circuit (VK), which with the shift register (SCH) and the first and second circuit arrangement (SA1, SA2) is connected by the three timing circuits (ZEB, ZES, ZEP) connected to the logic circuit (VK) and by an OR gate (01) whose inputs are connected to the outputs of the timing circuits (ZEB, ZES, ZEF) is. 3. Digital equalization circuit according to claim 1, characterized in that for the case the inequality of the pulse intervals before and after a read pulse the second circuit arrangement (SA2) if present a long pulse interval to the previous read pulse and several short itapulse intervals for the subsequent read pulses the read pulse following the checked read pulse to a further timer with a delay time lying between the delay times of the first and the second timing circuit and if there are several short pulse intervals before the read pulse to be tested and a long pulse interval to the subsequent reading VPA 9/210/1044 -20 - 309809/0993 _ ₂₀ _ 2H3109 Pulse the read pulse before the tested read pulse to another timing circuit with one between the delay sides of the third and the first Delay time. . 4 »Digital equalization circuit according to one of the preceding Claims, characterized in that that the first and second circuit arrangements (SAL, SA2) have a selection circuit from a pulse input circuit and a, pulse generation circuit is common * that the pulse separation circuit at one Output emits the read pulses that have a large pulse spacing from the previous read pulses and at the other output emits the read pulses, which from the previous read pulses a short pulse interval have and that the pulse generation circuit with the pulse separation circuit is connected and at its one output pulses of the duration of the trailing edge of a at the other output of the pulse separation circuit generated pulse up to the trailing edge of the next pulse appearing at the other output and on its other output pulses the duration of the trailing edge of that occurring at one output of the pulse separation circuit Pulse on the trailing edge of the next appearing at the other output of the pulse separation circuit Gives off impulse. 5. Digital equalizer circuit according to claim 4, characterized by a pulse separation circuit aus.einem first flip-flop (FFJ4) i from a fourth timing circuit (ZE4), which via a NAIiD-GIied (N1) on the one hand with the noninve'rtierten output of the first Flip-flops (FFJ4), on the other hand, is connected to the input for the read pulses, from a fifth timing circuit (ZE5), which is connected to the internal VPA 9/210/1044 -.21 - 309809/0993 . 2U3109 verted output of the first flip-flop (FFJ4) and the input for the read pulses is connected from a first logic circuit (N3, 1T4> NG-1), which "at coincidence the read pulse, the inverted output signal of the first flip-flop (FFJ4) and the inverted output signal the fourth timer (ZE4) or the read pulse, the non-inverted output signal of the first flip-flop (FFJ4) and the inverted output signal ~ les the fifth timer (ZE5) selects the read pulses, the one great Inipulsa stood behind the previous one Have read pulse from a second logic circuit (N5, Kb, ifG-2), called the coincidence of the read pulse, des inverted output signal of the first flip-flop (FFJ4) and the non-inverted output signal of the fourth Timing (ZS4) or the read signal, the directionally inverted Output signal of the first flip-flop (FFJ4) and of the non-inverted output signal of the fifth timing circuit (ZE5) selects the read pulses that have a short Have the pulse spacing to the previous read pulse. 6. Digital equalization circuit according to claim 4, characterized by a pulse generation circuit from a second flip-flop (FFSPK) connected to the output of the second logic circuit is connected and set by the output signals of the second logic circuit and is reset and from a third flip-flop (FFSPL), whose set input is connected to the output of the first logic circuit and its reset input to the output of the second flip-flop (FFSPK) connected. 7. Digital equalization circuit according to claim 5 and 6, characterized by a second circuit arrangement with a third logic circuit (N10, 1SF11, YPA 9/210/1044 - 22 - 309809/0993 2U31Q9 ■ NG-4), the coincidence of the non-inverted output signal of the third flip-flop (Ei ¹ SPL), the inverted output signal of the second flip-flop (FFSPE) 'and the output signal of the second logic circuit or the coincidence of the inverted output signal de3 third Flip-flops (FFSPI), the inverted output signal of the second flip-flop (FFSPK) and the output signal of the first logic circuit generate a signal that indicates the inequality of the pulse intervals before and after the read pulse, from a NAND element (N12) that upon coincidence of the non-inverted output signal of the third flip-flop (FFSPL), the inverted output signal of the second flip-flop (FFSPK) and the output of said third logic circuit outputs a signal indicating that the pulse interval prior to the read signal is greater than the pulse spacing after the read signal and from a further NAND gate (N13) i-. the coincidence of the inverted output signal of the second flip-flop (PFSPK), the inverted output signal of the third flip-flop (FFSPL) and the output signal of the third logic circuit emits a signal that indicates that the pulse spacing before the read signal is smaller than after Read signal. 8. Digital equalization circuit according to claim 7, g e indicates by a second timing circuit (ZES) from a fourth flip-flop (FPS), whose set input connected to the output of the NAND gate (ΝΊ2) and whose reset input negates the © output signal of the shift register (SCH) is fed from a NAND gate (ΝΊ5), which is connected to the output of the shift register (SCH) and the output of the fourth flip-flop (FF S) is connected and a delay element (VES) which is connected to the output of the NAND element (N15) and its delay time is greater than the delay by the amount ts VPA 9 / 21G / 1044 - 2 3 - 309809/0993 2U3109 - 23 time of the first timer (ZEB). 9 «Digital equalizer circuit according to claim 7> characterized by a third timing circuit (ZES) consisting of a fifth flip-flop (FJ ¹ P), whose set input is connected to the output of the ITAED-GlMes (N13) and whose reset input is the negated output signal of the shift register (SCH) is supplied from a NAND element (1T14) »which is connected on the one hand to the output of the fifth flip-flop (FFF) and the output of the shift register (SCH) and from a delay element (VEF) which is connected to the output of the NAND element (FI4) is connected and its delay time is smaller by the amount tf than the delay time of the first timer (ZEB). 10. Digital equalization circuit according to claim 7 »g ekennzeich.net through a first timing circuit (ZEB) consisting of a NAND element (N18), whose first input is the output signal of the shift register (SCH), whose second input is the negated output signal of the second timing circuit (ZES ) and desoem third input the negated output signal of the third timing circuit (ZEF) is fed and from a delay element (VEB) _? which is connected to the output of the NAND gate (N18). 11. Digital equalization circuit according to one of the preceding claims, characterized in that that the degree of equalization is changed by changing the delay time of the second and third timing circuits (ZES, ZEF) is changed. '■ 12. Digital equalization circuit according to claim 11, characterized marked that the delay VPA 9/210/1044 - 24 - 309809/0993 - 24 - the second and third time switch (ZEP, ZES) are different. 13. Digital computer maintenance according to one of the preceding Claims, characterized in that that when the reading pulse frequency changes, the fermentation guiigs clock of the shift register (SCH) and the three timing circuits (ZEB, ZES, ZEP) is switched. VPA 9/210/1044 309809/0993 4t? Blank page