DE2143109C3 - Digital equalization circuit for equalizing read pulse trains supplied by magnetic layer memories - Google Patents

Description

The invention relates to a digital equalization circuit for equalizing magnetic layer memories delivered read pulse sequences that cause phase shifts of individual read pulses Contain frequency jumps, the read pulses immediately after and before a frequency jump are shifted in time, and with timing circuits depending on the read pulse sequence can be switched on to delay the read pulses.

Magnetic layer memories are widely used for storing large amounts of data. To record of information on such magnetic layer memories are used as a writing method for Example the directional clock script or the two-frequency script used. With them the information recorded in two frequencies. At the transition points from higher to lower or lower to high recording frequency, so when a frequency jump occurs, the problem arises that the distances between the information-carrying read signal peaks not those on the write side, i.e. the actually correspond to the desired intervals. This shift of the read signal peaks compared to the Write signals is called peak offset. It has been found that especially the first and the last change of magnetization of a high frequency recorded on a magnetic layer memory Signal sequence to be pushed outwards, i.e. away from the center of the signal sequence.

Fig. 1 shows a graph in which the percentage peak offset is shown over a predetermined information sequence. The information sequence is UOO (H) 1 1 0 1 0 1. It is on the abscissa the gi arian representation. As a writing method the directional clock was chosen. Frequency jumps occur in the directional clock script then when information of different types is followed by several pieces of information of the same type and vice versa. You have to have several pieces of information of the same type, for example several If binary zeros are recorded one after the other, then there is an auxiliary flow change on the magnetic layer memory necessary. This means that the number of magnetization changes doubles and thus a frequency jump occurs. This frequency

! 5 6

The jump can of course also be seen in the one that works digitally and in which the clock pulses Read signals that do not have to be taken into account by the magnetic memory. It is pre-sampled will. It has now been ascertained that those from magnetic layer memories are exhausted before and after a frequency hop, d. H. if Lcscsignale, which are of an analog nature, keyed in the distance between the magnetization changes and ent- 5 digital read pulses have been reshaped. This In other words, the spacing between the read signals changes, digital read pulses then become the equalizer supplied for the first change in magnetization after switching.

transition from the low frequency to the higher frequency The task is solved by a shift register. th signal sequence and the last change in magnetization the read pulsec for the duration of the check before the transition from the higher frequency to io the read pulse c is delayed by a first switch low-frequency signal sequence to the outside, so processing arrangement that determines whether the distance of a from the middle of the higher-frequency signal sequence away - read pulse to the previous and to the following will. This creates the so-called following read pulse and is the same for this case Peak offset between write and Lcscs signals. the assigned, through the shift register ver-Die The solid curve in FIG. 1 shows the peak delayed read pulse on a first timing circuit Iciversatz above the specified read signal sequence c. As tet, by a second circuit arrangement, which at one can see that when the frequency changes, the inequality of the pulse spacing of a read pulse occurs higher frequency to the lower frequency signal to the preceding and following read pulse follow, in the example from the binary "0" to the binary when there is a long pulse interval to the "1", in the case of the read signal before the frequency jump 20, at least the previous read pulse considerable point oversalz. Even with the upstream reading delayed by the shift register Read signal., Which yes to a read signal of the impulse to a second timing circuit with a larger If the same type of information follows, there is still a peak delay time than that of the first time switch offset before. The binary zeros are now followed by two leads and when there is a long pulse spacing Ones. Here, too, there is a frequency jump and at least 25 for the subsequent read pulse If the frequency jump occurs again a peaked Lcsc offset, delayed by the shift register, but in the opposite direction pulse to a third timer with a smaller one on. The same applies to the transition from binary ones to the delay time as that of the first timer to the next binary zero. Take turns in introducing.

different types of information, as it ends up being Read signal sequence, Fig. 1, is shown, then the circuit after a frequency hop of a the tip offset is zero. The same applies if only low-frequency signal formations result in a higher-frequency signal of the same kind as follow and correspondingly those of a frequency shown at the beginning of the curve. Thus, the jump from one higher frequency to another is only the read pulses before and after a frequency jump versignal the signals in their phase with respect to the writing center of the higher frequency signal sequence affected, namely pushed in the above.

Way. Only with them does a peak offset occur. Mostly it will suffice if the direct

on. before and after a frequency jump

It is from OfTcnlegungsschrift 18 10 499 that 40 impulses are shifted in time, because only they

Circuit arrangement become known, with which have a very large Spilzcn \ ersatz.

Help the described peak offset with magnetic The digital equalization circuit determines how

layer storage should be eliminated. This switch shows the pulse spacing before and after the reading

arrangement is structured in the same way. It contains to the impulse - corresponds to a Magnctisicrungswcch-

Tcil complicated and expensive components. Difficult is 45 is - are. Conducts at approximately equal intervals

It is also possible to time such an analog sound and the equalization circuit does not involve an equalization process:

to have temperature-stable work. And finally, with unequal intervals before and after a Lcsc-

the degree of equalization is not very high, e.g. B. only pulse is an equalization process for this read pulse

20his30 ° / n. in the right direction with an adjustable

The disclosure document 17 62 733 also introduces an equalization amount of 50.

an arrangement has become known, with the aid of which digital signals are induced to cause the equalization of the peak offset in magnetic layer memories, it is possible that the equalization circuit should wrestle. It is proceeded in such a way that it can be expanded with the help of digital modules. The clock pulses, which are cheap and uncomplicated, necessary to evaluate the read pulses, are necessary to be delayed in such a way that they can be used to create simple, maintenance-friendly circuit arrangements for reading pulses that occur too late,
fall. The read pulses that occur too early are The equalizer circuit still has the advantage. delayed, in such a way that they coincide approximately with the vcr- that a different equalization wheel for delayed clock pulses. In this wärts- or backward-running direction introduced who arrangement, however, the correct appearing 60 can lie that, according to the direction of travel, a read pulse is always a bit next to the Taklim pulse. Switching over the delay times of the third This is a disadvantage, since it is necessary for a correct evaluation time circuit or the second time circuit to precede the read pulses that the clock can be received. Another Lescsignalfrcimpulsc timed as possible with the reading pulses auf- quenz, z. B. by a Bandgeschwindickeitsäntreten. 65 change or a change in speed, can thereby

The object of the invention is to edit an Entzcrrerschal- that the supply cycle for the

with which the offset of the read / shift register and the binary counter form

signals within Lescsignalsequcn eliminated th Zcitschaltcn can be changed together.

Other developments of the invention emerge from the uncertain claims.

The equalizer circuit according to the invention is illustrated with the aid of examples shown in FIGS
put sinti. further explained. It shows

Fig. 1 is a simple representation of the percentage Peak offset, recorded over a given Lcsc signal sequence before and after equalization,

Fig. 2 is a block diagram of the digital equalizer,

3 shows the implementation of the block diagram with digital building blocks,

Figures 4, 5 and 6 show a timing diagram for the equalizer circuit according to FIG. 3.

With the help of the equalization circuit of FIG. 2 and the F i g. 3 only the two outer Lcscimpulsc before and after a frequency jump shifted in time, so equalized.

The read pulses LES are first fed to a shift register SCH and are delayed by this. During this delay time, it is determined in the rest of the decoding whether a peak offset is present or not and then the read pulses delayed by the shift register are shifted or not shifted in time to the correct position in accordance with this determination.

The read pulses LES are also fed to a first circuit arrangement SA 1, which determines whether the pulse spacing of a read pulse from the previous and the following read pulse is either large or both times large. The first circuit arrangement SA 1 thus checks whether the pulse spacings before and after the read pulse are approximately the same. In this case it generates an output signal "EQUAL".

The read pulses LES are finally offered to a second circuit arrangement SA 2. It first checks in a circuit VGL whether the distances before and after a Lcseimpuls are unequal. In the event of inequality, it then also determines whether the pulse distance before the read signal is greater than after the Lcsesignal or whether the pulse spacing is smaller than after the Lcsesignal. In the first case it generates an output signal at the output of the circuit GR , in the second case at the output of the circuit KL.

The read pulses LES delayed by the shift register SCH and the output signals of the first circuit arrangement SA 1 and the second circuit arrangement SA 2 are fed to a logic circuit VK which establishes the connection between the shift register, the first circuit arrangement SA I and the second circuit arrangement SA 2 with three timing circuits ZEB , ZES, ZEF manufactures. The first time circuit ZEB has a certain fixed delay time / 0. Supplied thereto delayed by the shift register SCH read pulses LESS when the first circuit arrangement SA 1 emits an output signal, having thus been observed that the pulse intervals have been about the same before and after the timing circuit ZEB supplied Lcseimpuls. The second timing circuit ZES has a delay time OK + ts. Your delay time is therefore greater than that of the time circuit ZEB. The delayed read pulses LESS are then fed to it when it has been determined in the second circuit arrangement SA 2 that the pulse distance to the previous read pulse was greater than the pulse spacing to the subsequent read pulse. The corresponding lcse pulse is thus delayed longer than the lcse pulse supplied to the T'cit circuit ZEB. The third time circuit ZEF finally has a delay time / 0 f /, that is to say a smaller delay time than the first time circuit ZEB. You are offered the read pulses LESS , of which the second circuit arrangement SA 2 has determined that the pulse spacing to the previous read pulse is smaller than the pulse abslarni to the subsequent read pulse. The corresponding reading pulse is thus delayed by a shorter time than that of the timing circuit ZEB indicated reading pulse The outputs of the three ringing signals ZEB, ZES and ZtT are fed to an OR circuit 91 and the equalized reading pulses appear at the output of this OR circuit

»Ο The function of the equalization circuit according to F i g. 2 should with the help of the pulse plan of Figs. 4. 5 and 6 to be clarified even more. In Fig. 4 to d are in the first line the information written in the magnetic layer memory, in line 2 the Sthrcibsignal, in line 3 the read pulses are drawn. You can clearly see how the corresponding read pulses when a frequency jump occurs compared to the writing signa] are shifted in time. Such a line shift is given at Lescsignalcn 2. 4, 5, 7. When the second read pulse occurs, the equalization circuit sets determines that the pulse spacing to the previous, the first read pulse, is greater than the pulse spacing to the following, the third Lcseimpulse.

Then in the emitter circuit of FIG. 2 in the circuit arrangement SA 2, the circuit GR will respond and cause the read pulse delayed by the shift register SCH to be fed to the second timing circuit ZES . The read pulse 2 is thus shifted in time in the direction of the third read pulse, to be precise by such an amount that it comes to be below the corresponding writing signal in terms of time. When checking the third read pulse, the equalization circuit comes to the result that the pulse spacing is equal to the previous one: the second read pulse, and the following, the fourth read pulse. The first circuit arrangement SA 1 thus emits a signal and causes the read pulses delayed by the shift register SCH to be passed to the first timing circuit ZEB . It is then only shifted in time by the basic delay time i- / 0. When checking the fourth read pulse, the equalization circuit determines that the pulse spacing to the previous, third read pulse, is smaller than the pulse spacing to the following, fifth read pulse. Then the circuit KL responds within the second circuit arrangement SA 2 and the associated read pulse delayed by the shift register SCH is offered to the third time circuit ZEF , which delays this read pulse by a smaller delay time than 3ie the basic delay time / 0. The read pulse is thus shifted in time in the direction of the third read pulse. The equalization circuit then continues to operate accordingly for the further read pulses.
Since with a frequency jump the external reading

609 612/177

pulses must be shifted in the direction of the middle read pulse of the higher-frequency signal sequence, so in the pulse plan of Fi g. 4 to b once to the right (see reading pulse 2) and once to the left (see reading pulse 4), the correct reading pulses in relation to the write signal must also be shifted in time by a timing circuit (ZLB) , because this is the only way to achieve that a read pulse can be prematurely timed compared to its normal time slot.

In Fig. 3 the structure of the equalizer circuit with digital components is shown. The mode of action this circuit arrangement is to be used in conjunction with the timing diagram of FIG. 4 to 6 are explained. It the directional clock font has been selected and the writing signa] is recorded in line 2. From Read pulses derived from the read signal peaks (/! eile 3) represent the information times and contain the peak offset that can be traced back to the frequency hops in the write signal. the Numbers in FIG. 3 the lines in F i g. 4 to 6 indicate in which the occurring at these points Signal is shown.

The first circuit arrangement contains the NAND elements, V 8, N9 and NG 3, the second circuit arrangement contains the NAND elements N10, / VIl, ΛΊ2, N13 and NGA. Common to the first and second circuit arrangements is a selection circuit made up of a pulse separation circuit and a pulse generation circuit. At its one output the pulse interruption circuit emits the read pulses which are a long way apart from the preceding read pulses and at its other output the read pulses which are a short distance apart from the preceding read pulses. The pulse separation circuit is shown in FIG. 3 from the flip-flop FFI 4, the NAND gates ΛΊ. Nl. The Zcitschaltungen ZLi, ZEA and the NAND elements Λ / 3, NA, NS, V6, NGX. NGl. The pulse generation circuit is connected to the pulse transmission circuit and consists of the fiip-flops IFSPK and FFSPL and the NAND gate, V 7. The pulse generation circuit generates, on the one hand, pulses of a duration that are determined by the trailing edge of the read pulses with a short pulse spacing, and, on the other hand, pulses of a duration equal to that of the trailing edge of an initial reading pulse. which has a long pulse spacing to the previous read pulse and the trailing edge of the next pulse, which has a short pulse spacing, is defined. The first timing circuit ZEIi consists of the delay element VEB and the NAND gates Af 18. "Ν 17,; V16, the second timing circuit ZEF consists of the delay element VEF, the NAND element N 14 and the flip-flop FFF and the third timing circuit ZES from the delay element VES, the NAND element N 15 and the flip-flop FFS.

With the aid of a shift clock T (line 4), the reading pulses LES (line 3) in the shift register SCH are shifted in time by approximately ^: η main flow change periods. The time-shifted read pulses are shown in line 17 of FIG. 4 to 6 shown. They are called LESS . The further processing of the delayed read pulses LESS is described later.

The flip-flop FFJ 4 (line 5) is toggled by the positive edges of the read pulses LES (line 3). The positive edges of the output signal of the flip-flop FFJ 4 (line 5) trigger the timing circuit ΖΔ "4 (line 6), the negative edges of the output signal of the flip-flop FFJ 4 trigger the timing circuit ZES (line 7). After about 7O ¹¹ In a main flow change period, the time switches Zf 4 and ZES return to their original state.

With the help of the timer Zf 4 and ZES and Louischen Schaltuimen. consisting of the NAND elements .V 3. .V4. Λ'5. ; V6, NGX, NGl, it is determined whether the interval between two successive reading pulses is short or long. In line S. that is to say at the output of the NAND element NGl, the read pulses appear at short intervals, in line 9 of FIG. 4 and 6, i.e. at the output of the NAND gate

ι? NG 1. the read pulses of long distances.

To determine whether the pulse spacing between the successive read pulses is equal or unequal and whether the distance between a read pulse and the preceding and following read pulses is greater or less, further parameters are required. The flip-flop F! SPK in each case from the negative flank of the output signal of the NAND element, Vf? 2 (line 8) flipped !. The output signal of the flip-flop FFSPK is shown in line K). The flip-flop FFSPL is set by the negative edge of the output signal of the NAND element / VCl (line 9) and is reset by the positive edge of the output signal of the flip- FUy-FFSPK (line H)) If this is done, a certain phase relationship must be established between the output signals of the NAND elements .VG 1 and .VG 2 and the flip-flop FFSPK . The synchronization of the flip-flop FFSPK takes over from the output signal of the NAND element .VG1 (line 9) signal (line 12) derived by inversion by the NAND gate Λ'7, which is fed to the flip-flop FFSPK.

Due to the two short or two long pulse distances, two successive read signal distances can be equal. For this purpose, the coincidence of the Auscancssicnalen of the NAND element NG 1 (line 8), the "flip-flop FISPK (line 10) and the negated output signal of the flip-flop FFSPL is determined and, on the other hand, the coincidence of the output signal of the NAND element .VG 1 (line 9), of the flip-flop FFSPL (line 11) and the negated output signal of the flip-flop FFSPK

F i g. 4 to 6 after the fourth read pulse, after the seventh read pulse and after the ninth read pulse educated. At these times you can see that the two preceding read pulse intervals are each the same. In the first two cases the read pulse intervals are small, in the third case the reading pulse spacing is large.

Two successive read pulse intervals can be achieved by the sequence of a large and a small Be unequal or in reverse order.

To generate the "UNEQUAL" signal (line 14), the coincidence of the evaluation sjssicnale of the NAND element NG 1 (line 8), the flip-flop FFSPL (line) and the negated output signal of the

Flip-flops FFSPK on the one hand and on the other hand the coincidence of the output signals of the NAND element / VG1 (line 9) and the negated output signals of the flip-flops FFSFK and " FFSPL ." The

11 ° 12

Signal »UNEQUAL« (line 14) is generated after the third ZEB runs with the basic delay time / 0 and buten, fifth, sixth and eighth read pulse. Det with the back edge an output pulse (Zei-At these times it can be seen that the two Ie 25), the the third read pulse (line 26) and the preceding Lcseimpulspulsen are unequal. tugged generated.

In the first case (3rd read pulse) it is 5. Then it is determined that the sequence of

a long / short, in the second case (5th read pulse) pulse intervals are short and long and thus an off

by a short / long, in the third case (6th read pulse) output signal at the output of the NAND gate ΛΊ3

formed by a Lang / Kur /.- and in the fourth case (8. Lescim- (line 16). This creates the flip-flop FFS

pulse) by a Kurz'l.ang-ep. The sum of the set. This happens, for example, after occurrence

Equal and unequal mini-pulses must always be equal to 10 of the fourth read pulse. The assigned fourth

the number of read pulses c. The read pulse is sent through the shift register SCH

To indicate the direction for the equalization process hesitates and resets the flip-flop FFS (line 18). In order to be able to do so, it must be possible to distinguish between the signals "NOT EQUAL" The return line of the flip-flop FFS (line 14) whether the two additional elements VEF (line 19) start up. The unequal pulse intervals that exist in the time of the delay element VEF are equal to the differential sequence long / short or short / long. For l'erenz from the basic delay time OK and one the formation of the signal "GREATER" (line 15), line //, which also depends on the degree of distortion, ie that the pulse spacing is first large and then the tape head system of the magnetic layer storage device is small. the coincidence of the output signals is directed. The Rückllankc of the output signal of the flip-flop FFSPL (line 11) and the NAND 20 delay element \ EF (line 19) generates an element NG 4 (line 14) and the negated output pulse (see line 20), which the premature, so cntsignales of the flip-flop FFSPK detected. That caused the dragged fourth read pulse (line 26).
Signal »SMALLER« (line 16), ie. The consequence for the processing of the further reading pulses is short and long becomes due to the coincidences. the negated process is analogous to this.
Output signals of the flip-flops FFSPK and FFSPL 25 Line 26 shows the processed, equalized read and output signals of the NAND element NG 4 pulses. The dashed pulses show (line 14) formed. the position of the originally distorted read pulse c

One now has knowledge of the type of im- Die in the arrangement my F i g. 3 pulse intervals used, the reading pulses follow one another. ZcitschalHingcn can contain Ycr / ögerungsglicdcr-This is exploited, on the basis of the sliding keys, which are built up as dual counters.
gisterSCY / zeitlk 1 shifted read pulses (line F i g. 1 shows - as already explained above - 17) to have an equalizing effect. The basis for the peak offset, based on a main flow change equalization, is the knowledge that the outer reading distance is plotted against an Lcsesignalsequc. In the case of signals (first and last) of a high-frequency constant frequency of the read signals, no read signal sequence occurs to the outside, ie from the center 35 peak offset. Only when a frequency jump in the Lcsesignalsequc are pushed away. The first is present, that is after the 5th bit in FIG. 1, so if the read pulse is replaced by a read pulse train, the previous bits must be displaced over time. The result is borrowed late and the last read pulse of a read, thus the peak offset, which is premature in time in the extended pulse sequence. This is done with the curve shown.
Help the first, second and third timers. 40 The letter F on the fifth and on the seventh

The output signal of the NAND gate ΛΊ2 bit means that these bits arrive earlier.

(Line 15) sets the flip-flop FFS (line 21). The fen must, that is, that here the time switch ZEF

now the next to arrive, through which the sliding must become effective. to reduce the center offset

registcr SCH read pulse (line 17) sets lower. The letter .S in the sixth bit says-

the flip-flop FFS back. The Rückllankc of the flip 45 against. that the bit must arrive later, ie

Flops FFS leaves the delay element \ 'ES (line 22) that the time switch ZES must take effect here,

start up. The running time of the delay element is set to reduce the peak offset,

is made up of the basic delay time rO Dci degree of correction of the equalization circuit. i.e.

for the read pulses that are not to be equalized ■ -. ■ one of the amounts of time in the time circuits ZEF and ZES

Time /.v, which depends on the degree of distortion of the 50, must be measured in such a way that the equalized

Magnetic layer storage device. The back of the reading signal has the smallest possible residual peak distortion.

Output signal of the delay element VES (22) set, ie as close as possible to the zero line

generates a pulse (line 23). that of the OR of the ordinate. The degree of equalization says

Circuit Ol is supplied and on a pulse by how many percent a peak offset is present

regenerator MK is directed. This generated at its 55 is reduced. The time amounts for the time switch

The equalized read pulse at its output (line 26). tungcn ZES and ZFF can be chosen the same.

The third through the shift register SCH gclau- It is also entirely possible to use them differently

fene read signal (line 17) does not need to select equalized in order to adapt to the conditions of the system

will. To be able to adapt better to the outputs of the NAND elements N 12.

and / V 13 then no signal has been ^{generated and 6} ° The digital equalizer circuit takes effect in the

The time switches ZES and ZEP are not activated in writing at the corresponding points

been. The case that an Lcsesignal is not equalized and reduces the peak offset. The after

must be so that the pulse spacing before and the equalization results in the resulting peak offset

after the Lcsesignal are equal, can thus be drawn from the strkhlicrtcn line in Fig. 1. How to

the coincidence of the negated output signals of 65 can be seen, the peak offset has significantly changed

Zcitschaltungen ZES and ZEF and the delayed small.

Read pulse determined and thus the timing circuit to determine the delay time with the

ZEB must be started (see line 24). The time circuit, the time circuits ZEF and ZES run, can be

proceed in the same way: The arithmetic mean of the maximum and minimum occurring Peak offset determined at the bistable locations to be corrected. This results in a manipulated variable:

Manipulated variable =

S _{max means} maximum tip offset, S _min minimum tip offset.

The degree of rectification E for the peak offset is then according to the definition:

- (S _m g _X - manipulated variable)

By inserting the manipulated variable given above and transforming the equation, one obtains:

In this example it is assumed that the delay time of the timing circuits ZEF and ZES is the same.

jo The amount of equalization can easily be set by changing the delay time with which the timers run. This means that the time circuits ZEF and ZES must be influenced. Are as time switches ZES and

ZEF dual counter is used, then only the amount to which the dual counter counts has to be changed.

In addition 6 sheets of drawings

Claims (11)

Patent claims: 1.Digital equalization circuit for equalizing read pulse sequences supplied by magnetic layer memories, which contain frequency jumps causing phase shifts of individual read pulses, the read pulses being shifted in time immediately after and before a frequency jump and where, depending on the read pulse sequence, timing circuits for delaying the read pulses can be sounded in, characterized by a shift register ISCH), which delays the reading pulses for the duration of the review of the reading pulses, by ♦ ine first circuit arrangement (SA 1), which determines whether the distance of a reading pulse to the preceding and the following reading pulse is the same and in this case the assigned one the shift register passes the delayed read pulse to a first timing circuit (ZEB) , through a second circuit arrangement (SA 2), which, if the pulse spacing of a read pulse to the previous and subsequent read pulse is not equal, if a long pulse is present s distance to the previous read pulse at least the assigned read pulse delayed by the shift register passes to a second timing circuit (ZES) with a greater delay time than that of the first timing circuit (ZEB) and, if there is a long pulse distance to the subsequent read pulse, at least the assigned read pulse from the shift register (SCH) delayed read pulse leads to an idrilte timing circuit (ZEF) with a shorter delay time than that of the first timing circuit (ZEB) . 2. Digital equalization circuit according to claim 1, characterized by a connection circuit (VK) which is connected to the shift register (SCH) and according to (the output signals of the first and second circuit arrangement (SA 1, SA 2) the read signals to do three to the logic circuit (VK) connected time circuits (ZEB, ZES, ZEF) forwards whose outputs are connected to the inputs of an OR element (0 1). 3. Digital equalizer according to claim 1, characterized in that in the event of inequality of the pulse intervals before lind after a read pulse, the second circuit arrangement (SA 2) when there is a long pulse interval to the previous read pulse and several short pulse intervals in the subsequent read pulses to the tested Read pulse following read pulse leads to another timing circuit with a delay time between the delay times of the first and second timing circuit and, if there are several short pulse intervals before the read pulse to be checked and a long pulse interval to the subsequent read pulse, the read pulse before the tested read pulse is transferred to another Zeitschal-Uing with a delay time lying between the delay lines of the third and the first timing circuit. 4. Digital equalization circuit according to one of the preceding claims, characterized in that the first and second circuit arrangement (SA I, SAl) a selection circuit from a pulse separation circuit (FFJ4, Nl, Nl, ZE3, ZE4, N 3, N 4 , vV5, N 6 NGl, NGl) and a pulse generation circuit (FFSBK, FFSPL, Ll) is common, since the pulse separation circuit at an output; emits the read pulses which have a large pulse spacing from the previous read pulses and at the other output the read pulses which have a short pulse spacing from the previous read pulses, and that the pulse generation circuit is connected to the pulse separation circuit and at its one output pulses from the generated by the trailing edge of a pulse appearing at the other output of the pulse separation circuit and the trailing edge of the next duration set to Letenden pulse at the other output! and at its other output it emits pulses of the duration determined by the trailing edge of the pulse appearing at one output of the pulse separation circuit and the trailing edge of the next pulse appearing at the other output of the pulse separation circuit. 5. Digital equalization circuit according to claim 4, characterized by a pulse separation circuit from a first flip-flop (FFJ 4), from a fourth timing circuit (ZEX), which via a NAND element (NY) on the one hand with the non-inverted output of the first flip-flop (FFJ 4), on the other hand connected to the input of the read pulses, from a fifth timer (ZES), which through another NAND gate (Nl) to the inverted output of the first flip-flop (FFJ4) and the input for the Lescinipuise is connected, from a first logic circuit (jV3, N4, NGl) which, when the read pulse coincides, the inverted output signal of the first flip-flop (FFJ 4) and the inverted output signal of the fourth row circuit (ZE4) or the read pulse, of the non-inverted output signal of the first flip-flop (FFJ 4) and the inverted output signal of the fifth timing circuit (ZES) selects the reading pulses that have a large pulse spacing from the previous reading pulse uls, from a second logic circuit (N5. NC), NG 2), which occurs when the read pulse, the mvertiericii output signal of the first flip-flop (FFJ 4) and the non-inverted output signal of the fourth timing circuit (ZE4) or the read signal, the non-inverted output signal of the first flip-flop (FF / 4) and the non-lost output signal of the fifth timing circuit (ZF. 5) selects the read pulses which are at a short pulse distance from the previous Lcsc pulse. 6. Digital Enzerrerschaltung according to claim 4, characterized by a pulse generating circuit from a second flip-flop [FFSPK) which is connected to the output of the second logic circuit and which is reset by the output signals of the second logic circuit ccsetTt and and from a third flip -Flop (FFSPL), its set input is connected to the output of the first logic circuit and its reset input to the output of the second. Füp-Flops (FFSfK) is connected. 7. Digital equalization circuit according to claim 5 and 6, characterized by a second circuit arrangement with a third logic circuit (/ VlO, .VIl, A / G4), the inverted output signal when the non-inverted output signal of the third flip-flop (FFSPL) coincides the third flip-flop (FFSPL), the inverted output signal of the second flip-flop (FFSPK) and the Ausgan ^ ssignales the first logic of the second flip-flop (FFSPK) and the output of said second logic circuit and upon coincidence of the inverted output signal Circuit generates a signal that indicates the inequality of the pulse intervals before and after the read pulse, from a NAND gate (N 12), which when the non-inverted output signal of the third flip-flop (FFSPL) coincides, the inverted output signal of the second flip-flop (FFSPK) and the output signal of the third logic circuit emits a signal indicating that the pulse spacing before the read signal is larger r is the pulse spacing after the read signal and from a further NAND element (N 13), which occurs when the inverted output signal of the second flip-flop (FFSPK), the inverted output signal of the third flip-flop (FFSPL) and the output signal of the third logic circuit . emits a signal which indicates that the pulse spacing before the read signal is smaller than after the read signal. 8. Digital equalization circuit according to claim 7, characterized by a second timing circuit (ZES) consisting of a fourth flip-flop (FFS), the set input of which is connected to the output of the NAND element (N 12) and the reset input of which is the negated output signal of the shift register ( SCH) is supplied, from a NAND element (NlS), which is connected to the output of the shift register (SCH) and the output of the fourth flip-flop (FFS) and from a delay element (VES) which is connected to the output of the NAND - Member (N 15) is connected and its delay time is greater than the delay time of the first timing circuit (ZEB) by the amount ts. 9. Digital equalizer circuit according to claim 7, characterized by a third timing circuit (ZES) consisting of a fifth flip-flop (FFF), the set input of which is connected to the output of the NAND element (Nl 3) and the reset input of which is the negated output signal of the shift register ( SCH) is supplied, from a NAND element (Λ / 14), which is connected on the one hand to the output of the fifth flip-flop (FFF) and the output of the shift register (SCH) and from a delay element (KZTF), which is connected to the The output of the NAND element (N 14) is connected and its delay time is smaller by the amount tj than the delay time of the first timing circuit (ZEB). 10. Digital equalization circuit according to claim 7, characterized by a first timing circuit (ZEB) consisting of a NAND element (N 18), the first input of which is the output signal of the shift register (SCH), the second input of which is the negated output signal of the second timing circuit (ZES) and the third input of which the negated output signal of the third timing circuit (ZEF) is fed and from a delay element (VEB) which is connected to the output of the NAND element (N 18). 11. Digital equalizer circuit according to one of the preceding claims, characterized in that when the read pulse frequency changes, the supply clock of the shift register (SCH) and the three timing circuits (ZEB, ZES, ZEF) are switched over.