DE2142584C3 - Scanning device for a recording medium containing both clock information and data information - Google Patents

Description

The invention relates to a sampling device for both clock information and data information having a recording medium, with a scanning of this information Scanning head arrangement, furthermore with a buffer in which in the rhythm of the scanned Clock information the scanned data information (ions are stored, and with a separate, for emptying the intermediate storage after a further storage with compared to the Einspeicber speed different speed serving clock signal source with the two-page memory via a switch from filling to emptying or from emptying to filling the buffer effecting switching device is connected.

With one from the German interpretative document

is 1040 830 known scanning device of this type a common one for reading the data information and the clock information of the recording medium Scanning head provided, from the output of which a clock pulse sequence by means of special sound circuits

it can be derived in this way which controls the filling of a buffer store via a switching device. Is the If the buffer is filled, the switchover device changes the control of the buffer for the purpose of emptying after a

> s nem main memory to another control signal source.

However, the known scanning device is for manual evaluation on the scanning head arrangement recording medium to be moved past is not suitable, since in the known device the changeover from filling to emptying the intermediate storage at will after a certain time by changing over the switching device takes place, this switching to the speed in the known device of the mechanically moved recording medium can be adjusted, while in the case of the movement of the recording medium of Hand, for example when a passenger moves a boarding pass through the scanning device by hand, this is expected must be that if the switch from filling to emptying the buffer is too early, a faulty or incomplete sampling is present, while in the case of a very late switchover the entire Device works too slowly. Even if you have the changeover through the switching device makes dependent on the filling of the buffer, would be with the known scanning device error-free scanning of recording media moved by hand is not guaranteed, since a switchover to empty the buffer to the main memory would also take place if with the omission of certain data information, the buffer is only somehow filled with further information which is then passed on to the main memory, although it is error-prone.

The object of the invention is to be achieved, a scanning device of the type briefly described at the outset Art to be designed in such a way that even with irregular and non-uniform movement of the recording medium by the scanning device only from a complete, proper Sampling obtained data information from the buffer to the further memory

are submitted and come to the evaluation.

According to the invention, this object is achieved in that for sampling the clock information and the data information by hand through the scanning device

bindable recording medium in itself as is known, separate scanning heads are provided in each case are of which the scanning head used for clock information scanning is used to actuate the Unischalteinrichtiing with this Uraschalteinrichtung is connected, soft by means of one of the clock information scanner controlled counter can be triggered when a soil counter reading is reached.

This design of a scanning device has compared to corresponding, known devices furthermore the advantage that the soli counter reading of the mentioned counter can be set as desired, so that the switch from filling to emptying of the Buffer not from a predetermined period of time or from the capacity of the Intermediate storage is necessary dependent, but on the respective length of the recorded data information can be tuned, so that in one and theseioen scanning device different things Recording media can be evaluated.

It is from the German interpretation 1153559 Although known, separate scanning heads are used for scanning data information and clock information to be provided, but with this known arrangement there is no intermediate storage for section-by-section Ans - .. imulation of data information before the ^ 'cütigabe to a main memory with increased Clock speed provided so that the problems described above do not occur here anyway. Optical card readers are primarily used here, but it goes without saying that the proposed Solution in the same way also on card readers for magnetic cards or punch cards or for Cards with a stamped code can be used.

If the scanning device is used in connection with a central arithmetic and logic unit, then the other Memory part of the digital arithmetic unit. It can use the information read from the cards supplied and possibly stored information to a visual display and to various other evaluation devices are transmitted, for example to turnstiles or others Facilities, for example at an airfield.

In addition, expedient refinements of the scanning device according to the invention form the subject matter of the attached subclaims. Embodiments of the invention are described below under Explained with reference to the drawing. Put it

Figure 1 is a block diagram of a card scanning system and a data transmission system,

Fig. 2 is a block diagram of an embodiment a card reader,

Fi g. 3 a series of waveforms for descriptive purposes of the various signals as generated at certain points in the embodiment of FIG will,

4 and 5 are sectional views of a scanning head for a card reader, FIG. 4 being a section corresponding to that shown in FIG Section line 4-4 shows

6 shows a more detailed circuit diagram of a card reader and

FIG. 7 is a logic diagram of one shown in FIG Circuit component.

In Fig. 1, a scanning device is that proposed herein Type containing scanning system shown in the form of a card reading system. On the readhead assembly containing card reader 10, which is described in more detail below in connection with FIG. 2 to 7 is used for optical scanning of a card written with encoded data, wel-S before it can be inserted into the card reader and is formed, for example, by a boarding pass, as is currently the case with sk but without coding, is used by airlines. The card reader can use the Scan the card regardless of the speed at which the card is scanned through the card reader from This is done manually, as the code marks on the card contain both data information and timing information included, whereby the synchronism of clock pulse trains and data pulse trains unsabs depending on the clock speed or data rate is ensured.

The output of the card reader can also simply be used to generate certain control signals, for example to open a turnstile for a gate lock when the passengers pass their encoded boarding pass through the card reader. It goes without saying that the code used will be changed from day to day in such a way that, if necessary, forgery is not possible . If, in the embodiment according to FIG. 1, the coded information on the card is read by means of the card reader 10 at a first location A , then this information on the card or the boarding pass is sent to a central processing unit 12 for storage. In the same way, a card tenant 14 scans at a second location B, which can be formed by a further gate barrier, the coded information from another card or another boarding pass and then also supplies this information to the central arithmetic unit 12 any number of such card readers can be provided.

While the system described is an optical card reading system, it will be understood that magnetic Scanning devices in connection with magnetic code mark carriers, scanning devices for punched code marks in connection with corresponding code mark carriers and punch card scanning devices in connection with punch cards each formed in the manner proposed here can be. In any case, in the case of the scanning systems, the synchronization problem in detail can be caused by this be solved that in a known manner, the clock information in immediate assignment and the same coding as the data information is applied to the card in question and the scanning device responds to this coding method.

Display means 16 and 18 are provided at locations A and B , which are assigned to card readers 10 and 14 and are used to display the information encoded on the cards as well as various other data that are stored in arithmetic unit 12 , for example flight number, destination, free Co seats, etc. Logical adaptation schemes are designated by 20 and 11 , respectively. A chain printer or teleprinter 24 is controlled by the arithmetic unit 12 when printed information is desired, for example the printing of tickets for flight passengers.

Referring to Fig. 2, let us now see a scanning system for encoded cards written on. If the encoded area of cards, for example that in

4 is moved past photodetectors 62 and 64 of the scanning head assembly, so that Light is either reflected from the relatively bright background or experiences upon impingement Code marks no reflection, so that either signals generated by the photodetectors 62 and 64 or are not generated, wherein the photodetectors can be formed by phototransistors or photodiodes. Since, according to one embodiment, the data coding in the form of an increased length of the clock code marks is present, causes a change in the speed of insertion or bypassing the card on the scanning device only a change in the clock speed, so that the The data pulse channel 58 and the time pulse channel 60 are synchronous despite the changes in the clock speed remain.

Curve α according to FIG. 3 illustrates the clock pulses which are generated in that the clock code marks migrate past the photodetector 62, as can be seen from FIG. The data code marks which adjoin certain of the clock code marks generate pulses which are shown in FIG. 3 are drawn in at c and which occur simultaneously with the corresponding clock pulses according to FIG. 3a. Since there is no separate clock pulse generation in the device due to the self-synchronization in the system, the clock pulses that can be picked up from the output of the photodetector 62 are amplified in the clock pulse channel 60 by means of a preamplifier 66, while the data pulses that can be picked up in the data channel 58 from the output of the photodetector 64, can also be amplified by means of the preamplifier, 68.

Simultaneously with the pulse ridge of the clock pulses, a delay circuit 70 generates which the amplified clock pulses from the preamplifier 66 are supplied, each with a delayed Im pulse of about fifty microseconds in duration as shown by curve 36. The delay circuit 70 can be practically a monostable multivibrator contain.

A hold circuit 72, which can practically contain an astable multivibrator of known type, is from the pulse front of the amplified data pulses from the preamplifier 68 according to the Waveform 3c triggered or set to create a condition corresponding to a logical ONE if data is present and a condition is appropriate a logical ZERO occurs when there is no data and the hold circle 72 is not classified, as can be seen from Fig. 3d can.

The data output of the hold circuit 72 becomes the series input of a shift register via a switch 76 78 controlled supplied, which in the present embodiment, thirty-two digits to accommodate the thirty-two clock symbols, or bits, whichever of thirty-two Code marks are generated on the code mark carrier or the card. The shift register acts as a Buffer for transferring data received by the shift register with different To enable speeds on an arithmetic unit 80, with a different and preferably significantly higher clock speed is effective, which will be discussed in more detail below will.

In the clock pulse channel 60, the output of the delay circuit 70 is fed to the clock pulse input of the shift register 78 via a switch 74, which contains a logic circuit, for example dual NAND gate elements and serves to set the clock for the passage of the data pulses from the data pulse channel 58 through the Supply shift register. The two switches 74 and 76 can be distinguished in their interaction as a switching device bete. The impulse front of the pulse from the output of the delay circuit (see curve ib) causes the advancement of data in the shift register, while the impulse back of the same pulse resets the holding element 72 to the logic state corresponding to a ZERO.

The waveforms 3a and 3c symbolize clock pulse trains and data pulse trains ideally Shape. In practice, the clock pulses can lead or lag the data pulses somewhat

ao or wider or narrower than the data pulses. Data as they come in handy in a code scanning system can occur are shown in Fig. 3e. The irregularities in the data pulses can have various causes, including differences in the sensitivity of the photodetectors 62 and 64 and variations in the quality of the printed matter Code marks on the recording medium are to be mentioned, so that there is a misalignment the time or clock coding and the data coding can come, which results in clock pulses, which triggers an advancement in the sliding index 78 between the occurrence of data pulses which would result in a loss of data symbols or data bits. However, this danger is through delay circuit 70 and hold circuit 72 avoided.

The first data pulse of curve 3e corresponds to the case where a data pulse occurs before a clock pulse. Without the holding effect, the impulse forehead would

of the pulses from the curve 3fr occur after the first pulse of the pulse train 3e is already over, so that a sampling error move into the shift register would. The ideal hold circuit output shown by curve 3d is provided by the pulse front of the data pulses triggered and then remains triggered even if the data pulse disappears or a logical one N ULL occurs, so that the state corresponds to a logical ONE remains until the data pulse is entered into the shift register and the duration of the data

so tenimpulses is extended so far that this impulse coincides with a corresponding clock pulse, as can finally be seen from FIG. 3f. The case in which a clock pulse occurs before a data pulse is shown in curve 3e at 2. The in the

S ₃ pulse sequence ie pulse 2 shown sets the hold circuit, the pulse front of the delayed pulse allowing the output of the hold circuit to move further into the shift register, while the pulse return of the output of the delay circuit 70 causes the hold

circle 72 resets.

In the case in which the data pulse is narrower than the clock pulse, which is the case in the pulse train 3e at 3 shown, data is lost before the clock pulse arrives, so the same difficulties arise here.

th would occur, as in the case of pulse 1 of the Pulse train 3p namely when the data pulse occurs before the occurrence of the clock pulse. Here the holding circle 72 engages in the same way, correcting

7 * 8

rend a. If the data pulse is wider than the clock position of a pulse counter, it can be used.

pulse is what is indicated in the pulse train 3c at 4 The output of the arithmetic unit is then to

is, then the same difficulties arise as in the supply of an evaluation device 84 used which

Case of the pulse 2 from the pulse train 3p, namely from a data display device or a driving

when the clock pulse arrives in front of the data ticket printer or other peripheral equipment

pulse, and the correction is achieved in the same way gene can be formed.

As in the case of the pulse 2 of the pulse train 3c It is possible to use the switch 74 independently of the

As already mentioned, the clock speed control of the counter 82 is to be set so that it is changeable, since it is a function of the speed of the clock pulses of the clock pulse channel 60, with which the code marks are on the up> o and on the other hand when they are reset the Taktimzcichnungstrjiger or the card in the card reader to pulse of the arithmetic unit 80 brings into effect. In the photodetector 62 passed and scanned in the same way, the switch 76 can be controlled by the control. This variable clock speed can be made independent by the counter 82 and forms one input for the switch 74, while when the data from the data channel 58 is set, the other input allows the clock speed of the receiver to pass until it is reset by the arithmetic unit 80, which Of course, this is done by the plant 80 in order to create a cycle that is formed in the Schicberegijenigcn speed with which the existing data 78 can be brought about. It should be noted again that the data is entered into the memory of the arithmetic unit, that the switches 74 and 76 are bcn. If all thirty-two clock pulses are NAND gate switches,
all associated data on the way via the switch. In FIGS. 4 and 5, a scanning head for a ter 76 is introduced into the shift register 78, so that the Kodc scanning system is shown. A card 30 with code marks 37 printed on switch 74 to switch the shift register, which can be formed from black ink 78 from the clock from the clock pulse channel 60 on or from printing ink or from a non-reflective clock from the arithmetic unit, and which can be formed in the substance, The data contained in two Fotode transmission registers are then passed into the as detectors 62 and 64, which are sent to the Abta-Rcchcnwerk 80 with a second speed of clock code marks or data code marking cgcbcn, which is the one that is used in the arithmetic unit. The card is made of paper, which is used. is so light that the photodetectors

If for any reason the arithmetic logic unit 80, 62 and 64 passes by, switch to scanning once no data from the shift register 78 is used for 30 clock code marks or data code marks, The card is made of paper, which has such light response loops provided, which is inflected from the output that the photodetectors 62 and 64 nordcs Shift register 78 via switch 76 to repeatedly open light reflected from card 30 Shift register 78 leads. Data from data taking, but no light from those areas Impulse channel 58 can therefore not be received into the slider 35 of the card on which the non-reflector is located 78 can be entered while code marks 32 are located in the back of the slide. The order Register data circulate. Is then the arithmetic unit 80 of the folodetectors 62 and 64 with reference to the Kobcrcit. to record the circulating data, markers 32 will be located. The arrangement of the photo codes the data under control of switches 74 detectors 62 and 64 with respect to the code marks and 76 laktwcisc taken from the shift register 78- 40 32 can be seen in the drawing through a cutout Men and new data can again be recognized by the data 34 of the card 30. Becomes a card Pulse channel 58 get into the shift register 78, introduced for scanning in the card reader, so is from where they then either pull the arithmetic unit 80 - they are supported vertically so that the code marks the or, in turn, carry out a data cycle of folodetectors always at the same level opposite one another. Time pulses "or clock pulses of two 45 hen. The coding is different in the manner shown Speeds from sub-preferred dimensions along the lower edge of the card Schicdlichen pulse sources are therefore used for operation and the card can be on a strip 46 one and the same shift register. stand up to hold the card level,

A self-checking feature of the circuit is activated when, for example, manually in use reached by means of the counter 82, which led to three-two 50 airfields through a boarding pass reader Has big spots and the clock pulse counts, which is the one.

Exit delay circuit 70. If a card Fi g. 4 corresponds to a section along that in FIG. 5

pulled out or not completely through the section plane 4-4 indicated by the map, and the bar 36 biltenreader out, so are not the code marks det the lower part of an opposing wall corresponding to all thirty-two clock pulses 55 38, which are used to perpendicular to the card to be scanned sen and the associated data scanned or, if and, the code marks opposite the photo detectors a counterfeit card is presented, 62 and 64 are not to be kept aligned with the clock having all thirty-two clock pulse code marks code marks opposite the photodetector 62 and the imprinted. In these cases, the counter prevents data code marks from the photodetector 64 82 that data is aligned to shift register 60 via switch 76.

stcr 78 are transmitted and that an incorrect data

output is generated. But if the count is correct, the form can consist of a block of transparent or so the counter 82 effects a changeover on the switch transparent material with opaque or 74 and an emptying of the shift register 78. Exist over black outer layer 42, whereby a a connection to the arithmetic unit 80 can be self-65 side lighting or a light guide dunes understandably the counter 82 depending on the intended purpose when receiving light from a light source th purpose any desired counter reading entered 44 diffusely through the transparent block 49 will. Also there is a different control schahting, from where the light only goes to the one not with one

«9« 37/129

The area 46 provided with the outer layer can emerge, which also surrounds the openings of the photo detectors 62 and 64. The photo detectors can be the optically effective Scan code marks, as the individual Fotodetektprelemente, which for example a Phototransistor can contain, also provided with opaque covers 48 and 49, respectively are so that no over the transparent St. (Kk 40 transmitted light fall on the Folodctckitorcn can, but only light reaches the photo detectors from the transparent block 40 via the uncoated area 46 has emerged, has reached the card 30 and from there to the photosensitive Receiving surfaces 51 and 52 of the photodetectors 62 and 64 is reflected and thereby scanned can be.

The light source 44 is still with an opaque one Cap 53 provided to keep all light within 40 m of the clear block. connections 54 and 55 are connected to the positive and negative terminals of a battery 56, respectively.

6 shows a circuit diagram of a card reader system, in which parallel outputs of the shift register 78 can be used, a simple To form a code, which when compared with a default condition in a code comparator or with Actuation of a group of normal mechanical switches, for example when used on one Gate can cause the operation of a turnstile or a barrier through which the passengers must leave before boarding an aircraft.

Time information and data information are obtained from an encoded data card scanned by means of the phototransistors 100 and 102, with clock pulses via a line 108 to a generally designated 104, two-stage clock pulse preamplifier are transmitted while the data pulses over a line 110 to a similar, generally designated 106, two-stage Data pulse preamplifier are performed. The preamplifiers 104 and 106 are two-stage field effect transistor preamplifiers, which have a high input impedance generally in excess of five megohms and a gain of about have one hundred.

The clock pulses which occur on line 108 are passed through a filter capacitor 114 and a bias circuit is routed across resistors 112 and 126 which are of a sixteen Volt carrying line 128 are fed from, as well as the resistor 116 and that at 120 grounded Potentiometer 118 includes so that the clock pulses eventually to terminal 122 of the field effect transistor 124, which represents the first stage of the preamplifier 104. The transistor 127 forms the second stage of the preamplifier. The source or cathode connection of the field effect transistor 124 is biased by resistor 130 and drain terminal or anode terminal 132 is grounded. The output signal of the cathode terminal 134 of the field effect transistor 124 is via a bias voltage and Filter circuit including capacitor 136 and resistors 138 and 140, coupled to the base of the transistor 127, which is biased by means of the resistor 142. At the output, filtering is carried out by means of the capacitor 144.

The data pulses pending on line 110

are the control terminal of a field effect transistor 152 via a distortion filter capacitor 146 and a bias circuit made up of resistors 148 and 150, the source terminal

S or Kaihodenanschluss of the field effect transistor 152 is biased through the resistor 154 and the Anode connection is grounded. The output of the field effect transistor 152 is filtered in a filter circuit, the capacitor 156 and the resistors

ίο contains 158 and 160 and is then attached to the base of the Transistor 162 coupled, which the / next stage of the data pulse pre-amplifier 106. A resistor 164 is used to bias the collector of transistor 162 while the emitter is over

• 5 resistor 166 is grounded. A filter circuit with the resistor 166 and the capacitor 172 causes an additional filtering of the output signal c of transistor 162, while another fi-tcr circuit with resistor 174 and capacitor 176 an additional filtering of the output of the transistor 127 of the Taklimpuls preamplifier.

The amplified clock pulses are transmitted via a line 178 two inverters 180 and 182 fed to

* 5 the forehead and the back of the clock pulse c sharper train before a coupling to the pulse delay circuit 70 takes place. In a corresponding manner, the amplified data pulses are by means of a line 184 is fed to the imerters 186 and 188, before they are passed to hold circuit 72.

Sharp clock pulses are emitted over line 190

introduced into the pulse delay circuit 70, the contains three monostable multivibrators 192, 193 and 194 which have the waveform shown in Fig. 3b generate which via line 196 to shift register 78 and via line 198 to the thirty-two digit Counter 82 arrives. The output of the multivibrator 194 is enabled via a line 200 the resetting of the holding circle 72, which in the present embodiment is one half of a dualcn Flip-flop 202 contains the other half of which is part of the counting. 82 forms.

The sharp data pulses are generated after passing through inverters 186 and 188 of the flip-flop

«5 circuit 202 supplied together with the component 206, which is a four digit counter, produces the desired count. NAND gate switches 208 and 210 are connected so that the gate switch 210 generates an output pulse on the line 212 which

for example, lights up an indicator light when there is an incorrect count. the Counter is reset upon completion of a correct count on lines 214 and 216, wherein the reset signal is from a counter or from

can be derived from another device.

After passing through the hold circuit, the data pulses fed via line 220 to shift register 78, with a waveform on line 220 can be found in accordance with Fig. 3f and over

line 222 is provided with a normalized five-volt bias voltage to the individual flip-flops or flip-flops 224, 226, 228, 230, 232, 234, 134 and 238 of the shift register 78.
The content of the shift register 78 can be via a

Line 240 are transmitted in series to an arithmetic unit or else, as indicated by arrows in FIG. 6 indicated, parallel to a code comparison - of a known type, in order to

the present code with a predetermined Compare code, for example to operate a turnstile or a lock. It is also possible to connect the parallel outputs to a number of normal mechanical switches in order to do this to control any evaluation device or utility device.

The voltages for the preamplifiers and the logical signal voltages are taken from a common with 250 designated voltage source derived. A transformer 252 is on AC voltage and its output is rectified via a full-wave rectifier 254. Resistances 256, 258 and 260 as well as capacitors 262 and 264 cause harmonic frequency filtering before the voltage is fed to a regulator 266. An additional filtering is done by means of the capacitors Reached 268 and 270. The standardized components mentioned above are all commercially available without difficulty available and their properties are described in manuals.

In Fig. 7 is for explaining the circuit component 74 according to * Fig. 2 is generally designated as 280 logic circuit shown, which the clock-wise storage of data in a shift register, for example the shift register 78 at a first clock speed and then read out the shift register with a second, different clock speed for storage into another shift register or into an arithmetic logic unit, such as arithmetic unit 80.

The clock pulses 1 and 2, which each have a different repetition frequency, are into a first NAND gate 284 or a second NAND gate gate 282 entered. The outputs of the gate switching elements 284 and 282 are the

ίο F. inputs of a third NAND gate switching element 286 supplied, the output of which is used to switch from the first to the second clock speed as soon as a control signal arrives, which the other input of the NAND gate gate 282 after inversion in Inverter 290 and the other input of the NAND gate gate 284 is supplied. The clock pulses 1 according to FIG. 7 can have the clock speed of the clock pulse channel 60 according to FIG. 2, and the clock pulses 2 according to FIG. 7 can have the speed with which the data enters the arithmetic logic unit 80 should be entered.

A number of modification and further training options are available to those skilled in the art described system. For example, by adding additional hold circuits and shift registers multiple data tracks can be scanned at the same time.

For this purpose 3 sheets of drawings

Claims (5)

• ". Claims: 1. Scanning device for both clock information as well as recording media containing data information, with one of these Information scanning scanning head arrangement, further comprising a buffer in which the scanned data information is stored in the rhythm of the scanned clock information and with a separate one for emptying the buffer after a further storage with different speeds compared to the storage speed serving clock signal source, which is connected to the buffer memory via a switchover of Filling to emptying or from emptying to filling of the intermediate storage causing switching device is connected, characterized that for scanning the clock and the data information of the by hand by the scanning device feed-through recording medium (30) is provided in a manner known per se, each with separate scanning heads (62,64) are of which the scanning head (62) serving for clock information scanning is used for actuation the switching device (74,76) with this switching device is connected, which by means of a clock information pick-up head (62) controlled Payer (82) can be triggered when a target count is reached. 2. Apparatus according to claim 1, characterized in that the buffer (78) of a shift register is formed. 3. Apparatus according to claim 2, characterized in that the further memory part of a digital arithmetic unit (80) is. 4. Apparatus according to claim 2 or 3, characterized in that the data information scanning head (64) is followed by a hold circuit (72) which is switched on by data pulses and of delayed clock pulses in each case one downstream of the clock information scanning head (62) Delay circuit (70) is switched off, the latter via the switching device (74, 76) also supplies the control pulses for filling the shift register (78). 5. Apparatus according to claim 3 or 4 and / or claim 2, characterized in that the switching means (74, 76) one between the clock information scanning head (62) and the other Clock signal source (80) on the one hand and the shift register control input on the other hand connected, switch (74) controlled by the counter (82) and one between the data information scanning head (64) on the one hand and the shift register data input on the other hand located switch (76) and that of the the last-mentioned switch provides a return feed line to the input of the shift register leads, via which if the further memory (80) a data cycle can be generated in a waiting state.