DE2128934B2 - Semiconductor device and method for its manufacture - Google Patents

Description

The invention relates to a semiconductor arrangement according to the preamble of claim 1.

The invention further relates to a method for producing such a semiconductor arrangement.

A semiconductor device of the type mentioned is known from FR-PS 15 52 459

Further semiconductor arrangements with two or more transistors isolated from one another are z. B. from "Philips Technische Rundschau" 27 (1966) 5/6, 142-149 known. The integrated Circuits contain several isolated NPN transistors, which are of the transverse or vertical type, this means that - viewed from the semiconductor surface - the emitter, base and collector zones lie one below the other. The N-conducting collectors These transistors are formed by parts of an epitaxial layer that is on top of a P-type Substrate is attached. The mutual isolation of the transistors is obtained by the fact that the N-conductive end epitaxial layer with a system of diffused P-conductive insulating zones, which together form a lattice form and develop from the semiconductor surface to the Substrate area extend into a number of separate N-conducting parts or islands is divided into this Construction works in the semiconductor body, from one to the other going to the other transistor, two PN junctions happened, which are two opposing series connections Form diodes, whereby the mutual electrical isolation of the transistors at least for voltages, which fall below the breakdown voltage of the diodes mentioned is secured

ίο With these known integrated circuits a substantial part of the available semiconductor surface from the deep and thus also wide isolation zones claimed, whereby the size of the semiconductor elements available for the circuit elements themselves surface, namely the total surface of the isolated islands, is limited

In "Electronics" (International Edition) 41 (1968) 22, Pages 6E and 8E describe a transistor for use in integrated circuits that is much less Takes up space In this self-isolating transistor, the collector zone serves., ^ Ie shell-shaped is designed and completely encloses the base zone, at the same time as insulation. The base zone is thereby through a part of the surrounded by the collector zone epitaxial layer formed which layer in this Case d <-n same conductivity type as the substrate A diffused emitter zone is provided in this epitaxial base zone. This is also the case Structure is the mutual electrical insulation of the Circuit elements secured because - by one Transistor going to the other - at least two PN junctions are passed.

The transistor structure described last is the thickness of the base zone below the emitter, among other things. from the thickness of the grown epitaxial layer addicted. Since the thickness of the bast has electrical properties of a transistor, such as the current gain factor, in Affected to a considerable extent, the epitaxial layer must be carefully and with one over the whole Semiconductor wafer of uniform thickness are attached.

Furthermore, it can occur in various circuits, especially in logic circuits, that in operation the base-collector transition is little at least temporarily takes effect in the forward direction. This can cause an undesirable transistor effect in the two transistor structures described, because the PN junction in both structures between the collector zone and the substrate because of the required isolation in the reverse direction is biased, whereby the substrate as a collector for injected from the base zone into the collector zone Charge carriers can act. In this way, large leak currents can flow to the substrate.

Next is an essential part of the two types of integrated formwork described available surface of the semiconductor body for the electrical connection between the different The improvement of the circuit elements needed Manufacturing techniques bring an increase in number Circuit elements per integrated circuit and thus increases the complexity of the circuit, As a result, the metallization, with the help of which the electrical connections between the Elements are produced, a constantly increasing part of the surface takes up.

To simplify the wiring pattern required and to reduce the size of each circuit element

ment required semiconductor surface has already been proposed, for. B. transistors whose collectors carry the same potential in the circuit to be attached in the same isolated part or in the same isolated island of the semiconductor body, so that these transistors actually have a common collector zone. In many cases, and especially in the case of logic circuits, which are usually built up from a number of the same gate circuits, a compromise is inevitable, in which the transistors in question must be distributed over a number of isolated islands that each form a common collector zone, in general each gate circuit has such an island, because otherwise long conductor tracks are required for the connections with the other isolated circuit elements. Since crossing connections are avoided, the complexity

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required surface in the latter case.

From "IBM Techn. Disci. Bull. «11 (1969) 11, 1439 it is known to divide an epitaxial layer by separation zones in islands and the base zone one in one Such an island arranged transistor via a special diffusion zone with a surrounding the island To connect separation zone.

From FR-PS 14 25 149 it is known in the production of individual transistors in addition to individual Transistors at the same time test structures to control the manufacturing process in a semiconductor body in which the substrate has a lower resistivity than that applied to it having epitaxial layer of the same conductivity type.

The invention is based on the object of the semiconductor arrangement according to the preamble of the claim 1 to design so that there is a transistor structure that is self-isolating and in which the Above-mentioned dependence of the thickness of the base zone on the thickness of the epitaxial layer largely is avoided, and that mutually insulated transistors can be realized, in which the danger a parasitic transistor effect is significantly reduced isL

The invention is based u. '.. the knowledge that this can be achieved in that instead of the collector zone, the base zone of the transistor at the same time is used as an isolation zone.

The stated object is achieved according to the invention by what is stated in the characterizing part of claim 1 Features solved.

Further developments of the invention emerge from the subclaims.

The first transistor can be a field effect transistor, the first zone z. B. is designed ring-shaped and forms a first gate electrode, in which case the third zone then also serves as a second gate electrode the first zone may be a zone which locally overlaps the intermediate part of the second zone, whereby a connection between the first and third zones is obtained and these two zones together form the gate electrode. In both cases, the second zone contains the source and drain zones and the intermediate canal area.

Preferably, the second transistor is a transverse bipolar transistor, the first zone being this The transistor in the semiconductor body is completely surrounded by the second zone Base zone of the transistor. Preferably, the smaller of the first and the third zone is used as the emitter and

the larger one used as a collector. In this case it is the first zone is the emitter zone and the third zone is the collector zone of the bipolar transistor.

lnsbesonders is the first Transiistor a transverse bipolar transistor, wherein the first zone is surrounded in the semiconductor body from the intermediate portion of the second zone Also in this structure, the first and the third zone, preferably, the emitter or collector region of the Transsistors.

In such a semiconductor arrangement, the collector zone of the first transistor does not adjoin a single one Place at the third zone of the second transistor, which zone serves as a substrate for the first transistor. Charge carriers that are injected from the base zone into the collector zone can therefore not be more than Leakage currents flow off to the substrate. On the other hand, however, compared to the one described hpltanntpn be a somewhat isolating transistor larger space required. Compared to the described non-self-isolating transistors however, a considerable saving of space is achieved, mainly because no separate Isolation zones, which are due to the fact that due to the orientation of the different diffusion masks to be taken into account Tolerances must be located at a relatively large distance from this base zone.

It has already been noted that in the case of the known integrated circuits for the mutual isolation of the circuit elements two PN junctions can be used, which form an opposing series circuit. In the semiconductor device according to Invention is only a single isolating PN junction between the first and the second transistor present, which is biased in the reverse direction during operation.

The substrate of the semiconductor body can be used as a connection, for. B. as a feed connection, the arrangement is used thereby simplifying the metallization pattern in many cases. The transistors with do not need a common collector connection together in one island or in several islands to be accommodated, but they are, because the substrate now forms the common collector zone, less location-bound. They can be arranged in this way without requiring a larger surface that integrated circuits with a simple topology with the help of a metallization pattern relatively short conductor tracks can be obtained. When designing the »layout« you can usually can be assumed from the metallization. Once the metallization pattern has been designed. the circuit elements can be arranged according to this pattern. This is in contrast to the previous one usual design process in which first the position of the circuit elements is determined and then one of these Layer adapted metallization pattern is designed.

It is also particularly useful when used in a logic circuit, among others. advantageous that the base KoI lector transition consists of two parts The first part of this transition is between the intermediate one Part of the base zone and the collector zone. This part especially contributes to the transistor effect the structure and collects in the operating state the injected from the emitter zone into the base zone Charge carrier. The second part extends between the bowl-shaped insulating area of the base zone and the collector zone. This second part forms one

Diode parallel to the first part, which forms the actual base-collector junction of the transistor is switched and which prevents the transistor from being largely saturated, thereby reducing the switching speed is enlarged. This transistor remains because of the relatively large length of the PN transfer between the second and the third zone, whereby the base-collector capacitance is proportionate can be large for applications in which the switching speed is subject to particularly strict requirements are less suitable.

Furthermore, the thickness of the base zone below the emitter zone is equal to the difference in the penetration depth two surface zones and independent of the thickness of any epitaxial layer.

The third zone of the second transistor can, for. B. be an epitaxial layer on a substrate of the opposite conduction type is attached. In the development according to claim 5 is on one Substrate of the first conductivity type applied an epitaxial layer of the same conductivity type.

The specific resistance of the epitaxial layer can be applied to the collector zones in the usual way requirements are adjusted, while advantageously a low-resistance substrate is used whose specific resistance is lower than that of the epitaxial layer. The semiconductor body can then be contacted in a simple manner on the substrate side so that it can be connected to a suitable potential can be angled.

The aforementioned epitaxial layer may be a composite layer consisting of two or more epitaxial layers of the first conductivity type with the same or with a different specific Resistance is built up.

The present invention is of particular importance for integrated circuits which, in addition to the already mentioned transistors and other isolated circuit elements, such as diodes, further transistors, Complementary type transistors, field effect transistors, capacitors and / or resistors included.

The shell-shaped insulating region of the further circuit element can only serve as insulation or form part of the circuit element itself and z. B. the base zone of a second similar transistor, a of the zones of a diode or the collector zone of a complementary transistor.

In the further development according to claim 8, without metallization, electrical Connections are made, which also results in a considerable saving of space

Furthermore, the shell-shaped insulating area of the second zone can be used for contacting the second Zone can be used, which also saves space.

The development according to claim 11 ensures that the thickness of the intermediate part below the first zone and at the edge of the intermediate part bordering the surface is practically the same, whereby the electrical properties of the transistor can be favorably influenced, while the intermediate part of the second zone and first zone can be attached through the same window, so that the occupied space is smaller and be ^; During manufacture, the processes for applying a photoresist pattern and, if the intermediate part is doped in a non-oxidizing environment, an etching treatment can also be omitted.

The invention also relates to a method for producing the novel semiconductor device described.

*> The activators can e.g. B. be attached by diffusion or by incorporation of ions by ion bombardment. In the latter case, the activators can be applied in the first surface area after the epitaxial layer has grown. When using ion bombardment, the epitaxial layer can even be completely omitted and a homogeneously doped crystal can be assumed. Preferably, however, an epitaxial layer is used. The substrate can then be selected to have a low resistance, as a result of which the electrical connection of the substrate is simplified.

The further development of the method according to claim 15 has the advantage that the concentration of the activators of the second conductivity type in the first ν surface area needs to be selected to be less high in order to obtain a zone of the second conductivity type at the relevant point. The lower specific resistance can then easily be used for the remaining part of the substrate.
The development according to claim 17 can advantageously be used. In the case of diffusion in a non-oxidizing medium, the two openings can be identical. If during the diffusion of the intermediate part of the second zone μ oxidation occurs, the first window can simply be reopened by etching without using an etching mask to form the second window, even if the original masking layer consists of oxide. This simplifies manufacture while also obtaining an attractive structure in which the thickness of the intermediate part below the first zone and along the surface edge is practically the same.

Some embodiments of the invention are illustrated in the drawings and will be discussed below described in more detail. It shows

F i g. 1 schematically shows a plan view of part of a first embodiment of the semiconductor arrangement,

F i g. 2 schematically shows a cross section along the line «5 U-II of FIG. 1,

F i g. 3 a simple electrical equivalent circuit diagram of the self-isolating transistor according to FIG. 1,

F i g. 4 schematically shows a plan view of another embodiment of a self-isolating transistor; in the arrangement according to FIGS. 1 and 2 is applied.

Fig.5 and 6 are schematic cross-sections along the Lines V-V and VI-VI of FIG. 4,

7 schematically shows a cross section through a Part of a further development of a semiconductor arrangement according to FIG. 1,

F i g. 8 is a circuit diagram corresponding to part of the embodiment of FIG. 7 corresponds,

F i g. 9 a circuit diagram of a gate circuit,
10 schematically shows a plan view of this gate circuit, which is designed as an integrated circuit

11, 12 and 13 are schematic cross-sections along their length the lines XI-XI, XII-XII and XIH-XIII of FIG. 10, and

14 is a circuit diagram showing a self-isolating transistor.

A first embodiment is an integrated one

Circuit, part of which is shown in FIGS. 1 and 2 is shown. This semiconductor arrangement contains a semiconductor body 1 in which the semiconductor zones of at least one first transistor Ti and one second transistor T ₂ extend, which are insulated from one another with the aid of an insulation 2. The semiconductor body 1 has a practically flat surface 3 and the transistors Ti and T ₂ each have at least one group of three successive semiconductor zones of alternating conductivity type adjoining the surface 3, namely zones 4, 5 and 6 or 7, 8 and 9 Of the two groups of three zones, the second zone 5 or 8 extends - viewed from the surface - to below the first zone 4 or 7 and the third zone 6 or 9 to below the second zone 5 or 8 Furthermore, the corresponding zones of the two groups, that is to say zones 4 and 7, 5 and 8 or 6 and 9, have the same conductivity type.

between the first zone 4 and the third zone 6, part 10 has a shell-shaped area 2 connected to this part, whereby the second zone 10, 2 completely surrounds the third zone 6 in the semiconductor body and forms the insulating zone that is connected to the third zone 9 of the The transistor Ti forms an insulating PN junction 11 surrounding the transistor Ti.

The transistor Ti is a self-isolating transistor with a semiconductor body, being attached to one surface this body borders an area of the first conductivity type, which area three consecutive to the Contains surface bordering zones of alternating conductivity type, furthermore the activator concentration in the middle of these three zones is larger than in a part of the underlying zone bordering the middle zone outer zone (hereinafter referred to as third zone), the middle zone of the second conductivity type and apart from the part lying between the two outer zones, one connected to this part contains second cup-shaped region, wherein the third zone in the semiconductor body from the central zone is surrounded and the middle zone with the mentioned area of the first line type a transistor surrounding insulating PN junction forms. The isolation of the transistor is done with the help of the middle one Zone, in the present example the base zone 10, 2 obtained. This in contrast to the known self-isolating transistor in which the collector zone also serves as an isolating zone. This results, inter alia. the Advantage that the self-isolating transistor according to the invention in the collector region of a transistor from same type can be attached. In other words: the substrate can be used as a common collector (or used as a common emitter) of a number of transistors of a certain type are, moreover, simply isolated transistors of the same type, in which corresponding zones the have the same line type, can be used.

The second transistor T ₂ is a transversal bipolar transistor in which the first zone 7 in the semiconductor body is completely surrounded by the second zone 8 Zones 8 and 9 form the base and collector zones, respectively.

In the present exemplary embodiment, the first transistor Ti is also a bipolar transistor. The zones 4; : 10, 2; 6 the emitter or collector zone, the base zone or the collector or emitter zone. The transistor Ti can, however, also be a field effect transistor. Zone 4 can e.g. B. ring-shaped, at least with a closed geometry, and form a gate electrode. The source and the drain can then be formed by the part of the zone 10, 2 lying outside or inside such an annular zone, while the zone 6 acts as a second gate electrode

to can. Also z. B. the zone 10 is thereby distributed in two parts contiguous over a canal area be that the zone 4 overlaps the zone 10 in the lateral direction and is related to the zone 6.

The collector zone 6 of the bipolar transistor Ti is completely surrounded by the base zone 10, 2 and thus does not adjoin the substrate at any point, which, as in the known structures, can act as a collector of a parasitic transistor. This is from special RpHpiiHinn for longitudinal circuits, hot which, as is well known, the base-collector transition may take effect in the forward direction and charge carriers can be injected into the collector zone from the base zone. In the presence of a parasitic transistor, large leakage currents can then flow to the substrate. It is Obviously, this problem in a transistor corresponding to the transistor Ti described is completely eliminated.

It is also important that the transistor Ti is large takes up less space than a conventionally mounted transistor in an isolated island. This saving of space is due to the fact that the active part 10 of the base zone at the insulating zone 11 is applied. With the usual structures, on the other hand, the base zone and the insulation zone must be somewhat Distance from each other, which distance also because of the tolerances to be taken into account in Connection with the mutual orientation of the different diffusion masks and the for example the orientation occurring deviations must be relatively large.

In contrast to the known semiconductor arrangements with each other through PN junctions Isolated circuit elements, the semiconductor arrangement according to the invention does not have any opposing directions Series connection of two diodes, but only a single isolating diode 11. The PN junction U must be biased during operation in the reverse direction, which in practice almost always the case by itself is, and with certainty if the collector zone 9 is used as a feed connection.

By using the collector zone 9 as a feed connection, a simpler one can in many cases Metallization patterns are used because this connection is across the substrate to virtually everyone desired location on the semiconductor surface 3 is available and via short conductor tracks with the different Schahungselemente can be connected.

In addition, since the transistors with a common collector, such as the transistor T ₂ , are no longer bound to an isolated island, as in the usual structure, and therefore take up less space and are less fixed, while the isolated transistors also take up less space , when designing the »layout« or the topology of complex integrated circuits, a metallization pattern design can be assumed

the, the location of the circuit elements through this metallization pattern is determined. With the usual techniques with consideration for one As complete as possible utilization of the available semiconductor surface rather first the position of the s Circuit elements determined, while then a metallization pattern adapted to the position of the circuit elements is designed.

The base-collector junction of the transistor 7Ϊ consists of two parts 12 and 13. The first part 12 is located between the intermediate part 10 the base zone 10.2 and the collector zone 6. This part contributes in particular to the transistor effect and collects those from the emitter zone 4 in the operating state charge carriers injected into the base zone. The second part 13 is located between the cup-shaped insulating region 10 and the collector zone 6 and forms a diode D shown in FIG the actual active base-collector transition 12 is cut in parallel. The diode D prevents the Transistor ""], is largely saturated, reducing the Influence the switching speed of the transistor Ti favorably will.

The thickness of the base zone in the active part of the self-isolating transistor Ti, i.e. below the Emitter zone 4 is formed by the difference in the depth of penetration from the surface 3 of the zones 10 and 4 determined.

The third zone of the second transistor, in the present exemplary embodiment the collector zone 9 of the transistor T2, is a substrate 9a of the first conductivity type, on which an epitaxial layer 96 of the same conductivity type is applied. The shell-shaped region 2 of the transistor Ti has a surface zone 2a of the second conductivity type, which surrounds a part 6 of the epitaxial layer 9b on the semiconductor surface 3 and extends from the surface 3 to a region 26 of the second conductivity type, which at the interface between of the epitaxial layer 9b and the substrate 9a. The surface zone 2a forms the protruding wall of the bowl-shaped insulating region 2 and adjoins the base of the bowl formed by the buried region 2b on all sides. The part 6 of the epitaxial layer lying within this shell is the collector zone of the transistor T \.

The specific resistance of the epitaxial layer 9b can be adapted in the usual way to the requirements to be placed on the collector zones and the Koliekior-base junctions. The substrate 9a is preferably of low resistance in connection with the contacting already described on the underside, with a low series resistance being desired. Insofar as the voltage applied to the substrate 9a has to be fed to one of the other circuit elements via a conductor track, this conductor track can be connected to the substrate at a location suitably selected with regard to a simple metallization pattern via an opening in the insulating layer and a contact zone 15. These zones 14 and 15 can, for. B. be attached at the same time with the emitter zones 4 and 7. The collector zone of the transistor Ti has a buried part 16 to reduce the collector series resistance.

The different semiconductor zones can incidentally in the usual way via openings in one on the Semiconductor surface 3 lying insulating layer 17 with conductor tracks by contacting and / or through Interconnection with other circuit elements of the arrangement. These conductor tracks and the openings mentioned are shown in FIGS. 1 and 2 are not shown for the sake of clarity.

Of course, other geometries can be used for the transistors. Thus, FIGS. 4-6 show another embodiment of the transistor T 1, corresponding parts having the same reference numerals as in FIGS. 1 and 2 are designated. In this embodiment, the contour 20 of the emitter zone 4 on the surface 3 follows the contour 21 of the intermediate part 10 of the base zone 10, 2 at all points at practically the same distance. The contours 20 and 21 are the lines of intersection of the PN junction 22 between the emitter zone 4 and the intermediate part 10 or of the PN junction 12 between the intermediate part 10 and the collector zone 6 with the semiconductor surface 3 20 and 21, but also the PN junctions 12 and 22 themselves over practically their entire surface almost parallel to one another. Accordingly, the thickness of the intermediate part 10 at the edges and below the emitter zone 4 is practically the same, whereby the electrical properties of the transistor are favorably influenced.

In this exemplary embodiment, the bowl-shaped insulating region 2 of the base zone 10, 2 is for the Contacting the base zone used. On the semiconductor surface 3 there is an insulating layer 23, in which has an opening 24 attached. A conductor track 25 extends over the insulating layer 23 and through the opening 24 up to the semiconductor surface 3. In the Opening 24, the conductor track 25 forms a conductive transition with the shell-shaped insulating one Area 2. Furthermore, the opening 24 is attached in this case in such a way that the conductor track 25 also with the Collector zone 6 forms a Schottky junction. It is known that such a Schottky diode is enlarged between the base and the collector the switching speed of the transistor, noting that a Schottky diode is still more effective in this respect because of its lowest threshold voltage the aforementioned PN diode 13 is.

The fact that the base contact can be attached to the cup-shaped part 2 results i.a. the advantage that the active part of the base zone, i.e. the intermediate part 10, and the emitter zone 4 can be applied via the same opening in a masking layer, this opening further can also be used for the emitter contact. In addition to the aforementioned improvement in the electrical Properties of the transistor resulting therefrom also simplify manufacture So the processes for applying a photoresist pattern and, if the doping in one non-oxidizing environment takes place, an etching treatment is also saved

Insofar as the intermediate part 10 lies within the insulating region 2, it is on the surface 3 largely surrounded by the collector zone 6, whereby the fact is exploited as far as possible that in in this case, too, due to the uniform base thickness the edge of the transistor is active. It can also be noted that, insofar as the emitter zone 4 and the bowl-shaped area 2 overlap somewhat, this part of the emitter zone mostly practically not

is active because the bowl-shaped area 2 mostly more heavily than the intermediate part 10 is doped. The injection of charge carriers from the emitter zone is mainly take place in the part of the base zone with the lowest doping concentration.

For the sake of completeness, it should be noted that when impurities are diffused through an opening in of a masking layer, the depth of penetration is known to be in a direction transverse to the semiconductor surface is greater than in a direction parallel to this surface This means that even if the base and the emitter zone are attached through the same opening, the base thickness is not exactly uniform The distance between the PN transitions will be close to the surface, i.e. at the edge next to the Emitter zone, mostly a little smaller than below the Be emitter zone.

Another embodiment that is based on the F i g. 7, comprises a substrate 40 covered with a composite epitaxial layer is provided, which is made up of two parts 41 and 42. The emitter zones 44 are located in the semiconductor body, the base zone 45, 46 and the collector zone 47 of a self-insulating first transistor, which is through a insulating PN junction 48 from a second transistor of the same type with an emitter zone 49, a base zone 50 and a collector zone 40-43. In addition to these two transistors, there is also Another isolated circuit element is present, namely a complementary transistor with a Emitter zone 51, a base zone 52 and a collector zone 53. The collector zone 53 is cup-shaped and forms an insulating PN junction 48 with collector zone 40-43. The bowl-shaped zones 46 and 53 of the first transistor and the complementary transistor are related to each other, whereby without metallization, an electrical connection of the in FIG. 8 is the type shown

The collector zones 47 and 40-43 are both with a buried portion 54 and 43, respectively, for relief of the collector series resistance. Furthermore, there are 47 in the collector zone and 52 in the base zone Contact zones 55 and 56 applied. The use of a composite epitaxial layer 41, 42 is related to the manufacturing process, as explained in more detail below will.

The invention is of particular importance for logic circuits. As an example of such Circuit is based on the F i g. 9-13 describes a gate circuit. This gate circuit forms the The subject of Dutch patent application No. 70 09 090. The operation of this circuit is for the present invention is not essential, for which reason it is not discussed in detail. Such a gate circuit can, for. B. as a building block for building larger logic circuits, such as Flip-flops, comparators or memories are used.

FIG. 9 shows the electrical circuit diagram, while FIG. 10 shows a topology or a "layout" of this Circuit shows, the different circuit elements in these figures with corresponding Reference numerals are denoted.

The semiconductor arrangement contains a semiconductor body 70 which has a low-resistance substrate 71 that an epitaxial layer 72 of the same conductivity type and with a higher specific Resistance is attached. The substrate 71 and the epitaxial layer 72 together form the common collector zone of the transistors Tu-T ₁₃ , T \ s and 7Ie, which are connected to a reference potential, e.g. B. on earth, can be placed. In the present embodiment with this zone also the positive terminal of the

Supply voltage source connected so that the substrate

carries the most positive potential in the circuit occurs

The input transistors Tn-Tb each have one

Base zone 73 on and an emitter zone 74 on. Input signals can be fed to the transistors Tu, Tb and Tb via metal tracks 76 lying on the insulating layer 75 and connected to the base zones 73 in openings in the insulating layer.

A metal track 17 prevents the three emitter zones 74 with the base zone 78.79 of the isolated transistor Ti «. This base zone has an intermediate part 78, which encloses an emitter zone 80 in the semiconductor body, and a shell-shaped insulating part

79. the one with the common collector zone 71,72 The insulating PN junction 81 surrounding the transistor TU forms the collector zone 82 of the transistor Tu, which is provided with a contact zone 83 is completely separate from the base zone 78, 79 in the semiconductor body surround. The intermediate v. Part 78 of the base zone hangs on the semiconductor surface 84 with the insulating part 79, with the intermediate tube 78 extending in a direction parallel to the surface 84 'up to the vicinity of the insulating part 79 extends and adjoins the part 79 there. As a result, the part 78 located between forms a di-i semiconductor surface 84 bordering approach or extension of the insulating part 79, which extension extends above the collector v.one 82

The insulating part 79 is ring-shaped on the semiconductor surface 84 ', or at least has a closed one Geometry on. This ring can be used to make contact with the base zone 78, 79. At a the insulating layer 75 can be suitably selected above the insulating part 79 with an opening 85 are provided, via which the conductor track 77 is connected to the base zone 78, 79 thanks to this flexibility With regard to the position of the base metal contact, the metallization pattern can usually be simpler and with shorter conductor tracks can be carried out, whereby crossing metal tracks are often easier to avoid can.

As can be seen from the circuit diagram (FIG. 9), the resistor An is connected to the base of the transistor Tu tied together. This fact is used to create a conductor track and the space for the associated Saving contact openings in the insulating layer. The second zone 78, 79 of the transistor Tm has to dei Surface 84 locally from the insulating part 7S outstanding part 86 on, which is to the common « Collector zone 71, 72 adjoins and extends in a direction transverse to the semiconductor surface 89 over a extends smaller distance than the shell-shaped insulating region 79 in the semiconductor body. diesel

& ° excellent part 86 can be used at the same time as the intermediate part 78 are attached. Dei located within the bowl-shaped area 79 intermediate part 78 forms the actual active part of the base zone of transistor Tu, d. H. the part, ir which, in the operating state, the charge transport, which is the actual transistor effect of the structure, takes place at least essentially. The resistance Rw is at least largely determined by the

outstanding from the bowl-shaped area 79 Part 86 formed The insulating region 79 is therefore used not only as insulation for the transistor, but also as a low-resistance connection of the active part of the base zone and as a low-resistance connection between the active part and the resistance

It will be appreciated that several resistors can be connected to the base zone in the same manner, so that for example also the position shown in Fig. 14 circuit frequently used can be easily integrated, said cup-shaped insulating region as a low-impedance connection between the two resistors Rx and Rn and the active base zone of the transistor 7 »is used.

The resistance An continues with the negative Terminal of the supply voltage source connected. For this purpose, the zone 86 has an opening in the Insulating layer 75 connected to a metal layer 87.

The resistor Rit is formed by the zone 88 and is connected via an opening in the insulating layer to a metal track 89, which leads to the emitter zone 80 of the transistor 71 ₄ and the emitter zone 90 of the transistor 7 * i6. The resistor Rn is through the zone 91, which is connected on one side to the zone 88 and on the other side to the base zone 92 of the transistor 71e. The resistor Ru is formed by a zone 93 connected to the base zone 92 by using the metal layer 94, which is in the opening 95 in the insulating layer, which is located next to the emitter zone 90 and the opening 96 opposite, lies on the semiconductor surface, the resistance value of the resistor Ru is more precisely defined via the opening% and the metal track 97 is the resistor Ru with a first of two emitters 98 of the multi-emitter transistor 71s tied together. The two emitter zones 98 are surrounded by a base zone 99 in the semiconductor body. Zones 100 and 101, which form the resistors Rn and / fi3, are connected to this base zone 99. A metal layer 102 on the semiconductor surface is also used in these resistors to improve the definition of the resistance values. A metal track 103, which connects the second emitter 98 of the transistor 71s to the collector zone 82 of the transistor 7m and to the resistor Ru , forms the electrical output of the Gate switching. The resistor Rn is connected via an opening 104 in the insulating layer to a metal layer 105, which is connected to the common collector zone 71, 72 with the aid of a contact zone 106.

The transistors Tn-Ti ₆ are each provided with a buried low-resistance part 107 to reduce the collector series resistance, which low-resistance parts 107 extend on and in the vicinity of the boundary between the substrate 71 and the epitaxial layer 72.

In particular in the case of an integrated circuit of the type described above with a group of transistors with a common zone, the result is Application of the invention significant advantages. In the first place it can be mentioned that a minor one Number of isolated areas than in the usual design are required, whereby a high yield can be expected. Furthermore, it is particularly in the case of a large number of transistors with a common zone saves space considerably, also because then the Topology and metallization can be kept simpler due to the fact that the transistors mentioned are not fixed and not, as usual, in a common isolated island need to be accommodated.

The gate circuit described has a simple metallization pattern. A substantial number of Connections are obtained without metal traces while the circuit elements are further grouped in this way can that - also thanks to the relatively large freedom in terms of the contacting points insulating zones - for the rest of the inner ones

ίο connections short conductor tracks are sufficient.

The semiconductor arrangements described can be localized using the usual techniques Doping of semiconductor material can be produced. For example, the production of the

Semiconductor arrangement according to FIG. 7 described.

It is z. B. from an N-conductive silicon body assumed a specific resistance of about 0.01 Ω cm. In a first surface area. this Substrate 40, which corresponds to the location of the buried part of the Isolation 46 corresponds to acceptors, e.g. B. boron, For example, the body is attached with a masking oxide layer provided in which an opening is made by the usual photo-etching techniques will. Then the body becomes a half during et * a Heated to about 950 ° C in a boron-containing atmosphere for an hour take place for about 4 hours at 1200 ° C in an oxidizing atmosphere. Then in the usual way an N-conductive epitaxial layer 41 with e.g. B. one Thickness from about 6 to ΙΟμίτι and a specific one Resistance of about 03 - 1 Ω cm deposited. In a surface area of this epitaxial layer which corresponds to the long one of the buried parts 43 and 54 are now donors, z. B. arsenic or Antimony, introduced e.g. B. in that for 2 hours to about 1200 ° C in an arsenic-containing atmosphere is heated, after which the body for about 4 hours at about 1200 ° C in an oxidizing atmosphere is held. During this and the following

■ * o Edits also diffuse from the acceptors buried parts doped with boron into the epitaxial layer 41.

The next step is the epitaxial Layer 42 deposited. This layer also consists of

■ »5 N conductive material and has a thickness of about 6 μπι, while they also have a specific Has a resistance of about 03-1 Ω cm in one Surface area with a closed configuration corresponding to the location of the protruding walls of the insulating shell-shaped part 46 corresponds and that is one or more parts of the epitaxial Layer 41, 42 surrounding layers, which are above the first boron-doped surface area, are then turned off the upper surface of the facing away from the substrate 40 epitaxial layer 41, 42 introduced acceptors z. B. by diffusion of boron for about half an hour to about 1100 ° C and subsequent heating in an oxidizing atmosphere for about 3 hours at about 1200 ° C.

The intermediate part 45 and the parts 50 and 51 can by diffusion of boron during about one half an hour to about 950 ° C and subsequent heating for about half an hour to about Maintained 1180 ° C in an oxidizing atmosphere

κ become. The sheet resistance of these zones is e.g. about 150Ω / D. The diffusion of the takes place intermediate part 45 in a surface area which is at least the inner edge of the through the

Surface zone of the insulating tube-shaped area partially obtained prior to processing covered

Then, the emitter regions 44 and 49 and the contact zones 55 and 56 are mounted by the diffusion of phosphorus, for example, for about 20 minutes at about 1000 ⁰ C, and by a subsequent heating of about 20 minutes to about 105O ⁰ C. The Flächenwiderst & nd this zone z is . B. about 5 Ω / D.

The diffusion of acceptors from the buried part doped with boron into the epitaxial layer was stopped already mentioned During the heat treatments described, this diffusion continues in such a way Measures continued that in combination with the diffusion in the opposite direction from the mentioned surface zone on the upper surface of the epitaxial layer the closed cup-shaped P-conductive zone 46 is obtained. It should be noted that the diffusion from the buried te; ' at the location of the buried zone 54 slowly goes ahead sicfi, which refers to the existing there Donor concentration is due to the overdoping difficult and also a diffusion generates counteracting electric field by acceptors. At the point of zone 54, the Expansion of the buried part of the shell shape! The region 46 in the epitaxial zone is therefore not small be. At the edge of the buried part, around the: Zone 54, this expansion will be considerable, because here the donor concentration is much smaller. In this way it is already through diffusion a part of the protruding wall of the zone 46 is formed from the substrate The projecting wall is largely made up of the manufacturing process using this effect Substrate obtained and supplemented from the top surface during diffusion processing, in which Machining also the intermediate part of the second zone is attached. That way will! a diffusion processing saved. Incidentally, this effect can be increased if necessary that in the part of the buried part covered by the zone 54 activators with a small Diffusion coefficients, such as boron or arsenic, and at the edge of the buried part activators with a large diffusion coefficients, such as aluminum or phosphorus, are introduced. Activators, e.g. B. those with a large diffusion coefficient, in an annular area around the buried zone 54 can be introduced on the surface of the epitaxial layer 41.

In the usual way, openings for contacting the different can be made in the insulating layer Semiconductor zones are attached. In these openings and on the insulating layer, the Metallization patterns are applied for the electrical connection and the electrical connection, e.g. B. in that an aluminum layer is evaporated and then etched according to a pattern.

Finally, the semiconductor body can be mounted in a conventional envelope in the usual way.

The procedure described is only one possible example.

It is i.a. it is also possible for the doping to be incorporated by ion bombardment. In this case it can even a homogeneously doped crystal without an epitaxial layer can be used because the buried zones in the case of ion bombardment, they can be attached over the free upper surface. In connection with the Use of the substrate as a feed connection is, however, preferably of a low-resistance substrate assumed, on which a high-resistance epitaxial layer is applied. The one described above Method used composite epitaxial layer gives the advantage that a greater freedom in With regard to the choice of the doping concentration for the two adjacent buried zones of opposite conductivity types, these buried zones exist Zones can both be placed in the substrate. Then, however, when determining the doping concentrations of the substrate and the two buried zones, the fact must be taken into account that twice overdoping must be achieved with what can bring that especially the concentration in the low-resistance substrate would have to be selected higher than with regard to a low series resistance is desired for the feed connection

The doping of the substrate can also be practical

can be selected independently if the layer adjoining the surface of the substrate is at least at the Place the surface area of the first buried zone a higher resistivity than that This can be done with the help of the remaining part of the substrate can be achieved by outdiffusion, if necessary can be done locally, or z. B. with the help of a high-resistance epitaxial layer, with the latter Case of the substrate crystal and the epitaxial layer together form the actual substrate area of the described level structure.

The arrangement according to Fig.4-6 can be done with a simplified modification of the method already described can be produced. Including the Attachment of the intermediate part 10 of the The production of the base zone proceeds in an analogous manner, whereby the processing for obtaining a low-resistance buried part in the collector zone 6 can be omitted. Even . ¹ Ti connection herewith can be a simple epitaxial

* o Layer 9b can be combined with a sufficiently low-resistance substrate 9a.

The modification of the method relates to the fact that after the attachment of the intermediate part 10, the opening in the masking layer 23, Via which the activators are attached in the part 10, again exposed by etching without masking thereby avoiding the alignment of a photomask, or making this alignment, if at the same time with the emitter zone 4 a contact zone 14 must be attached, less critical in relation to to the desired accuracy. Using a difference in thickness and / or in The composition of the masking layer inside and outside the closed opening is

uncovering the opening by etching without photoresist masking the re-exposed opening automatically aligned with great accuracy with respect to the original opening. The two openings are namely practically identical. This re-exposure is naturally omitted if during and after the formation of the part 10, the opening used for this purpose remains free, which z. B. may be the case if the Diffusion is carried out in a non-oxidizing medium.

The above also applies to the opening for the Emitter metal contact is required. In this case there is the additional advantage that the metal contact automatically up to a small distance from

PN junction is enough, reducing the series resistance of the emitter can be particularly low.

The described semiconductor arrangement according to the invention can except in those with reference to the figures described combinations also in connection with z. B. one or more other self-insulating Transistors, with (a) field effect transistor) with Diodes and / or with capacitors can be used. When combined with one or more others Isolated circuit elements, the shell-shaped Isoüerzonsn to be used for these elements can not only, as described, a part of the relevant circuit element form and z. B. the Form the collector of a complementary transistor, but also serve only as insulation. Further The third zone of the second transistor can also be an epitaxial layer which is formed on a substrate crystal of the opposite type of conduction or attached to an insulating surface.

The protruding wall of the shell-shaped insulating zone can be obtained not only partially but also entirely by diffusion from a buried region provided at the interface between the substrate and the epitaxial layer. The invention can also be used with the integration of logic circuits in other versions such as DTL, ECL and E ² CU. Resistors with a large value, such as the resistor An in FIG. 9, can be designed as buried resistors to a greater or lesser extent in order to save space by locally covering them with a zone of the opposite line type. Furthermore, others can Materials such as germanium or semiconducting A '"B ^V compounds, and for the insulating and / or masking layer, for example, silicon nitride, aluminum oxide or combinations thereof with silicon oxide. For the metallization pattern, besides aluminum, other conductors such as molybdenum or a composite of are used Different layers, such as titanium-platinum-gold layers are suitable The diffused contact zones can be replaced by platinum-silicide contacts, for example Diodes are obtained in that at the same time as the emitter zone one or more additional zones, which for example form cathodes, are attached, the insulating part then acting as an anode between these z Additional zones, the insulating part and a semiconductor device bordering on this part, such as the collector zone or the substrate, can be practically completely avoided.

It should be noted that in the embodiments described, the bowl-shaped insulating region is the completely surrounds the remaining zones of the self-isolating transistor, which is also preferably the case but it is Obviously, under certain circumstances, the bowl-shaped insulating zone can be locally uninterrupted can e.g. B. in order to obtain a connection to the collector zone in the interior of the semiconductor body.

In addition 5 sheets of drawings

Claims (17)

Patent claims: 1. Semiconductor arrangement with a semiconductor body in which the semiconductor zones of at least one first and one second transistor extend, the semiconductor body having a practically flat surface and both the first and the second transistor at least one group of three consecutive to this Surface-bordering semiconductor zones of alternating conductivity type, of which the second zone - viewed from the surface - extends to below the first zone and the third zone extends to below the second zone, corresponding zones of the two groups being of the same conductivity type and the third zone of the first transistor in the semiconductor body is practically completely surrounded by a shell-shaped region which forms an insulating PN junction which at least practically completely surrounds the first transistor, characterized in that the shell-shaped region (2) with the one between the first (4) and the third Z one (6) of the first transistor (Ti) lying part (10) of the second zone (5) and thus forms part of the second zone (5,10,2) of this transistor (TX) , the insulating PN junction through the PN junction (11) located between the shell-shaped area (2) and the third zone (9) of the two-line transistor (T2) is formed. Yo 2. Semiconductor disorder according to claim 1, characterized in that the part (10) of the second zone (5,10,2) lying between the first (4) and the third zone (t>) of the first transistor (Ti) extends in a direction parallel to the upper surface (3) up to the bowl-shaped area (2) and adjoins this area 3. Semiconductor arrangement according to one of the preceding claims, characterized in that the first zone (7) of the second transistor (T2) in the * o semiconductor body (1) is completely surrounded by the second zone (8) of this transistor and that the second transistor is a is a bipolar transistor, the first (7), second (8) and third zone (9) of which form the emitter, base and collector zones, respectively. ⁴ pp 4. Semiconductor arrangement according to one of the preceding claims, characterized in that the between the first (4) and the third (6) of the first transistor (Tl) lying part (10) of the second zone (5,10,2) completely surrounds the first zone (4) and that the first (4), second (5) and third zone (6) of the first transistor, the emitter, the base and the Form the collector zone of a bipolar transistor. 5. Semiconductor arrangement according to one of the preceding claims, characterized in that the third zone (9) of the second transistor (T2) is a substrate (9a) of a first conductivity type, on which an epitaxial layer (9b) of the first conductivity type is applied, wherein the shell-shaped region (2) of the second zone (5,10, 2) of the first transistor (Tl) has a surface zone (2ajaufweiiit, which on the surface (3) of the semiconductor body surrounds part of the epitaxial layer up to one in the semiconductor body the interface between the epitaxial layer (9b) and the substrate (9a) lying region (2b) of the second conductivity type extends and is connected to this region. 6. Semiconductor arrangement according to claim 5, characterized in that the specific resistance of the substrate {& a) is lower than that of the epitaxial layer (9b) 7. Semiconductor arrangement according to one of the preceding claims, characterized in that except the first (44 to 47) and the second transistor (49, 5C and 40 to 43) at least one more Circuit element (51, 52, 53) is present, which also consists of an insulating PN junction (48) between a bowl-shaped area (53) and the third zone (40 to 43) of the second Transistor is surrounded (Fig. 7). 8. Semiconductor arrangement according to claim 7, characterized in that the shell-shaped region (53) the second zone (45, 46) of the first transistor with the cup-shaped region (53) further Circuit element related thereby the first transistor and the further circuit element are electrically connected to each other. 9. Semiconductor arrangement according to one of the preceding claims, characterized in that there is an insulating layer (23) on the surface (3) of the semiconductor body (1), the second zone (5, 10, 2) of the first transistor (TX) having a conductive one Contact (25) is provided, which is connected in an opening (24) in the insulating layer (23) to the shell-shaped area (2) of the second zone (FIG. 4). 10. Semiconductor arrangement according to one of the preceding claims, characterized in that the first zone (4) of the first transistor (TX) in the semiconductor body is completely surrounded by the second zone (5) 11. Semiconductor arrangement according to claims 9 and 10, characterized in that the contour (20) of the first zone (4) of the first transistor (TX) on the surface of the contour of the between the first zone (4) and the third zone / 6 ) lying part (10) of the second zone (5,10,2), at least insofar as this contour lies outside the bowl-shaped insulating area (2) of the second zone, follows everywhere at practically the same distance 12. Semiconductor arrangement according to one or more of the preceding claims, characterized in that between the first zone (4) and the third zone (6) of the first transistor lying part (10) of the second zone (5, 10, 2), insofar as it lies within the shell-shaped insulating area (2), on the surface largely to the third zone (6) of the first transistor and is surrounded by this zone (Fig. 5). 13. Semiconductor arrangement according to one or more of the preceding claims, characterized in that the second zone (78, 79) of the first transistor (TXV) on the surface (84) has at least one part (86) protruding locally from the bowl-shaped region (79) which adjoins the third zone (71, 72) of the second transistor (T 16), extends in a direction transverse to the surface (84) over a smaller distance than the shell-shaped insulating region (79) in the semiconductor body and with a conductive contact (87) is provided (Figs. 12-14). 14. A method for producing a semiconductor arrangement according to any one of the preceding claims, characterized in that on a surface of a semiconductor substrate of the first conductivity type Activators of the second conductivity type are introduced locally in a first surface area, that on the surface mentioned an epitaxial layer of the first conductivity type is formed and of the facing away from the substrate upper fly of the epitäktischen layer ago a surface zone of the second conductivity type is introduced, which on the upper surface surrounds a portion of the epitaxial layer that covers the first surface area and that in the heat treatments carried out during manufacture by diffusion of activators of the second conductivity type in the epitaxial Layer from the top surface and from the first surface includes the cup-shaped region of the second region of the first transistor is formed. 15. The method according to claim 14, characterized in that a substrate is used from which the layer adjoining the surface, at least at the location of the first surface area, has one has a higher specific resistance than the rest of the substrate. 16. The method according to claim 14 or la, characterized in that of the upper surface of the epitaxial layer ago after the application of the activators to form the surface zone from second conductivity type in a surface area that has at least the inner edge of the mentioned Surface zone partially covered, the part lying between the first and the third zone second zone of the first transistor is attached. 17. The method according to claim 16, characterized in that between the first and the third Zone lying part of the second zone over an opening in one on the free surface applied masking layer is applied, after which a second opening, the boundary of which practically coincides with the first opening, activators to form the first zone of the first transistor are introduced into the semiconductor body.