DE2120410A1 - Data processing system with a working memory subdivided into partial memories - Google Patents

Description

SIEMENS AKIDIEKGESELLSOHAEiD Munich, the? 6th APR. 197 1 Berlin and Munich Witteisbacherplatz "2

VPA71 / 2Q46.

Data processing system with a working memory divided into partial memories

The invention relates to a data processing system in which the main memory is divided into partial memories of several Memory cells is divided and the partial memory can be controlled simultaneously and in which the commands and Data of a program can be stored in different partial memories.

It is known to divide main memories into different partial memories with several memory cells. The reason for this The division consists in being able to use the various partial memories at the same time. The individual partial storage are then controlled with the help of part of the address.

For example, if a program consists only of instructions that have no operands, i.e. no data from the main memory take, the successive commands are in different sub-memories. That means that in such a Program at the same time as reading one command - or slightly shifted against it - the next command and if there are more than one Partial storage of further commands can be read. This method is particularly advantageous for main memories, whose cycle time is greater than the access time. Because then the recovery or re-writing time does not appear as a processor waiting time in appearance.

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But if there is a program whose commands process operands from the main memory, this often occurs that the respective operand is in the same partial memory as the instruction to be read. In such a The advantage of the simultaneous use of different partial memories for a program with commands and Lost data ..

The object of the invention is therefore to subdivide the main memory so that even with programs with commands and | Data that are part of the memory can be controlled at the same time or slightly shifted from one another. This task is achieved in that the partial memories are arranged in a matrix of ή columns and m rows, that the rows the partial storage unit, the columns of the partial memory and the Memory cells within the partial memory are addressable and that the commands and the data of a program in the Main memories are stored in such a way that the commands are in different rows or columns of the partial memory than the data.

The address for such a subdivided working memory can provide a part for the line selection, a part 'for the column selection and a part for the selection of the memory cell within the activated partial memory.

The invention is to be explained further on the basis of an exemplary embodiment. Show it:

1 shows the structure of the main memory as a partial memory matrix,

FIG. 2 shows the address for controlling the main memory of FIG. 1.

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In Pig. 1, the partial memories are denoted by TS. They are arranged in a matrix of η SpaltmS and m rows Z, η and m are whole numbers. In the exemplary embodiment, η = 4 and m = 2. Each partial memory contains memory cells SZ.

The address for controlling the main memory of FIG. 1 is in Pig. 2 shown. The lowest value address parts SA, in the embodiment 2 bit, are used for column selection, the highly finished address parts ZA, in the exemplary embodiment 1 bit, for line selection. With the help of the between ZA and SA k bit, the memory cell SZ becomes one of the partial memories TS selected.

Usually programs consist of an instruction part and a data part. In such a palle, the commands are stored in a different line of the partial memory than the data. For example, the commands are written into the first line Z1 of the partial memory and the data into the second line Z2 of the partial memory. The first command of the program can then be written into the first memory cell of the partial memory located at the intersection between the first column and the first row, the second command into the first memory cell of the partial memory located at the second column and the first row, etc. and when all the first memory cells of the partial memories of row Z1 have been placed, the following commands are stored in the second cells of the partial _{memories of row Z1, starting again at the partial memory located at the intersection between St 1 and Z1.} In this way, it is possible to read out several commands, at least four in the exemplary embodiment, at the same time. The data are correspondingly written into and read out in the partial memory of the second line Z2.

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Of course, the commands and data of a program also be stored in the working memory in such a way that the commands in one column and the data in another Column stand.

With such a division of the main memory into Partial memory and with such a division of the commands and the data of a program in the partial memory, it is impossible that the respective operand to be processed of a command to be read are in the same partial memory. There are consecutive commands or data so always in different partial memories of the main memory. This will increase the effective access time of the entire The main memory is considerably smaller than the access time of a partial memory.

2 claims
2 figures

VPA 9/210/1014 - 5th

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Claims (2)

Patent claims Data processing system in which the main memory is subdivided into partial memories made up of several memory cells is and the partial memory can be controlled at the same time and where the commands and data of a program can be stored in different devices, characterized in that the partial memory (TS) are arranged in a matrix of η columns (S) and m rows (Z) that the rows (Z) of the Partial memory (TS), the columns (S) of the partial memory (TS) and the memory cells (SZ) within the partial memory (TS) are addressable and that the commands and the data of a program are stored in the main memory are that the commands are in different rows (Z) or columns (S) of the partial memory (TS) than the data. 2. Data processing system according to claim 1, characterized in that the columns (8) of the partial memory (TS) with part of the address, the lines (Z) with another part of the address and the memory cells (SZ) within a partial memory (TS) can be controlled with the remaining part of the address. VPA 9/210/1014 209845/100? Blank page