EP1079307B1 - Method for operating a memory system as well as memory system - Google Patents

Description

The invention relates to a method for operating a memory system comprising a main memory and associated therewith, structured in address-related lines cache memory in the data can be loaded from the main memory and read out as needed by a processor, wherein during access of the processor to data a certain address in the cache memory, under which certain data from the main memory of a corresponding address are stored, it is checked whether sequential data is stored in the cache memory at the next following address, which in case of absence from the main memory in the context of a prefetch in the cache memory can be invited.

In known memory systems, a plurality of data stored in the main memory are already loaded into a cache memory before being polled by an associated processor executing a corresponding program. A cache memory is a fast buffer memory, from which the required data is available to the processor much faster than from the much slower working main memory. To ensure that even in the vast majority of cases, the data required by the processor in the cache memory are present, the use of prefetch has proven. In the context of a prefetch operation, data which is not yet needed by the processor at the moment, but which is likely to be needed shortly due to processor access in the cache memory, is previously transferred from the main memory into the cache memory. Memory or a corresponding register so that they, if the processor requires this data, there are also available. A cache memory is subdivided into a multiplicity of lines, which are usually also structured in columns, with each memory line being assigned a specific address line. One line of the main memory is written to one line of the cache memory, with the line address specified in the cache memory corresponding to that of the main memory. Each line thus has a certain length over which the data is written. The operation of such a memory system is now such that when a hit in the Cache line N, which contains the data of the address A, is checked simultaneously, whether in the cache line N + 1, the data of the address A + line length are. Thus, a hit in the cache line N always checks whether sequential data are present in the subsequent line which the processor is expected to require shortly. If this is not the case, the data of the address A + line length in a prefetch operation are either loaded into the cache memory or a corresponding associated register.

Basically, the use of prefetch for a cache increases the hit rate that is achieved in the cache memory by the processor. In turn, a high hit rate results in better performance of the system because memory access can be performed on a hit without delay, while a miss results in access to the slower main memory and slows the system down.

The use of prefetch but also disadvantages. On the one hand, data is loaded from the main memory into the cache memory, which may not be needed at all, whereby this danger exists in particular for large line lengths, since in this case a large amount of data is transferred into the cache memory during a prefetching process. Since every data transfer contributes to power consumption, the power loss increases. On the other hand, a conflict arises if a cache cache fails during a prefetch operation, ie if the processor does not find the data there. Then the prefetch process must either be aborted or completed before the required Daren can be loaded. In both cases, additional delays occur which reduce the performance of the system.

The document " Prefetching using a pageable branch history table "IBM TECHNICAL DISCLOSURE BULLETIN ., XP002152936, describes a cache line prefetch using PBHT by dividing a cache line into areas and specifying the subsequent line to be used for each area.

The document " Buffer block prefetching method "IBM TECHNICAL DISCLOSURE BULLETIN , XP002152937, describes a prefetching method for high speed buffer (cache) processors, where prefetching is done using a special bit associated with each block position in the cache.

The document " Confirmed prefetching with confirmation on exit "IBM TECHNICAL DISCLOSURE BULLETIN XP002152938, describes a prefetch implementation, prefetching being allowed only if the previous prefetch attempt was successful.

The invention is therefore based on the problem to provide a method for operating a memory system, which improves the performance of the system and reduces the power consumption when using a prefetch strategy

Particular and preferred aspects of the invention are set forth in the appended independent and dependent claims.

To solve this problem, it is provided according to the invention in a method of the type mentioned in the introduction that a prefetch takes place only when the processor accesses a predetermined line section lying within a line.

In the method according to the invention, therefore, a prefetch process is advantageously only initiated if the processor accesses data which lies within a predetermined line segment within a line. Only in this case, if the check for the presence of the sequential data reveals that they are missing, a prefetch is performed. This is based on the knowledge that the probability that the data of the line following the row being processed sequentially is required by the processor is greater, the further back in line N the hit lies or the processor reads out data. Because then it can be assumed that the processor executing a particular program, the data of the line N reads out further and shortly the sequential data of the subsequent line N + 1, as stored in the main memory, would need. This can be taken into account by the definition of a specific line section, which defines the part of a line that the processor must access in order for there to be any possibility of prefetching. If the processor accesses an address in the line which is outside the predetermined line segment, a prefetch can not (yet) be initiated.

This can increase the performance of the system, since a prefetch operation is initiated only when it is very likely that the data retrieved from main memory will actually be needed. Thus, a prefetch is not necessarily performed each time upon detection of the absence of the sequential data, but only in preferred cases. This reduces the number of prefetch operations performed during a program run, so that the power consumption caused by the loading of data into the cache memory or the register associated with it also drops significantly. Compared to a conventional prefetch strategy, power consumption for data transfer can be reduced by more than 30% with improved system performance. A particularly preferred application of this prefetch strategy is in the field of mobile radiotelephony, in particular when using the storage system in a mobile terminal of the mobile radiotelephony.

For easy definition of the line section, this can be defined according to the invention by means of a predetermined line section address and comprise all addresses of a line which are greater than or equal to the line section address, wherein the Address within the line, which is accessed by the processor is compared with the line section address to determine from this comparison, whether the processor now outside or within the predetermined line section works, so that it can be decided whether a prefetch can be initiated or not. The final placement or selection of the line section address is essentially dependent on the performance parameters of the processor, in particular the processor clock and the data transfer rate from the main memory as well as the program structure of the program, which the processor executes because this is predetermined by whether the processor in Essentially continuously address for line or line by line processing the data, or whether during execution of the program very many interlaced. Basically, the line segment address should be set so that in the majority of cases the prefetch operation is already completed before accessing the data from the processor.

Each line of the cache memory may be divided into a plurality of line areas of particular length, each associated with a separate line area address, the line area address being compared to the line section address. This takes account of the possibility of configuring a cache memory in various forms and essentially relates to the division of each cache line or the entire cache memory into several columns, wherein the columns may be of different lengths depending on the cache configuration , A specific amount of data can be written into each line area, which can be found using the line area address, which is compared within the context of the checking of the "work location" of the processor within the line segment line. In this case, the line segment address may be given in the form of a numerical value, wherein a comparative numerical value is determined on the basis of the address within the line or the line region address where the processor is currently accessing. According to an expedient development of the inventive concept, provision can be made for a plurality of line sections of different lengths to be determined, the line section to be used for determining a prefetch to be executed being selected depending on the program section of a program to be executed by the processor within which the processor is operating at the time of the determination. The line section or the line section address is read during the runtime of a Processor to be processed by the program itself. Thus, according to this embodiment of the invention, a dynamic change of the line section is realized, so that it is possible to define separate line sections for different program parts, which may be differently structured, and to separately define the trigger conditions for a prefetch for each program section. In this way it is possible to react to different program structures. So if you implement the decision to initiate a prefetch process so that it can be configured by software, a dynamic change of this parameter is possible.

In addition to the method, the invention further relates to a data storage system comprising a main memory and a multi-row cache memory in which data read from the main memory is writable and readable by a processor when needed, and a prefetch means for determining; whether to prefetch data from the main memory for transmission to the cache, as well as to prefetch. This memory system is characterized in that in prefetch means at least one of the length of a line of the cache memory related line section address is determined or determinable, by means of which a line section is defined within the line of the cache memory, wherein the means for comparing the Line section address having an address within a line accessed by the processor, and for determining whether the access is within the line section, as well as for performing a prefetch depending on the comparison result.

Each row of the cache memory may be divided into a plurality of row areas each having a separate row area address comparable to the row slot address, this row area address indicating the access location of the processor and correspondingly comparing to the row address address of the prefetch means to determine whether a prefetch would be possible at all.

It has also proven to be useful if a plurality of line section addresses are determined or determinable for determining a plurality of line sections, wherein the line section address to be used for the comparison in each case depends on the program section a program processed by the processor, which is processed at the time of access of the processor to the cache memory by the processor is selected.

In order to avoid that any data loaded from the main memory in a prefetch should be written directly into the cache memory, it has proven to be expedient for the cache memory to comprise a register memory into which the prefetch data is to be fetched by means of the prefetch means are writable. If the prefetch data stored in the register memory of the cache memory is required, it is given by the latter to the processor and also stored in the cache memory for subsequent accesses.

When using only one register memory, it may happen that after prefetch data is written to the register memory, the program jumps to another cache line where a new prefetch becomes necessary. The old prefetch data in the register memory are not yet read out, but can be used again soon when the program returns. Since there is only one register memory, they will be overwritten because of the new prefetch. If the program jumps back, a new prefetch may be required. To remedy this situation, it has proven to be expedient if a plurality of register memories are provided, in each of which the prefetch data of various prefetch operations can be written. In this case, new prefetch data to be written in should be written to the register memory in which the most recent prefetch data exists while overwriting the oldest.

• Fig. 1 eine Prinzipskizze eines Speichersystems mit zugeordnetem Prozessor,
• Fig. 2 eine Prinzipskizze der Struktur eines Cache-Speichers einer ersten Ausführungsform zur Darstellung der Vorgänge zur Initiierung eines prefetch, und
• Fig. 3 eine Cache-Speicher-Struktur entsprechend Fig. 1 mit mehreren, dem Cache-Speicher zugeordneten Registerspeichern.

Further advantages, features and details of the invention will become apparent from the embodiments described below and with reference to the drawings. Showing:

• Fig. 1 a schematic diagram of a memory system with associated processor,
• Fig. 2 a schematic diagram of the structure of a cache memory of a first embodiment illustrating the processes for initiating a prefetch, and
• Fig. 3 a cache memory structure accordingly Fig. 1 with a plurality of register memories associated with the cache memory.

Fig. 1 shows a storage system 1 according to the invention, comprising a main memory 2 large storage volume, but has a relatively slow operating speed. Associated with this is a cache memory 3, which is a much faster working buffer memory. Connected or associated with the cache memory 3 and the main memory 2 is a prefetch means 4, by means of which, on the one hand, it is determined whether a prefetch is to be performed at all, and, on the other hand, the prefetch is carried out. Assigned to the memory system 1 is also a processor 5, which is in the example shown in communication with the cache memory 3 and the prefetch means 4. The processor 5, which processes a program and has to access corresponding data of the memory system 1, primarily accesses the very fast-acting cache memory 3, in which a large part of the data stored in the main memory 2 has been written in advance. By transferring the data into the memory 3, it is ensured that these are available to the processor in a sufficient speed if required. If, however, a particular address line which the processor 5 wishes to access does not exist in the cache memory 3, then this is loaded from the main memory 2 into the cache memory 3 and from there to the processor 5.

In the Fig. 1 shown overall configuration, which is preferably provided on a common chip, which is advantageous in terms of data transmission and power consumption, is also designed as described for performing a prefetch. As part of this, it is checked on access of the processor to a cache memory line and there to a specific address in the line, whether a subsequent line containing sequential data is also already present in the cache memory 3. If this is not the case, the corresponding missing line is transferred from the main memory 2 into the cache memory 3 via the prefetch means 4 or such a transmission process is initiated.

Fig. 2 shows in the form of a schematic diagram of a possible cache memory configuration and serves to explain the procedures for initiating a possible prefetch. The processor 5 provides an address 6 to the cache memory indicating what data the processor needs. The address 6 consists of a total of three address sections I, II, III. The first address section I indicates the page address of the main memory to which the data of a cache memory line is assigned. The cache memory 3 has a corresponding cache address directory 7 in which page addresses 8 corresponding to the main memory page addresses are stored. Within the cache address directories 7 is now addressed with the address section II and the address section I compared with the contents of the cache address directories. In this case, the page address is "0x01".

The address portion II representing a row address indicates in which row of the cache memory 3 the data stored under the address portion I is present. This information thus represents the link between the cache address directory and the cache. In the example shown, this address information is "Z5". Finally, with the information in the address section III, the address of the respective data to be read out within the line is indicated. As Fig. 2 shows, the cache memory 3 is divided into a plurality of rows Z1, Z2, ..., ZN as well as a plurality of columns S1, S2, ..., SM. The information in address part III is "S6" and thus determines as data to be read those in column S6.

In the example shown, access is therefore made to data which is located in the cache memory 3 in line Z5 and there in column block S6. The information to be read in the example shown is "17".

If the cache memory now receives the address 6 from the processor, it is automatically checked whether the following data, which are stored in the main memory in the corresponding following line, are already present in the cache memory 3. It is therefore checked whether the data line following the address "0x01 / Z5", namely the line "0x01 / Z6" is likewise already present in the cache memory 3. This is done by checking the cache directories 7 in step 9. If the presence of the row is detected, this data is available, if this row is missing, a prefetch might be required to load that row from main memory.

In order to actually initiate a prefetch process, another condition must be fulfilled in addition to the missing line. This is that the processor in the cache memory 3 must access an address which is within a predetermined line segment. This line segment is determined in the example shown using the line segment address "X". The line segment thus defined comprises all the addresses of one of the lines Z1, Z2 ... ZN which are equal to or greater than the line segment address. For example, if the line segment address were X = S5, then the line segment would include all the columns S5, S6 ... SM. If the address S6 currently retrieved by the processor is outside this line segment, no prefetch takes place. If it is within, a prefetch will be performed. This will be checked in step 10. Now, if the conditions of steps 9 and 10 are both satisfied, which is checked in step 11, a prefetch is performed, the corresponding data is read from the main memory and transmitted to the cache memory 3. The steps 9, 10 and 11 are performed in the prefetch means 4, for which it has a corresponding logic and software. It should be noted that the line section value X can ultimately be arbitrarily set, that is, the respective line section can be arbitrarily set in size. If, for example, as in the prior art, the possibility of a prefetch be given for each processor access, the line section value X is set to S1, the line section then comprises all column sections. If a prefetch is not to be performed at any time, the line section value X is set to 0, for example.

Fig. 3 finally shows the configuration of a cache memory accordingly Fig. 2 However, here are the cache memory 3 a plurality of register memory 12 ', 12 ", 12"', 12 '''' assigned, in which in the context of a prefetch loaded from the main memory data is written. The register memories 12 ', ... 12''''associated with a corresponding cache register address directory 13, in which then the respective, corresponding to the main memory addresses addresses are written. By using multiple register stores, it is possible to hold prefetch data for a period of time without immediately overwriting it on a new prefetch, as would be the case if only one register store were present. The write-in strategy may be such that new prefetch data always overwrites the register memory that stores the contains oldest prefetch data. This takes into account the fact that in the processing of programs in which there are very frequent interleaves, not read prefetch data, although read, but were not needed due to the interleaved, are held for a certain time until overwriting because the possibility exists that the program will return to the original line and the data will still be needed. Overwriting by a subsequent prefetch is excluded because this data would be written to another register memory. Finally, it should be noted that the cache memory configurations shown are merely exemplary. The cache memory can be structured as desired. For example, the memory may be implemented as a directmapping cache or as a two-way set associative cache.

Claims (11)

1. Method for operating a memory system (1) comprising a main memory (2) having a cache memory (3) assigned to it that is structured in address-based lines and in which data can be loaded from the main memory (2) and, if needed, read out by a processor (5), the method comprising:

   - the processor accessing data of a specific address in the cache memory (3) where specific data of a corresponding address from the main memory (2) is filed, and

   - is checking during this access if sequential data is filed in an address of the cache memory following the specific address,

   - if the sequential data is not filed in the cache memory (3), the sequential data from the main memory is loaded (11) into the cache memory (3) as part of a prefetch,
   characterized in that the implementation of the prefetch further comprises:

   making a decision (10) that a prefetch will only be implemented when the processor (5) accesses a cache line section or a predetermined cache line section located within a cache line, wherein the predetermined cache line section or the cache line section is determined based on a line section address (X);

   dynamically adjusting the predetermined cache line section or cache line section by setting the line section address (X) based on a current status of operation of the processor (5).
2. Method according to claim 1,
   characterized in that
   the cache line section is defined by means of a predetermined cache line section address and comprises all the addresses of a line that are larger than or equal to the cache line section address, wherein the address within the line, that the processor (5) accesses, is compared with the cache line section address.
3. Method according to claim 2,
   characterized in that
   each line is divided into several line areas having a specific length to each of which is assigned its own line section address, wherein the line section address is compared with the cache line section address.
4. Method according to claim 2 or 3,
   characterized in that
   the cache line section address is provided in the form of a numerical value, wherein a comparative numerical value is determined with the help of the address within the line or the line section address.
5. Method according to one of the previous claims,
   characterized in that
   several line sections of different lengths are determined, wherein the line section, that is used to determine if the implementation of a prefetch is indicated, is selected based on the program section of a program, in which the processor (5) is working at the time of the determination, to be processed by the processor (5).
6. Memory system (1) for data, comprising:

   - a main memory (2);

   - a cache memory (3) structured in several lines,

   - a processor (5) configured to access, if necessary, data of a specific address of the cache memory (3), at which address specific data of a corresponding address was filed by the main memory (2), and

   - prefetch means (4) designed for testing during the accessing of the data of the specific address of the cache memory (3) if sequential data is filed in an address in the cache memory (3) following the specific address, wherein these prefetch means (4) are designed in such a way that if the sequential data is not in the cache memory (3) they will load (11) the sequential data from the main memory into the cache memory (3) as part of a prefetch,
   characterized in that
   these prefetch means (4) are designed in such a way to make a decision (10) that a prefetch will only be executed when the processor (5) accesses a cache line section or a predetermined cache line section located within a cache line, wherein the predetermined cache line section or the cache line section is determined based on a line section address (X),
   these prefetch means (4) are furthermore designed to dynamically adjust the predetermined cache line section or cache line section, by setting the line section address (X) based on a current status of operation of the processor (5).
7. Memory system according to claim 6,
   characterized in that
   each line (Z1, ..., ZN)
   of the cache memory (3) is divided into several line areas (S1, ..., SM) each having a separate line area address comparable with the line section address.
8. Memory system according to one of the claims 6 or 7,
   characterized in that
   several line section addresses are determined or can be determined for determining several line sections, wherein the line section address respectively used for the comparison is selected based on the program section of a program, which is being processed by the processor (5) at the time when the processor (5) is accessing the cache memory (3),
9. Memory system according to one of the claims 6 to 8,
   characterized in that
   the cache memory (3) comprises a register memory (12', 12", 12"', 12"") in which the prefetch data can be written by means of the prefetch means (4).
10. Memory system according to claim 9,
    characterized in that
    several register memories (12', 12", 12"', 12"") are provided in which can be written respectively the prefetch data of different prefetch processes.
11. Memory system according to claim 10,
    characterized in that
    prefetch data to be written for the first time can be written into the register memory (12', 12", 12"', 12"") by the most recent prefetch data being available by overwriting the oldest ones.

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