DE2116784A1 - Program-controlled step memory device - Google Patents

Description

F 4801 JB. APR.

SOCIETE LAMIOMAISE D'ELECTRONIQÜE Route de Perros-Guireö -22- LAMION (France)

and

COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS

CIT-ALCAIEL
12, rue de la Baume -75- PARIS (8). France

PROGRAM CONTROLLED STEP MEMORY DEVICE

The invention relates to expandable or non-expandable, looped or non-looped step memories, which consist of a carrier in which, controlled by one or more feed timers, binary information circulates. The information is composed of words that are formed by a certain number of binary characters, each of which can have the value 0 or 1; the word is the unit of information. If the binary characters forming a word follow one another in time in a single channel of a memory, then it is a question of a word circulating in series , if, on the other hand, the binary characters forming a word are each simultaneously in a special channel

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of the memory occur, it is a parallel circulating Word. A memory is therefore called a memory with a series or parallel structure, depending on whether the words are in In a row or in parallel. In the first case it consists of a single channel; in the second case it consists of so much Channels such as binary characters forming the word are present.

In the following, the totality of the binary ζ oak elements forming a word is called elementary memories, regardless of the type of storage used, regardless of whether it is

it is a Heihen- or a Parallelspeieher This means that the capacity of a memory is determined by the number H of words that it can hold where each word consists of k binary characters.

When the period of the timer is t, the is Circulation time in a channel Tp = ITt, provided it is a Parallel storage and Ts = Hkt, provided that it is a series storage acts, where both memories have the same capacity K. "

In many applications, especially when the Memory is messed up and a permanent circulating memory the period of revolution is constant.

If the timer period t is the same for both memory types of the same capacity N, then Ts = kTp, because the entire Nk binary characters of the serial ^{memory must circulate one} after the other 1 for a binary character to pass through the memory.

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can run j it results from the fact that the parallel storage with the same timer period is known to work faster than the row speakers and that to achieve one with that of a parallel memory, the timer time of a series memory is comparable or the same in circulation is shorter than that of a parallel storage j this means at the same time that the timer frequency of a series memory is much higher than that of a parallel memory, In particular if the capacity of the memories is the same, i.e. N, is the timer frequency of a serial memory having the same round trip time T as that of a corresponding one Parallel storage k times larger than that for parallel storage necessary timer frequency.

Tt> Ts

The totality of the Ή - - or ΪΓ = ■ timer pulses of a cycle T form a time interval in which the pulses can be numbered from 1 to S ". Likewise, the time intervals between two timer pulses within the relevant time interval can be numbered so that information can be determined in time by the signal of its occurrence at the channel input (or output), this signal representing the information address, this is important for writing and reading information. The addressing capacity of a memory is equal to the capacity 'S of this memory In a parallel memory, this capacity is equal to the number of signals t in the time interval T _9, while in a series memory the capacity

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equal to the number of signals t / k of the time interval T, the value t or t / k is determined, depending on whether it is a parallel or a series memory, the number of channels in the time interval T ₇ , this number of channels being equal to the number of words N is.

When using a memory, this is usually the Number of words to be stored is less than the capacity of the time interval ü), which, for example, leads to a restriction operation during a certain period of time.

One solution is to create a JImla, buffer, in which the capacity during a time interval T Equal to Ii is «This requires great costs for the equipment with partial utilization, as full capacity is only reached gradually as demand increases «

•. The memory according to the invention is characterized in that it has only one storage capacity η, that the distribution of the pulses of a timer controlling the storage shift corresponds to the distribution of the words in the time interval T and that in the pulse sequence of the timer only the pulses or groups of pulses which belong to the same order as the words are used. . _t

According to another inventive feature, the feed system of the memory comprises one or more feed systems. _% ; timer, namely the influence of a dreary '. _a number of regularly repeating timer signals

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by a square pulse that reproduces the distribution of the words in the time interval T, ■

Another characteristic is the position of the Information in the time interval T with a not looped Memory changed over time by changing the square pulse.

According to another feature, a memory for η words can be expanded up to N words, in stages or not, by adding the required number of memories and changing the square-wave pulses at the same time.

According to another characteristic, all signals are perpetual of a time interval T applied to a distribution line, with a device that emits the square-wave pulses any changeable electrical lines or bridges connected so that only the signals corresponding to the words in the time interval T are transmitted to the device

The features of the memory according to the invention are described below using an exemplary embodiment and FIG Describe drawings s

- Fig. 1 shows a circulating memory, for example a parallel storage unit, which except for a capacity N can be expanded;

- Pig. 2 is the time diagram of the store behind Fig. II

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Figure 3 illustrates a buffer memory; ί- > ■ .ν

- Fig. 4 is the timing diagram of the memory according to

Fig. 3. - ^: -

^. In lie 1 is the n-step ITmlauf memory rait 1 designated?

2 is a distributor with outputs marked Bf through si to sN ;, 3 is an ODES-Satt® * ¹ . ax to the inputs corresponding to the outputs of the distributor el Ms eE _f 4 is an IMD gate with an input for x · di @ signals of a timer H and a lisgaiig for the ^: awjaiem. Clatter 3 exiting In * - W formation K, - the from Sem Gatter.4 ^: exiting signals H ^x

will be on. the memory t. . Filed, "The-.Distributor 2 and the gate 3-are iilogr-sia @. b0stiiffis # e" ünaslLt iron connections D, for example BI ₉ S2 ^ B9 _S D10 _P 3323 * connected to each other ι the Vertei-tw esiffiiigt Si ^ ialß "from the character about H and time <-

Sj3R: i3kPonisati§3i.®t * 0iisie S. «EI21 Järessenzähler.er 5 'oils il.i.gnal, i3- stes faitgiil? Er3 H wjid ixe Zeitintenrall-Lsatisu-Ssi ^ siaie-Sf # - i #% # 4u Eoiapayato.s * _f der | 3 © i A

das miiim & si ^ W «ag:. &## iö0 ^ gl # S iss Wsm $ m ^^ ww

mm ti

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the AND gate 9 receives; 12 is an AND gate which receives information from the inverter 11 and from the output 17 of the memory 1; 13 is an OR gate whose inputs are connected to AND gates 10 and. 12 are connected, the output 18 of the ÖDER gate being connected to the memory 1 J 14 is an AND gate which receives signals from the output 8 of the address comparator 6 on the one hand and read commands L and square-wave pulses K on the other; 15 is an AND gate, the information from the output 17 of the memory 1 and% receives from the output of the AND gate 14 ■ 19 is the output of gate 15 outputs "of the read information in the memory. 1 . . . ^ .- .; ■, ..; -: ■ - ■■ ..- ;.

The memory according to Fig. 1 -a ^ lii ^ e't '^ oilgenderiisä ^ s ^ i) :: Aiii Jnf ^ ig des ^ eitinte ^ vajis t represents a time interval-

S de »Adrösäfiiiallhler 5 on the first Distributor 2 on the first step, the

Time interval Φ corresponds to? controlled by 'i H, the counter 5 scans the different Adrjss ^ eh $ b _? ^ ii§ While a signal is given to each of the

g sN of the distributor 2 occurs; the connections , W, DlÖ, D23 between distributor 2 and the OR

Gä ^ he _f 3 allow the delivery of a square pulse K, the

4 is applied, which also the signals

H receives and timer signals during the

K outputs j these are the signals H des Vö3? Söhub?! Editor of the memory 1 ·. On the other hand, he receives

■ ■ "■■■ ■■ '■ · ■ r - ■ ■ ■ - · ./.

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21T6784 ** "

the address counter 5 assigned comp.ara ^ toK..6-.about '-, A a .., word address ^r and gives via "8, ^ if A and · .the information _; 7» ,, _; , are identical ,; a command either to read ₁ ... or to write a word- · into the memory, t . ... Gate 9, ₍ that. The output info.rmation of the comparator β eampf ängir, also: a: Einahreibbefehl. Via E ^: and specifies; this. .. 1RS receives the einzu-sehreibenden WSrter *, and transmits this · Vforter to .the OR gate ΐ3 they DAS ⁵ its output s.uf 'memory 1 passes this memory receives the signals H:. of Vorsefetbzeitgebers The words arriving via tS are only written in if a square pulse occurs in the feed timer which corresponds to one or more addresses in time. In the example given in FIG Assuming that the time interval T contains 24 signals t which are each assigned to a word of a parallel memory, the connections D1, $ D2, D9, D18, D23 correspond to a capacity η = 5 of the memory 1.

The information contained in the memory 1 therefore run, controlled by the feed timer, from the input 18 to the Output 17; Any information occurring at the output 17 is applied to the AND gate 12. If no enroll command over E arrives at the AND gate 9, the AND gate 12 receives a write command from the inverter 11, so that the the memory 1 originating and applied to the AND gate 12

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Information is passed on to the ÖDER gate 13 rand via the output 18 of the ODEB-Sairber 13 into memory 1, "If, on the other hand, a JEinschreibbef 6hl arrives via E at the IMD-Gaürce: r 9, Mases transmits the command to> das OT3-Gairfcer 1O ₃ so that = the information arriving over 16 is passed on to the ODEE gate 13 aond lifoer the output 16 of the ODEK gate the%> rather 11, 3 © is written?

12 _a so .that 'the; aais scanning the output 17 of the memory 1 © Informaition ni © 1ai; again in this long-cycle life we> ä | im Speidiei · 1 liat im en "tspreclienänen Augenialblicli: the pre-blooming time given in pin Iiifiormationsweelisel took place»

If the OTB-0atter 14 has a Receives read command, there is this on the UM) gate 15j and the information emerging from the memory 1 is applied to the output 19 of the "AND gate 15. The capacity η of the memory 1 can therefore be fully or partially used, the words being distributed in the time interval T as desired can be; if the distribution of words in the time interval changes, "changing the connections D between the devices 2 and" 3 becomes a change in the advance timer causes, so that square-wave pulses are obtained which reflect the distribution of the words in the time interval T.

If the storage capacity needs to be increased, that's enough it is to expand the available memory by a certain number of binary characters, so that the capacity from η to n1 increases, and the connections D between the devices

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2 and 3 !, the number of these compounds may be at most equal to ill.

Fig. 2 shows the time diagram of the memory of FIG. 1. In this Fig. S denotes the synchronization signals in function of time, wherein the time interval T is the distance between two signals, H denotes the signals of the timer, · in which In the example illustrated in the figure, there are 24 signals during the time interval T. D1, D2, D9, D18 are dependent) | of the time associated with the corresponding connections square pulses of the distributor 2 according to FIG. IjK is a function of the time, the output signal of the OR gate

3 according to FIG. 1, this signal corresponding to the sum of the square-wave pulses D1, D2, DS, D18, D23 .; As a ^{function of the time, H x} denotes the timer signals which are output by the AND gate 4 according to FIG

the signals H to those of the timer H during the Occurrence of the pulse K acts; H and K denote the. two input signals of the AND gate in FIG. 1.

3 illustrates a buffer memory, for example a serial memory, with a capacity n which is less than N. For example, in this figure, 20 is a distributor like that of Figure 1; si, s2, s3 ... sN are the N outputs of this distributor, the time interval synchronization signals at S and at H receives timing signals; 21 is an OR gate with multiple inputs and one on

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a memory 25 lying output 23; ' 22 is a GDER gate with several inputs and one lying on the memory 25. " Output 24; L8, L11, L15, L22 are connections between. the Inputs of the gate 21 and the corresponding outputs s8, s11jBi 5, s22 of the distributor 20? L3, 19, 114, -L19 are Connections between the inputs of the gate 22 and the corresponding outputs s3, s9, s14, si 9 of the distributor 20; K is an output of the memory 25, which is connected to an AND gate 26, which also has the signals of the Timer H receivesj H is the output of the gate 26, which is located on a buffer memory 27, which also receives the information to be stored at E .; 28 is an output of the buffer memory, this output being a row output.

3 works as follows: The distributor 20 receives time interval synchronization signals at S and timer signals ^ certain timer signals are passed on to the OR gates 21 and 22, that is, the timer signals of the order 8, 11, 15, 22 im Time interval 1 are given to gate 21, while the signals of the order 3, 9, 14, 19 are given to gate 22. The signal of order 3 reaching distributor 20 is sent to OR gate 22 and sent via output 24 of this gate to memory 25, where it remains stored until a delete command is issued; the signal of order 8 reaching the distributor 20 is sent to the OR gate 21 and via

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whose output 23 is passed on to the memory 25 and forms the L'oschbefehl 'for the memory 25, which is so free and a ■ Signal from the OR gate 22 can store.

The memory 25 stores the instruction corresponding to the impulse of the 9th order, the erasure being carried out by the impulse of the 11th order 15 is given? ^ Then the memory stores the command corresponding to the pulse 1-9, the erase command being given by the pulse 22. The memory 25 then emits square-wave pulses via its output K, the duration of which is different? The square-wave pulses in the example 3 each have a duration corresponding to the interval between the timer pulses 3 and 8, 9 and 11, 14 and 15, 19 and 22. The AND gate 26 receives on the one hand the square-wave pulses K coming from the memory 25 and on the other hand the pulses ^ lse the timer H and outputs at the output for the duration of the square-wave pulses K ψ timer pulses, which form the pulses H of the feed timer of the buffer memory 27 the. This memory receives information to be stored at E which is present during the different times of the time interval T corresponding to the “emitted square pulses K”. The information E is stored in the buffer memory 27, controlled by the signals of the feed timer; the information stored in the buffer memory 27 is then controlled by this

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BATH ORIGINAL

ψ, ^{> sr} ^

Signals, transmitted from input E to output 28, with the cycle time, i.e. the storage time »equal to the duration of the time interval T. The buffer memory has a capacity n, but the change in the connections L between the distributor 20 and the OR gates 21 and 22 allow the information to be shifted in time »It is also possible to the capacity of the buffer memory 27 to a capacity n1 to increase, which is lower than the maximum capacity N, which corresponds to the time interval T, and additional connections L between the distributor 20 and the OR gates 21 and 22 to manufacture. The capacity can be increased up to the value N.

4 shows the timing diagram of the buffer memory according to FIG. 3. In this FIG. 4, S denotes the synchronization signals as a function of time, the interval between two signals being the time interval T. H represents the signals of the timer, ie there are 24 signals in time T in this figure. L3, L8, 19, LI1, L14, L15, L19, L22 illustrate, depending on the time, the corresponding connections with the OR gates 21 and associated square-wave pulses of the distributor 20. According to FIGS. 23 and 24, the square-wave pulses each apply the outputs 23 and 24 of the OR gates 21 and 22. K is the square-wave pulse emitted by the memory 25 according to FIG. H ^x denotes the advance timer signals which are output from the AND gate of FIG. These signals control the

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Storage of the information E and its circulation in Buffer storage 27..

The invention is generally applied "to any device whose information is in the form of pulses encoded during a time interval T, ie whose mode of operation is based on pulse code modulation, such as in particular in PCM telephone systems. The device according to FIG. 1 enables the use of expandable devices Memory, _fc, for the production of a central memory which summarizes all addresses in a connection circuit, while the device according to FIG. 3 enables the production of a buffer memory with access to the commutators forming a connection circuit.

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Claims (9)

PATENTAir CLAIMS A- Program-controlled step memory device for storing information or words in a Pulse code modulation system in which in a time interval T contain N words of k binary characters between two pulses can be, of which only η words are used, characterized in that it has a memory M (27) with a useful capacity η less than Ή or equal to N and one or more advance timers of the memory, each of which has pulses corresponding to a certain temporal distribution in the "time interval T based on signals from one or more timers with a constant period. 2. Apparatus according to claim 1, characterized in that a feed ^{timer which emits pulses H x has} a pulse shaper which emits square-wave pulses of different or not different duration on the basis of the timer pulses, according to a given controllable distribution, and with an AND- Gate (4,26) is equipped, which emits the pulses of the timer H during the duration of the square-wave pulses K applied to it. 3. Apparatus according to claim 2, characterized in that the pulse shaper consists of a 10984-597 Distribution circuit (2) exists, which is connected to a circuit (3) for generating the square-wave pulses. Any variable. Electrical connections ... or bridges (D1 ... D2-3), with all pulses of the time interval T being given to the distribution circuit which only transmits the pulses of the time interval T which correspond to the words in the time interval via the electrical connections. 4. Apparatus according to claim 3, characterized marked * that the memory M (27) with a capacity of η words to N words in stages or can not be gradually expanded by adding the required Number of binary characters is added and at the same time the square pulses are changed. 5. The device according to claim 4, characterized in that the pulse shaper has a distributor (20), two OR gates (21,22) and a memory m (25), the distributor (20) Έ outputs (St ... SN) has certain pulses from a timer (H) to a first ÖDER gate (21) and certain pulses from the timer (H) to a second OR gate (22), a pulse emerging from the first gate in the memory m (25) is stored and a pulse emerging from the second gate erases the memory m (25), which generates a ^ Becfcteckimp ^ * le'ii ^ eiT ^ g ^ äüsgetrettnen '^: -.-. V-i Pulse abgibti: \ ^=: V; ";;':-' _'y:>: / V, ^-';. ;;:. 109844/1597 6. Apparatus according to claim 3, characterized in that characterized in that the pulse shaper has a distributor (2) and an OR gate (3), the Distributor N outputs S1 ... SÜT) that has certain impulses give a timer (H) to the OR gate (3), which in each case the pulses transmitted by the distributor (2). The timer (H) emits corresponding square-wave pulses (K). 7. The device according to claim 1, characterized in that its memory M (27) can be expanded up to a capacity N, the number of pulses H ^{x of} a feed timer and their temporal distribution depending on the new capacity of the memory M (27) to be changed. 8. Device according to claims 5 and 7, characterized in that in one Advance timer the temporal distribution of the pulses of the timer (H) through variable electrical connections between certain outlets of the IT outlets of a distributor and certain inputs of the OR gates (21,22) is guaranteed. 9. Device according to claims 6 and 7, characterized in that in the case of a timer, the temporal distribution of the pulses of the timer (H) is ensured by variable electrical connections between certain outputs of the IT outputs of a distributor and certain inputs of an OR gate (3) is. 109844/1597