DE2036368A1 - - Google Patents

Description

PHB 31987 Va / PJ Dr. Hcrljert See! "

Patent attorney

Registration H. Y. Philips'OIoeilampenfabrielcÄ

Akin No. ■ PHB-31987
Announcement dated July 20, 1970

"Frequency Synthesizer".

The invention relates to a frequency synthesizer and, more particularly, to a frequency synthesizer, which contains: a nominal frequency generator for generating a pulse series of the nominal frequency in spectrally impure form; a controllable oscillator for generating a series of pulses, the frequency of which - now in spectrally pure form - is nominally equal to the target frequency; an error detection circuit ", the detection of an error between the target frequency pulse train and the pulse train fed to it, nominally of the same frequency, an error signal

109808/2080

PHb "'. 1 ^MW

gives up; and means responsive to this error signal to control the controllable oscillator in dor Vei ^>, that the two frequencies are brought into synchronism.

The previously known frequency synthesis require high manufacturing costs and require extra>! ii often the disadvantage is that their output signals are spectrally correct because the signal is a signal should be pure form and the same frequency, is actually still frequency modulated.

The invention aims to provide a frequency synthesizer to create which supplies a spectrally pure output signal and which is also suitable for production in the form of an integrated circuit, so that the manufacturing costs are reduced.

According to the invention, the frequency synthesizer includes of the type mentioned above, a setpoint frequency generator with one of a clock pulse source operated binary counter, which supplies an output pulse at every transition from 0 to 1, while furthermore a register for. selective passage of the output pulses of the binary counter to an input of the mentioned error detection circuit is provided so that during one cycle of the binary counter a predetermined number of pulses the error =

PHB 319B7

detection setting at the specified frequency (jp leads which error detection circuit contains means with the help of which the size of the error is detected by the fact that the counter position <* otektiert that the binary counter of the aforementioned setpoint frequency generator detects an error. has achieved through the aforementioned error detection circuit.

The invention is described below for an exemplary embodiment with reference to the accompanying drawing nKhrr explained. Show it:

1 shows, in a simplified block diagram, the essential components of a frequency synthesizer according to the invention;

Fig. 2 is a block diagram of a frequency synthesizer according to the invention} and

FIG. 3 is a block diagram of a decimal multiplier which is used in the frequency synthesizer according to FIG. can be installed.

The frequency synthesizer, which is shown in detail in FIG. 2, contains four essential ones Circuit elements shown in the block diagram of the figure. So includes the frequency synthesizer basically an arrangement 1, which the So11frequency supplies in spectrally impure form. The output signal of the frequency synthesizer is a span-

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P]] U 31987

Taken from voltage-controlled oscillator 2, whose pulse series has nominally the same frequency as that of the arrangement 1. The output signals of the arrangement 1 and the voltage-controlled oscillator 2 are fed to an error detection circuit 3 which, after detecting an error, outputs an error signal to an error control circuit k , which in turn controls the voltage-controlled oscillator 2.

The different parts of the frequency synthesizer according to the invention will now be described separately:
Setpoint frequency generator

The setpoint frequency generator 1 contains a clock pulse source 10 which operates a binary counter 20. In a binary counter, only one changes with each input pulse of an individual part Level from 0 to 1. With a four-level counter there is in the level of least importance eight such transitions from 0 to 1, four in the next level, two in the next level and one in the most important level for each cycle of the counter. this means that if from these O-1 transitions impulses all these impulses are derived, because the transitions take place at different times, can be fed to a single output line without the risk of coincidence

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of a full cycle of a four-stage counter, a maximum of 15 pulses on the output line are fed. In the described embodiment the counter 20 appears to have much more than four stages and the number of stages is from that for frequency range required by the frequency synthesizer addicted. A set frequency register is used to obtain a pulse train from the set frequency generator 1 30 is provided, which controls a number of AND gates through which the inu binary transitions through the O-1 transitions Counter-induced pulses have been let through. The AND gates are not shown, but each one Such a gate is assigned to the level of the binary counter 20. When using negative logic, the AND gates replaced by OR gates. By pre-setting the size in the reference frequency register 30 generates the binary Counter in each cycle a predetermined number of separate impulses from the reference frequency register 30 as the target frequency of the frequency synthesizer.v can be selected. The output signal thus obtained on the output line f is, however, spectral not pure. Accordingly, the output signal of the reference frequency generator is used as a reference signal, with respect to which the output signal of the voltage controlled Oscillator 2 is measured. This error scanning takes place in the error detection circuit 3

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The structure of the binary counter 20, its · z AND gates and the setpoint frequency register 30 is un *, or the designation "Dinärvervi el fächer" per se bckaiiii '·. Fault detection circuit 3.

The faulty detection circuit 3 consists of a reversible counter 40, one input of which is the output signal of the setpoint frequency generator 1 and the other input of which is the output signal of the voltage-controlled oscillator 2 via the line f. The two input signals are fed to the reversible counter kO via an anti-coincidence stage 50, so that it is avoided that an input pulse appears at the inputs at the same time.

If the two input signals have the same frequency, the counting position in the reversible counter k0 is _t even though the input signal of the setpoint frequency generator has passed. 1 is not in phase with the spectx * al pure input signal of the voltage-controlled oscillator3 2, never exceed the range from -1 to +1, that is, the counting position will always be within a range of 3.

However, if there were to be a difference between the two frequencies, the counting position would be of the counter 40 can either go above or below this range depending on the polarity of the error. In this way, the error control circuit

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· '♦ ο fed into the I-'phlnrsignal as soon as there is an error of more than one cycle between the Frofjnoii7.cn fed to the counter - Ks is also crf order! I. All the more, there is a greater error between the two Froquen / o ¹ : (lc-tü faster the error is detected ₀ Hei is the preferred embodiment

assumed that the size of the error in counting of the binary counter 20 is inversely proportional. Since the counter 20 continuously with the clock pulse l'requonz counts, is the time between the start of a counter cycle and the detection of an error has elapsed, the counter position in the counter must be just proportional. The size of the error is thus depends on the reciprocal value of the counter position in the counter. This reciprocal value can approximately be achieved by that the error is made equal to 2, where η is the number of leading zeros in the binary number im Counter 20 represents. This number is determined by the advance O-detector 60 specified.

If, therefore, an error is detected in the reversible counter kO , the binary counter 20 is brought to a standstill, the approximate reciprocal of its counter setting with the aid of the advance O-detector 60

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which is formed by an Ai't decoder can be.

In the reversible counter - ¹ JO and in the lead ¹ - ') - detector 60 are now received signals that concern the dio (! Rosse and the polarity of a detected error: ¹ and which are now supplied to the error control circuit k Counters 20 and kO are then reset via the reset line R, so that the established output signal of the voltage-controlled oscillator can be sampled.
Faulty control circuit

This circuit consists of a summon / difference generator 70, to which the signals of the advance U-detector 60 and the counter ^ O are fed and which controls the value stored in an accumulator 80. The sum / difference generator 70 and the accumulator 80 can be of the type described in "Digital Computer Design Fundamentals", chu, publisher McGraw-Hill, pp. 386-391 . This value in turn controls the digital-to-analog converter 9-0, which drives the voltage-controlled oscillator 2. If an error is detected in the reversible counter ho , a sequence of corrections are carried out by the circuit described, by means of which the frequencies of the voltage-controlled oscillator 2 and the setpoint frequency generator are brought into synchronism.

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PHB 3 19ί "7

The genorieno generated by the frequency synthesizer Frequency can be changed with the help of a single rotary knob through which both the setpoint frequency rogi · -.- ter 30 as well as the accumulator 80 can be controlled. This knob can either be turned by hand or, in an automatic system, mechanically driven in such a way that a certain frequency range can be scanned. Such an arrangement is particularly advantageous when the voltage-controlled Oscillator 2 has a linear characteristic.

In the illustrated embodiment actually two digital-to-analog converters are provided, the digital-to-analog converter 90, as described above, the detected errors between the two frequencies are processed while the second digital-to-analog converter 100 is connected directly to the reference frequency register 30 and for rough adjustment the voltage controlled oscillator processes the modified values of a setpoint frequency when these values can be fed to the setpoint frequency register with the aid of the manually operated adjusting disk. this happens only for structural reasons and the second digital-to-analog converter can also be omitted.

The slight changes that are possible in the arrangement of FIG. 2 are made in the

109808/2080

Figures 2a and 2t »shown.

When the output frequency of the synthesizer ^ especially high, e.g. higher than 100 MHs, according to LJ, can be determined by the techniques known up to now. "· make a binary multiplier which at dertioj b «··. Frequency can work. In order to avoid this, Fig. 2a shows an η divider between the voltage-controlled Oscillator 2 and the reversible counter ^ O is arranged. This means that the binary Multiplier η times slower than the voltage controlled Oscillator can work. However, this has the consequence that corrections to achieve synchronism time between the two signals after the detection of an error is η times longer will take.

Fig. 2b shows a variant in which an n-divider is arranged between the voltage-controlled oscillator and the output. The binary © multiplier now works more quickly than the voltage-controlled oscillator and corrections of errors are now possible. made at a speed m times greater *

The arrangement according to FIG. 2 also contains some additional circuit elements that can be used to phase lock the output frequency, when the output frequency is changed step by step.

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For example, it may be sufficient if the »frequency is changed over nine series of 100 cycle steps. Vu dirsom purpose is a Phasendetoktor 110 between dpr Au ρ f ^ a ^ iif .si egg processing f of spannungsßpstoucrton ο · / ·:, ι -t_ tor "2 and the output line for the binary ZAEL-'eif-20th switched on. This phase detector 110 has a zoit constant which is longer than the cycle time of the counter 20, and supplies an output signal to a fine low-pass filter 120 which controls the voltage-controlled oscillator 2 directly. The low pass 120 can be replaced by an integrator.

As described above, this is in the reference frequency register 30 stored number a binary Znh1 The coordination of the binary counter 20, the setpoint frequency register 30 and that controlled by the latter AND gates that the pulses of the binary counter 20 are allowed through is known per se as a binary pre-multiplier. But practical considerations become preferably decimal numbers are used, while the binary multiplier is represented by the one shown schematically in FIG Decimal multiplier can be replaced - The decimal multiplier is the only binary counter 20 is replaced by a number of binary counters 20a, 20b and so on. The output signals of the different Stages are then taken from a reference frequency register, in such a way that each of the decade stages has at most

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PHB 31987

a number of 9 pulses can be taken. Diοκ can be done using standard combinational logic take place at the reference frequency register. The withdrawal can also be made using a 1,1,2,5 code am Reference frequency register take place.

Various other 8 ^ 21 codes can be used in the binary decades; e.g. P.tus-2-, Plus-4 and Plus-6 codes are all used require a 1125 code on the reference frequency register. Theoretically, the reference frequency register can control the pulses Let through each binary decade according to each weighted decade code in which the sum of the weights equals 9, e.g. 1,2,2,4 or 1,2,3 »3 ·

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Claims (5)

PHB .319 * 7 Pa credit claims : nj frequency synthesizer, which contains: a nominal frequency generator for generating a pulse series of the nominal frequency in spectrally non-pure form, a controllable oscillator for generating a pulse series whose frequency - now in pure spectrally pure form - is nominally equal to the nominal frequency; an error detection circuit which emits an error signal when an error is detected between the desired frequency pulse train and the pulse train supplied to it, nominally of the same frequency, and means for controlling the controllable oscillator which is responsive to this error signal in such a way that the two frequencies are brought into synchronism , characterized in that the
The aforementioned setpoint frequency generator contains a binary counter operated by a clock pulse source, which
an output pulse at each transition from 0 to 1
supplies, while also a register for selective
Allow the output pulses of the binary counter to pass
an input of the mentioned error detection circuit is provided in such a way that during one cycle of the binary counter a predetermined number of pulses of the error detection circuit with the mentioned
Reference frequency are supplied, which error detection circuit contains means for detecting the size of the error, which detect the counting position, 109808/2080 PIT 'Ί1''- ¹ which is reached in the binary counter when the mentioned error detection circuit has detected an error in the mentioned setpoint frequency generator. 2. Frequency synthesizer according to claim 1, characterized in that the error detection circuit contains a reversible counter, the transmitted pulse train of the binary counter being a Input and output signal of the voltage t eup r t ο j ι Oscillator is fed to the other input while Means are provided, with the help of which an error signal is generated when the counting position in reversible counter has come outside of a predetermined range. 3 · frequency synthesizer according to claims 1 and 2, characterized in that the error signals of the reversible counter and the means for detecting the "size of the error" fed to an accumulator will. k. Frequency synthesizer according to Claim 3 »characterized in that the accumulator supplies an output signal to a digital-to-analog converter, which converter in turn supplies an error signal to the voltage-controlled oscillator. 5. Frequency synthesizer according to claim h _t, characterized in that the register for passing the pulses of the binary counter directly with a BAD ORiQfNAL 109808/2080 PHH 21 ° ^Q ncm second digital-to-analog converter for coarse adjustment «Lor external frequency of the frequency synthesizer connected is. 0, sequence synthesizer according to one or more of the preceding claims, characterized in that means are provided through which the oscillator at a variety of pre-determined initial risk levels can be made phase-locked. 7. Frequency synthesizer according to claim 6, characterized in that the latter means contain a: phase detector to which the gate pulses of the binary counter and the pulse series of the controllable oscillator are fed and to which a time constant
that is longer than the cycle time of the binary counter
is while this phase detector is either one
Low-pass or an integrator supplies an output signal, which low-pass or integrator in turn
controls the controllable oscillator. 109808/2080