DE2032240B2 - DEVICE FOR SERIAL OPTICAL SCANNING AND EVALUATION OF DATA - Google Patents

Description

The invention relates to a device for serial optical scanning and evaluation of data, which are different by at least three besides other Areas are shown, each area being in the scan direction of each preceding Area is different and in which at least two photosensitive elements are provided, each responding to at least one area type.

■ on / .. for example, from German patent specification 239512 I known recording media, the binary data is represented by the fact that a first binary information by a first recognizable RE-rich

and interpreting a second binary information by a second recognizable area. the the two recognizable areas are spaced apart from one another on the recording medium, whereby the recording medium sections lying between these areas are only used for clock signal generation can be used, and thus a data transfer area is lost. Because the above Intermediate areas not for information recording can be used is for a specific information section to be transmitted relatively large recording media required. Devices that produce such recording media in two Sensing directions is very complicated. From Swiss patent specification 452 246 is a record carrier is known on which data is represented by white, wide black, and narrow black Stripes are recorded. With different scanning speed, the scanning device can can no longer reliably distinguish between wide black and narrow black stripes, since the Intensity or the quantum of the light reflected from the recording medium is evaluated will.

The German Auslegeschrift 1 236 835 discloses a device for scanning a recording medium described, with which can be scanned safely in two directions, since with the help of a counter the recording elements of the same size are counted for each character. This record carrier however, cannot be serial, e.g. B. can be processed with hand-held scanners, since the data is bit-parallel are recorded. This type of recording also requires too much recording area.

From the German Auslegeschrift 1 096 653 it is known to determine the difference values of a colored carrier to evaluate reflected light within a grid square that is scanned at points. This method is only suitable for the evaluation of notes or cards with constant Speed to be moved under a scanning device. The multicolored record of data is also known from French patent specification 1,021,260. These records must be used simultaneously by at least two scanners are scanned when recording surface by combinations of color features should be saved.

It is the object of the invention to provide a serially operating one which is particularly suitable for scanning labels To create a device with which the data scanned by these safely even with different Scanning speed can be evaluated, and with the recording medium in forward and Reverse direction can be scanned.

The device according to the invention is characterized in that a Vidco processing unit generates a signal on at least one of at least three lines depending on the sequence of the signals detected by the pholocmpfindlichcn elements on two lines, and that the sequence of areas is interpreted, with in a Dckodiercinhcit each signal is stored until the next signal is generated, and that this generates first and second binary signals depending on the signals on the three lines, with range transitions of a second sequence is assigned a second binary signal and that the binary signals a memory are supplied to it from the popped in Depending wedge of the scanning device in a known manner in a first or second sequence the who, where each binary signal is inverted when the withdrawal is undertaken in the second sequence.

All transitions that represent a binary "1" when scanning in a first direction are set at ίο Scanning in a second direction, one binary each time Represents "0", i.e. H. when scanning is not carried out in the forward direction but in the reverse direction, arises the complement of the recorded information.

Since the information is not represented by the areas themselves but by the area transitions becomes, the requirement on the time system in the present invention is not very critical. That's why a hand-held scanner can be used with advantage, which operates at different speeds can be guided over the recording medium. Another advantage is that the recording areas are not the same size in the scanning direction have to.

A Nusführungbeispiel the invention is in described below with reference to drawings. In these shows

F i g. 1 a recording medium on which data are applied in coded form, F i g. 2 shows a basic representation of the hand-held scanner, a dichroic mirror and in form ■ a block diagram of the data recognition and processing device,

Fig. 3 is a sectional view taken along the line 3-3 in Fig. 2;

F i g. 4 a detailed block diagram of the detection circuit,

F i g. 5 shows part of the detection circuit according to FIG. 4 to show the synchronization for the Data transfer to the memory area,

F i g. 6 A the first part of a block diagram of the decoder circuit,

F i g. 6 B the second part of the decoding circuit, FIG. 7 an input register circuit, F i g. 8 a label recognition circuit;

9 shows a memory input synchronization unit, FIG. 10 shows the second part of a circuit for the Synchronization of the memory input, FIG. 11 a circuit of the memory unit, F i g. 12 a circuit of the comparison unit,

13 shows a circuit of the program counter unit,

F i g. 14 shows a circuit of the parity check unit, FIG. 15A shows the first part of the output register circuit,

15B shows the second part of the output register circuit,

F i r IΛ the first part of a control unit and 17 shows the second part of the control unit. In Fig. I a record carrier is shown on which a plurality of adjacent different colored stripes are applied of the three different color strips used are each different. On the Recording media according to FIG. 1, strips with the colors green, black and white are used. The green and black stripes are printed on the white support so that there are white everywhere

5 6

Stripes arise where there are no green or black dies attached to the color stripes 52, 54, 56 and 58 Stripes are printed on it. That in the present neten four transitions are thus also through the Invention described as the recording medium, these color strips 24, 26, 28 and 30 are assigned The end label was shown with the coded data transitions. However, the deii last see that there is information associated with both forward and reverse strips; can be scanned in the upward direction. The one on the complement to the first-mentioned transition Code sections applied to the carrier are thus associated information. that on a section four bits, the weight assigned to transition from 52 to 54 is two are represented by four transitions, each associated with the transition from 58 to 60 be summarized. io weight, on the other hand, sixteen. It follows from this that / 3 Instead of the above-described setup. the weights of the by the strips 52, 54, 56 and drawing support structure can also be a recording. 58 shown transitions in a scan direction voltage carriers are used on the z. B. ma- are sloping from left to right. The transition Magnetic areas with different magnetic fields from 60 to the white background of the label 20 properties are provided. 15 is a transition from black to white and represents In the present example it is assumed that a bit that defidas by the second scanning direction is in Fig. 1 shown label 20 from left to ned.

to the right is to be scanned, as indicated by the arrow. The two parity bits are chosen so that the

12 is indicated. The first color transition is a total of all "O" bits modulo 3 of the total

White-green transition, and occurs nn the strip 22 ao corresponds to the "1" bits modulo 3. This allows the

on, This transition represents a bit, the value of which is attached to the white background on the label

is given by the left-right direction. The two ends are used as the first color area

next four transitions will be on the strip 24, the.

26, 28 and 30 are created. The following transitions occur: The data transitions represented by the color transitions on: from green to black, from black 25 bits are under the label in FIG. 1 in terms of value represented by green, from green to black and from black. Go on with the two arrows 12 and 14 Green. This section indicates the number of the two possible scanning directions a'if the E *: string 20 recorded data bits tet. When scanning in the direction of arrow 14, specified. The transition from the strip 22 will reverse the recorded bits to the strip 24 represents a bit that is scanned 30 direction and inverted. Hereinafter weighted sixteen. The will be described how in this case the scanned The transition from 28 to 30 represents a data bit that is being decoded. The transition from one is valued with weight two. The transitions from white stripes to black stripes or from 24 to 26 and from 26 to 28 are accordingly from a black stripe to a green Strcimit rated eight and four. 35 fen or from a green stripe to a white

The first color transition, the one after the strip mentioned above, represents the binary information "1". A

the th section is scanned, is a transition from a transition from a white stripe to a green

the strip 30 to the strip 32. This strip or from a green strip on

Information associated with transition is called pari- a black stripe or from a black one

ity bit used. This transition is a transition of 4 "stripes to a white stripe

from green to black. The next four super-binary pieces of information represent »0«.

gears, which when scanning from left to right It follows from the above definition that

occur at the strips 34, 36, 38 and all recognized as "1" in a first scanning direction

40. These four transitions are also with corresponding information when scanning in a two

rated by the weights. The transition from 32 to 45 direction will be recognized as "0". The one at one

34 takes place from black to green and will represent the character recognized with the first scanning direction

Weight one provided. The transition from 38 to complement to those in a second scan direction

40 goes from white to black and is represented with the recognized character.

Weight rated eight. The evaluation success of the In F i g. 2 shows a scanning device,

Transitions thus increases with a scanning direction of 5 ° which has a stylus 62 which is ζ. B. by a

left to right. Sales person at an automatic registration

Which is activated by the colored stripes 42, 44, 46 and 48 checkout handling point. The scanning stand Transitions make z. B. a number with the pen 62 is in the form of a pen holder so that he lowest weight. From 42 to 44 a can easily be guided over a label. Other Black-to-white transition, the scanning devices that can be used with the 55 are generally weighted one is rated. The transition from knows and can also be successful in the pre-black after the color strips 48 and 50 are white, the present invention will be used. It is not rated with the weight eight. Both the consequence absolutely necessary that the scanner has the of the individual bits as well as the sequence of the individual label is moved. It just depends Sections will be in a scanning direction from the left 60 that a relative movement between the scanner to the right with an ascending weight sequence and the label, The transition from the strip 50 to the light source 64 is in a housing 68 on Strip 52 is attached to a transition from white to black in a conventional manner. In this case and just like the transition from 30 to 32, there is also a converging lens 70 and a Representation of a parity bit used. Independent 65 converging lens 72, which ervon from the light source 64 The direction of scanning signals with light reflected in the opposite direction are fed into a section 78 from a set binary value, there are transmission differences between these two optical fiber bundle transitions. Transfer order. The converging lenses can, if

(ο

it is desirable to combine with the light source 64 red and non-infrared light components

be set up as an integrated module. sorb.

The section 78 of the optical fiber assembly The output signals of the light-sensitive EIc-

74 directs the light generated by the light source 64, elements 102 and 104 reach a level of intensity.

through the stylus 62 onto the label 20. The dressing unit 106, in which two separate amplifiers are provided,

Schnilt 80 is also made up of optical fibers. The amplified signals get over

and directs the light reflected from the label onto lines 108 and 110 into the recognition device.

cinen dichroic mirror 100, which is in a Gc- direction 112. This device decodes the over

häusc 76 is arranged. The optical Fascranord- the lines 108 and 110 incoming signals,

tion 74 is surrounded by an abrasion-resistant protective cover and generates a binary data signal in each case.

give. One end of the optical fiber array speaking of those arriving on these lines

is connected to stylus 62 at 82. Signals. This signal arrives on line 113

In Fig. 3, the stylus 62 is along the line in a data processing device 114. Last crc

3-3 shown in section. At 86 and 88 are with an input device 16 or with a

Epoxy layers are shown connecting the optical fiber 15 viewing device, e.g. B. a cash register

bundle 90 surrounded. The individual optical fibers can be.

can e.g. B. a diameter of 0.076 mm. In Fig. 4 is a video processing unit 115 point. The small white circles in Fig. 3 represent the provided over lines 108 and 110 the optical fibers, which also run the non-infrared signal components and the infra in section 78, while the small black circles are laid out in 20 red signal components. The on Figure 3 indicates the optical fibers carried by the binary occurring on lines 108 and 110 Follower pen 62 over section 80 to housing data represent the color transitions of color 76 to lead. stripes white, green and black. According to the

In stylus 62 is a conventional lens scr signals appear on lines 120, 122

Lens 94 arranged, the from the light source 64 25 and 124 signals. A occurs on line 120

signal received via section 78 of fiber array 74 if both the photosensitive element

The captured light is focused on the label 20. The on 102 as well as the photosensitive element 104 a

The light spot that arises on the label 20 is roughly as signal generated. Then arises on the line 122

as large as the width of the signal on the label 20, if only the photosensitive element

borrowed color tires. Which has generated a signal from the label 20 reflex 30 104. On line 124

oriented light passes through the objective lens 94 in which there is a signal if neither the element 102 nor

optical fiber assembly 74 and section 80 the element 104 has generated a signal.

onto dichroic mirror 100 in housing 76. A decoder unit 126 (FIG. 4) receives the

The enclosure 98, which surrounds the dichroic mirror signals "white", "green" and "black" from the 100 and the photosensitive elements 102 and 35 video processing unit 115. Correspondingly, the-104 is opaque. Of the dichroic signals, signals with the logic level mirror 100 reflect a part of the received "1" or "0" generated, which are fed to an input register of light on the photosensitive element 102, select 128. In the input register 128, the remaining part of the light through the mirror is temporarily stored after the data have been decoded in 109 through to the photo-sensitive element 104 * o of the decoding unit 126. Got from. The mirror is transparent for the infrared portion of the input register 128, they become a bc-Lichtcs, so that this is transferred to a memory 130 at the infrared-specific time,
sensitive element 104 can arrive. The rest of the memory 130 contains a 5-bit auxiliary memory portion of the light is reflected from the mirror 100 onto the register 132, the input of which is reflected with the output of the non-infrared-sensitive element 102. 45 input register 128 is connected. Between the two components of the radiation are reflected by the auxiliary storage register 132 and an output register label 20, when a light beam through 148 a storage register 134 is arranged. The storage register 134 pointing the stylus 62 at a white stripe may be made of 128-bit metal. If the light beam is directed onto a black oxide semiconductor shift register or some other strip, none of the components will consist of a shift register type. Reflected in the memory 130. If the light beam reaches a green one, a total of 133 bits can be stored, the stripes, so only the infrared portion of the label is scanned. Thus light can be reflected. In the described device on the label 30 digits of 4 bits each are recorded on the label 20 green, black and become. The memory 130 is constructed in such a way that each strip is used, but other color combinations can also be applied because the newly arriving data is provided by the auxiliary. Storage register 132 into storage register 134 about when the infrared and non-infrared signal communications are carried out. The components in the storage register 134 are used for evaluation, borrowed data can circulate in this,
A memory input synchronization unit 136 is used, which would have to reflect both non-infrared and a comparison unit 147 components with the input register 128, an end-of-label infrared or near infrared component. Connected in place of the green stripe and a program counter unit 140. You can also use strips that receive signals from the label end detection absorb non-infrared components, and infrared device 138, from the comparison unit 147 and red or near infrared areas 65 from the program counter unit 140. It controls the Reflect light components or are too transparent for this data transfer into the auxiliary storage register 132. In place of the black stripes of a certain time.
Colors can be used that are both infra- The stylus 62 in FIG. 2 can be used with different

The speed can be sensed via the label 20 . The speed can e.g. B. contribute 1520 mm / sec or more for each digit. It is therefore necessary to determine when the stylus 62 has completely scanned the label 20. This task is accomplished by the label end detector 138 by generating a "label end" signal when the stylus 62 is swept over a white strip that is at least four times as wide as a black or green colored strip. After the "label end signal" which is generated by the label recognition device 138 , the data in the memory 130 and in the output register 148 are checked, whereby it is determined whether they represent value information.

The last five bits read from the tag represent a four-bit section and a direction bit. These bits are stored in the auxiliary memory register 132. The bits belonging to the section, which are now located in the auxiliary memory register 132 , are compared by the comparison unit 147 with the bits representing a section in the output register 148 when a "label link signal" is generated by the device 138 . If two numbers are the same, a signal is applied to the parity check unit 146 , whereby the parity check is initiated. A parity check signal occurs when the sum of the "I" bits equals the sum of the "O" bits. The stored bits are added up modulo 3 (only the numbers 0, 1 and 2 may result in the sum, if 1 is added to 2, the result is 0).

The forecast counter unit 140 contains a 7-bit program counter which can count up to 128. The count of this counter is incremented each time the data in memory register 134 is shifted by one position. The program counter unit applies a control signal to the memory input synchronizer 136 , which ensures that the data transferred from the input register 128 to the auxiliary memory register 132 7u can only be transferred in the counting area between 127 and 007. The maximum count 127 is again followed by the count 000.

The input of the output ^r egislcrs 148 is connected to the Spcichcrregistcr 134th Its output leads to the one shown in FIG. Datenverarbcitungsvorrichtung 114. shown 2 The output register 148 is a shift register to which the Daienbits are applied in one direction and the follower pin 62 is guided over the label 20, these data bits in forward or reverse Rich Lung, depending on the direction in which, the data processing device 114 supplied. The data to be transmitted are thus sometimes reversed in sequence before they are further processed.

A conventional circuit is used as the clock signal source 127 , which generates two main clock signal trains. The first is drawn below as "bar 1" and "bar 3". Both clock signals have the same pulse repetition frequency, but they have a different temporal position within this frequency. The two clock signals can also be generated by the data processing device 114 as a function of the main clock signal. They are required in storage register 134 .

The logic circuit of the recognition system can be accommodated in a separate function block will. The main functions performed by the logical unit are 1. Conversion of the video signals in binary signals, 2. Storage of the decoded bits, 3. Identification of the Labels, 4. Assessment of those on the LItikctt Information and 5. Output of the data to a display device, a cash register or a data processing unit.

The decoding unit 126 in FIG. 4 converts the "black", "green" and "white" signals into binary 1 "or" 0 "signals. The logic consists of flip-flop modules, in which it is stored whether a first or a second color strip has been scanned.

When a first color has been saved and a second occurs, a "data blanking pulse" is generated, which indicates that a color transition has occurred. The second streak found will turn stored in a flip-flop until a next color stripe is detected.

Each time a "data blanking pulse" is generated, the binary signal arriving on the data transmission line is stored in the input register 128. This register is required because the data are scanned asynchronously, but are to be supplied to memory 130 at a specific time. The size of this register depends on the access rate of the memory. In the version described here, an 8-bit register is used.

3 "The program counter unit 140 contains a security level binary counter which controls the flow of data into the memory 130. The value of the program counter is increased by one each time the data in the memory is shifted one place. If new data have already been scanned and even previously sampled data in memory, the new bits are stored in the locations in which previously were the previously sampled data. the Programmzählcrcinheit executes this control together with the Spcichereingangs-Synchronisicrcinhcit 136 through.

New data can only be entered in the memory register 134 in the period in which the program counter has the count "0".

»» Hen new i ^ atenoits are entered into memory becomes the counter in the program counter unit reset to "0" each time after the last data bit has been entered. Whenever the program counter reaches the count value »0«

the input register 128 is checked to see if any new data bits were sampled in the previous period while the counter was in the "0" counter position.

In Figure 5, three new data bits have been sampled.

entered into the first three stages of input register 128 . When the program counter reaches the count "0", the three data bits are entered into the auxiliary storage register 132 , and at the same time those on the left in the input register 128

standing last sampled three bits shifted to the right. Those at the three right Speichcrstcllen the auxiliary storage register 132 bits are shifted into the storage register 134. When the input register 128 does not store any more data, the program counter is reset to the value "0". The program counter is reset at the moment when the last bit is inserted into the memory register 134 and takes place

aiiiomutisch through the necessary synchronization. The data transfer from the input register 128 into the auxiliary memory register 132 and into the memory register 134 occurs whenever the input register contains new data bits and the program counter has a count of "0" but the end of the label has not yet been determined.

The auxiliary memory register 132 contains the last five bits which are scanned by the scanning pin 62 became. The value stored in the 1 auxiliary storage register 132 is compared with the counter country of the program counter to determine the Set the time in which the data is transferred from the memory register 134 to the output register 148 will. The information section stored in the auxiliary memory 132 is then copied with that in the output register compared to the current information section, and if an over-forehead mon »is found a label value signal is generated, which initiates an inoduIo-3 parity check.

A modulo 3 rarity check is carried out every time carried out when a wcrtiketlsignal is detected. According to the foregoing Test procedure, the sum of all "Ic bits" must be equal to the sum of all "(!" Bits, taking into account the be niodulo-3-counting. The table below gives an overview of the modulo 3 parity check procedure for different recording media, each with a different number of recorded Contain data bits.

Modulo 3 parity check

total Digits UiIs Modulo-.V / .iihlung Sum "0" 20th Sum "1" 1 4th 28 1 2 6th 36 2 0 8th 44 ■ 0 1 10 52 1 2 12th 60 2 0 14th 68 0 1 16 76 1 2 18th 84 7th 0 20th 92 0 i 22nd 100 1 2 24 108 2 0 26th 116 0 I. 28 124 1 Ί 30th 132 2 ü 0

With the modulo parity check procedure described above, "1" -bit errors and multiple errors are generated recognized that are not due to a multiplication by 3. Neither can mistakes which are based on the fact that a "0" is read as a "1" and a "1" is read as a "0" at the same time.

Whenever the values of a label have been decoded and determined by the parity check if it is a question of a value or amount, the data buses are fed to a data processing device. The output register 148 exists from an eight-stage shift register in which the data is moved both to the left and to the right can be moved. The data are each shifted to the right in the output register 148 entered. When transferring from the output register 148 to the data processing device the shift direction is determined by the value of the "direction bit" scanned by the label was decided. If a label was scanned from right to left instead of left to right, the complement is formed from all scanned bits. The transfer from the output register 148 into the data processing device takes place in a reverse order than they take place ίο would if you scan from left to right would.

Decodic purity (Fig. 6 A and 6B)

When Figures 6A and 6B are taken along line 6-6 are brought together, the circuit of the decoding unit is created. by 126 in FIG. 4 indicated is. Input lines 120, 122 and 124 are connected to invertcm 182, 184 and 186. A NAND gate 188 has a first input which is connected to line 120. A second entrance is to the output of inverter 184 and its third input to the output of inverter 186 tied together. The NAND gate 188 generates a "0" output signal when the line 120 has a "white signal" and the lines 122 and 124 neither a »green signal« nor a »black signal« exhibit. The inverter 190 inverts the output of the NAND gate 188, i. i.e., it generates a

Output signal with the level "1" if only a "white signal" occurs at the input of line 120, however, there is no “black signal” and no “green signal” on lines 122 and 124 is.

Using the same principle, a NAND gate 192 and an inverter 194 generate a logical "1" - Output signal when a "green signal" occurs on line 22, but on lines 120 unc 124 no “black signal” and “white signal ahead”

tying is. A NAND gate 196 and an inverter 198 generate a logic "1" signal when a "Black signal" occurs on line 124, but neither a "white signal" on lines 120 and 122 a »green signal« is still present.

The output of the inverter 190 is connected to the first input of a NAND gate 200, while rend its second input is connected to the output of an inverter 267 (Fig. 6B). To the last named second input becomes a »transmission

blocking signal «applied. The ^ transmission lock signal «prevents new data from being entered into memory 130, although dii Data sampled from a previous label is still in memory 130 since these could not yet be fed to the data processing system 114 (FIG. 2). In these In this case, the entry of new data is delayed for a predetermined time (e.g. 100 microseconds) After this time there are also transmission disturbances

signals subsided.

The output signal of the NAND gate 200 is be C with the unconditional clear input of a flip-flop] 205 connected. The flip-flop 205 is shown in somewhat more detail and represents the mode of operation

of all flip-flops used in the circuit. A truth table is given below which can be used for the flip-flop 205 and for all flip-flops used in the circuit is valid.

3C14

Flip-flop truth table

0 O Q _n (no change)

1 O 1 (set)

0 10 (delete)

1 1 Q, ⁺¹ (change depending on

state)

(n means a clock time which is defined by the clock pulses which are applied to the clock signal input T. It is assumed that / i = 0, 1, 2, 3, etc.).

The signals appearing at J and K determine the state of the flip-flop in accordance with the aforementioned truth table. If an "O" signal is applied to C , the flip-flop is cleared. If a signal with the level »0« is applied to P or to the preset input, the flip-flop is set.

If the flip-flop 205 is unconditionally cleared, a signal with the level "0" is generated at Q and a signal with the level "1" at JJ . The flip-flop 205 is cleared when a signal with the level "0" occurs at the output of the NAND gate 200. The outputs of the NAND gates 202 and 204 are connected to the C inputs of the flip-flops 206 and 207 in the same way. The clock signal inputs T of flip-flops 205, 206 and 207 are connected to NAND gates 246, 252 and 256, through which they receive the signals "white set", "green set" and "black set". When the "transmission blocking signal" from inverter 267 assumes the value "1", a signal "0" then arises at the output of NAND gate 200 if the output of inverter 190 also has a "1" signal. If the "transmission inhibit signal" assumes the value "0", the NAND gates 200, 202 and 204 can no longer generate a "0" signal at their output, which is fed to the flip-flops 205, 206 and 207 as a clear signal.

The input K of the flip-flop 205 is permanently connected to ground, so that a "0" signal is constantly applied to it. The input / is not occupied, which means that there is a constant "1" signal at this input. When the “White set” signal takes on the value “1” and a “1” signal is applied to the C input at the same time, the flip-flop 205 can be set. The £ 7 output of flip-flop 205 is set to "0" and is applied to input J of flip-flop 210 and to input C of flip-flop 212. The signal (7 at the output of flip-flop 205 is referred to as the "white locking signal". Before the scanning pen 62 is initially moved over a white strip, there is a "0" signal at the input / of the flip-flop 210, which is output from the output (3 of flip-flop 205. Flip-flop 210 is cleared when a "1" signal is simultaneously applied to its clock signal input. This is the case because output Q of flip-flop 205 is cleared via NAND gate 200. This results in at its output ~ Q a "1" signal is applied to the input / of the flip-flop 21 "and when the" clock 1 signal level becomes "1", this signal is simultaneously applied to the flip-flop 210, whereby When the flip-flop 210 is set, it sees a "!" signal at its output Q and a "0" signal at its output (7). The signal produced at the output Q of the flip-flop 210 is called "white pulses " designated.

When the flipflop 205 is cleared by the NAND gate 201, a "1" signal is sent to the input C of the flip-flop 212. The input / of the flip-flop 212, which is connected to the Q output of the flip-flop 210, receives a " 1 »signal when flip-flop 210 is set. Since the flip-flop 212 at the beginning

ίο was deleted by the "0" signal occurring at output g of flip-flop 205, a "!" signal is initially generated at output £ J of flip-flop 210, which is connected to input K ■. When the "measure 1" signal takes on the value "1", it will

FlipHop 212 set. When flip-flop 212 is set, entsieht at its output 7 a £ "O" -Signaf, the C _g elsewhere at the entrances of flip-flop 210 is applied. This clears flip-flop 210 again. If at the clock signal input of the flip-flop 2 »5

If a "!" signal is applied, this is reset to its initial state.

When the stylus 62 is swept over a green stripe, the flip-flops 206, 214 and 216 become operated in the same way as the flip-flops 205,

210 and 212 when a white stripe is scanned by the stylus 62. When the stylus 62 crosses a black stripe, the flip-flops 207, 218 and 220 are operated in the same way, like flip-flops 205, 210 and 212 when a white stripe is scanned.

NAND gates 222-228 in FIG. 6B receive the corresponding "color lock signals" and "color signals" from flip-flops 205-220. For example , NAND gate 222 receives a

»Green signal« before the exit ζ? of flip-flop 214 and a "black signal" from output 5 ^of flip-flop 218. A "1" signal at the output of NAND gate 222 indicates that either a "green signal" or a "black signal" is generated

became. In the same way, the NAND gate 224 generates a "1" signal, which indicates that a "white signal" or a "black signal" was generated. The NAND gate 226 then generates a "1" signal, when a "white signal" or a "green signal" has been generated.

The output signals of NAND gates 222, 224 and 226 are sent to NAND gates 240, 250 and 254 applied to generate a "white reset signal" and a "black reset signal". The exit

of the NAND gate 222 has a first input of the NAND gate 240, the output of the NAND gate 224 is connected to the first input of the NAND gate 250 and the output of the NAND gate 226 is connected to the first of the NAND gate 254. Each of the named NAND elements receives a "value transfer signal" from the terminal 602 which is connected to the control unit 142 of FIG is. The »value transfer signal« assumes level »I« when video signals from the video

processing device 115 of Fig. 4 to the decoding unit 126 are transmitted.

Selecting the time during which the signals from the video processing device 115 to the Dccodiercinhcitl26 are transmitted, the NAND gate 240 then generates a signal with the level "0", if a »green sign« or a »black signal« auflrill. The first input 604 of a NAND element 242 receives a "clock-1" -Sionnl and a two-pin pin

output 606 a "value transfer signal". The NAND gate 242 generates a signal with the level "1" when information is transmitted from the video processing device 115 to the decoding unit 126 and if no information is transferred between the aforementioned units, the NAND gate 242 generates an "O". -Signal during the occurrence of a bar 1 signal with the level »1«.

The output of the NAND element 240 is connected to the first input of a NAND element 246 , the second input of which is coupled to the output of the NAND element 242. The NAND gate 242 causes NAND gates 246, 252 and 256, reset signals for the flip-flops 210 to produce up to 220, when the follower pin 62 of the label has completely crossed. The stylus 62 has traversed all of the color strips as well as a white section which is four times the size of a single color strip.

In the same way, the NAND gate ao 252 generates a »green reset signal« with the level »1« if a »white signal« or a »black signal« with the level »1« is generated and the »value transfer .iüungssignal «also has the level» 1 «. In the same way, the NAND gate 256 generates a "black reset signal" with the level "1" if a "white signal" or a "green signal" is generated with the Pcgei "1".

When flip-flop 205 is cleared by the occurrence of a "white signal" on the line 120, it remains in its erased state to a "green signal" or a "Sclrvarz signal" is generated, and thereby the NAND gate 246 is a "White reset signal" with level "1" generated. This signal is applied to the clock input of flip-flop 205 , which means that it can be reset if a "!" Signal is simultaneously applied to its inputs.

The NAND gates 222 to 238 are connected to the flip-flops 205 to 220 and receive the various color interlocking and color signals generated by said flip-flops. The NAND gate 228 has the "green locking and black signals" at its inputs and therefore generates a signal with the level "0" if both pulses occur simultaneously. The "white locking and green signals" arrive at the inputs of the NAND gate 230 and the "black locking and white signals" at the inputs of the NAND gate 232. The two last-mentioned NAND gates then generate each a signal with level »1« if the respective impulses appear at their inputs at the same time. The outputs of the NAND elements 228, 230 and 232 are connected to the inputs of a NAND element 258 , the output of which generates a "1" signal when three "0" signals are present at its inputs. The output of the NAND gate 258 is connected to the input of the inverter 260 .

When the stylus 62 is filled over the label 20 , when a green stripe is scanned, a "1" green lock signal is generated, and if a black stripe is subsequently detected a "black signal" is generated at the level "1"'- generated, whereby a recorded "O" bit signal is recognized. If a recorded "O" bit is recognized, a signal with the level "0" is produced at the output of inverter 260. The outputs of the NAND elements 234, 236 and 238 are connected to three inputs of a NAND element 262 , the output of which is coupled to the input of an inverter 264. The "white locking signal" and the "black signal" are thus at the inputs of the NAND gate 234, while the "black locking signal" and the "green signal" at the input of the NAND gate 236 and the "green -Locking signal "and the" white signal "appear at the inputs of the NAND gate 238 . A signal with the level “1” appears at the output of the inverter 264 when a recorded “O” bit is detected. Conversely, a signal with the level “1” appears at the output of the inverter 260 and a signal with the level “0” occurs at the output of the inverter 264 when a recorded “1” bit is recognized.

The NAND gates 266 and 268 are cross-connected to form a locking circuit. If a "1" oii signal is recognized, the "1" signal from the output of the inverter 260 and the "Ü" signal from the output of the inverter 264 switches the NAND gate 266 to the "0" State and the NAND gate 268 in the "1" state. If the NAND gate 268 is switched to the “1” state, a “!” Signal appears on the data line and at the output terminal 608. If an “O” bit is detected, the “1” signal on the Output of inverter 264 and the “0” signal from the output of inverter 260 put the NAND gate 266 in the “1” state and the NAND gate 268 in the “0” state. This produces a signal with the level “0” at output terminal 608. The outputs of inverters 260 and 264 are connected to the inputs of a NAND element 270 , the output of which is in turn coupled to the input of an inverter 272. Every time a "1" bit or a "0" bit is recognized, a signal with the level "1" appears at the output of the NAND element 270 , which is output as a signal with the level "0" at the output of the inverter 272. appears. If neither a “1 ” bit nor an “O” bit was detected, the output terminals of the inverter and 260 and 264 have signals with the level “1”. The output of inverter 272 represents a "data pulse" that can be tapped at terminal 610.

The NAND gates 274 and 276 are cross-connected to one another and form a trap circuit. The output signal of the NAND gate 274 arrives at an output terminal 612 and is called the "data value signal". The signal produced at the output of the NAND element 276 arrives at an output terminal 614 and is called the "data value signal". If a "0" signal arises at the output of the inverter 272 , the NAND element 274 is switched to the "1" state and the NAND element 276 to the "0" state, albeit at the same time the "data return signal" is applied to an input 616 of the NAND gate 276 . This signal comes from the input register 128 (Fig. 4). The “data reset signal” at terminal 616 changes to a “0” level when the “clock!” Signal has a level of “1”.

The output of an inverter 308 is connected to the input of a NAND gate 261 which is cross-connected to a NAND gate 263 and forms a trap circuit . At the input of the NAND gate 229 are the "white signals", the

"Green signals" and the "black signals". A “color signal” is generated at terminal 618 when the link condition for NAND element 229 is met. The fourth stage of a counter 310 in FIG. 8 generates the "delayed reset signal" which occurs at terminal 629 and arrives at the input of NAND gate 263. Whenever a "1" signal occurs at the output of NAND element 229 and the "clock 1" signal is simultaneously present at terminal 621 , a "reset signal 310" is generated on line 621 by a NAND element 306 ( Fig. 8), which resets the counter 310. If a "color signal" with the level "1" occurs, the NAND gate 261 is switched to the "1" state and the NAND gate 263 to the "O" state, as the "delayed reset signal" and the signal have a logic level »1« at terminal 620. . The counter 310 in Figure 8 is incremented by one when the output of NAND gate 320 is a "" - Signa! arises, which is applied to the value increase input of the counter 310 . The "delayed reset signal" at terminal 622 will assume a logic level "0" after the "reset signal 310" has assumed the value "1". For example, this happens 10 microseconds after the "reset signal 310" on line 621 has assumed the value "I" again. When the “color signal” has been generated by the logic element 229 , a “(!” Signal occurs at the output of the inverter 308. And when the “delayed reset signal” at the terminal 620 has the value “1”, the NAND element is activated 263 is switched to its "0" state and the NAND element 261 is switched to its "1" state. The output of the NAND element is connected to the input of the NAND element 265 , the second input of which is connected to the control unit 142 (Fig. 4) through which a "value transfer signal" is applied to terminal 624. If two "!" Signals are present at the input of the NAND gate 265 , an "O" signal is generated at its output, which is used as a "transmission blocking signal" and is applied to the inputs of NAND gates 200, 202 and 204 (FIG. 6A) via inverter 267. The delay in the "transmission inhibit signal" is caused by the "delay reset signal" at terminal 620 , which ensures that transmission interference signals not in the recognition system m arrive when new information bits are recognized.

Input register circuit (Fig. 7)

An input terminal 630 connected to a NAND gate 278 is coupled to the output terminal 612 of the NAND gate 274 (FIG. 6B), whereby "data value signals" are transmitted by the NAND gate 274. The "Tnkt-1" signals arrive at the second input 632. 634 of the NAND-limb transition s on the third A 278 reaches the "Ausblenduntcrdrüekungsimpuls" the Speichercingangs-synchronizing unit 136 (FIG. 4). This pulse prevents new data from being entered into register 280 during the time that data is being transferred from register 280 to memory 130 (FIG. 4). Thus, if the "clock 1" signal at terminal 632 and the "data value signal" at terminal 630 and the "fade suppression signal" at terminal 634 each have the value "I" at the output of NAND gate 278 "0" signal is generated.

The "clock 3" signal is applied to an input terminal 638 of a NAND gate 290 , and the "fast shift inhibit signal" is applied to the second input terminal 640, which is connected to the memory input synchronizer unit 136 (FIG. 4) . This signal has a level of "1" as long as data in register 280 is

ίο are stored, which are then transferred to the saliva 130 (Fig. 4). If at the same time a "clock-3" signal occurs, a "(k signal appears at the output of NAND gate 290th

The outputs of NAND gates 278 and 290.

are at the input of a logic element 292. The output of the NAND element 292 is connected to the shift input of the shift register 280 . Every time the NAND gate 292 generates a "1" signal, the data stored in register 280 is shifted one position in the direction of the output. The shift signal also appears at terminal 642.

The NAND gates 284 and 28ό are cross-connected to one another and form a trap circuit.

The output of a NAND gate 282 is connected to an input of the NAND gate 284 , while its first input is connected to a terminal 644, to which the "clock 1" signal and its second input is connected to a terminal 646 , to the the "data value signal" is applied from terminal 614 (FIG. 6B). The output of the NAND gate 282 only has a "0" signal if the two signals at the inputs have the values "1".

The “data value signal” we applied to terminal 630 has the value “0” if the “data value signal”. which is switched to the NAND gate 282 has the value "1". A "!" Signal is thus produced at the output of the NAND element 278 when the NAND element 286 is switched to the "O" state and the NAND element 284 to the "!" State.

If a "1" signal is produced at the output of NAND gate 282 , a "(!" Signal is produced at the output of NAND gate 278 , with NAND gate 284 in the "(!" Element 286 is switched to the “1” state, as a result of which a “1” signal is produced at the output of NAND element 286. A NAND element 288 has an input which is connected to the output of NAND element 286 . Its second input is connected to a terminal 648 , to which the "clock 1" signal is applied. If the "clock 1" signal has the value "1" and at the same time a "1" at the output of the NAND gate 286 "Level is present, a" data reset signal "with a level" 0 " is produced at terminal 650. This signal is connected to the input terminal 616 of the NAND gate 276 in FIG.

A "detection signal" is applied to the first input of a NAND gate 294 from the output terminal 608 of the NAND gate 268 (FIG. 6B), while a "detection signal" is applied to the second input, which is connected to the memory input synchronization unit 136 (FIG. 4).

connected, the "fade-out prevention signal" is applied. The output of the NAND gate 294 is connected to an input of a NAND gate 296 , the second built-in part with the Au «i>: inu

19 20

a NAND gate 100 is connected. The NAND "bar 5" and "bar 6" signals are generated by the element 296 at its output ei.i "1" data "bar 1" and "bar 3" Signals of a known type signal applied to line 656. Except- derived. If at the output of the NAND gate is the output of the NAND gate 296 with 322 a "(!" Signal occurs, the value of the ZHhdem input of the first flip-flop stage of the register 318 is increased by one in each case
280 connected. An inverter due to the pulse repetition frequency 204 is connected into this connection. Every time the counter 310 counts a shift pulse to register 318 six times as fast as the counter ? 92. -The status is before new information is entered into the register and the io contained in it is transferred from the counter 310 to the counter 318, data are shifted by one place in the direction of the output which is produced at the output of a NAND gate 324. _sen inputs with the individual stages of the counter The output of the NAND gate 300 is connected to the 318, a "(!" signal. ! «Signal The one input of the NAND gate 300 is via 15 indicates that the scanning pen 62 scanned a color strip 660 with the last flip-flop stage of the shift register. The last-mentioned signal, while the other input with one is inverted by an inverter 325.
Klimme662 is connected, to which the "fade-out" It can thus be determined when the blocking signal from the memory synchronization sensor 62 has crossed the label 26. The data unit 136 (Fig. 4) is created. Whenever it is possible to scan at a speed, the linkage conditions for the NAND element are not less than five milliseconds per bit. 300 are satisfied, the data stored in register 280 can be. With some practice, the operator can scroll around the stored data. Meet the requirements without difficulty. The on

Label detection circuit (Fig. 8) * ^{5 NA} . ⁿ⁵ ' '' ^lied ^ ² J are applied "measure 5" signals

⁰ & ν & / _so that all levels of the payer 310 are inside

A NAND gate 306 in Fig. 8 generates one half of seven milliseconds after the reset "Reset signal 310", which is switched to its "^" state via line 621 on counter 310 Reset input of a counter 310 is applied. the one from which they were to-Das The "warning signal" is sent back via a terminal 670 30. If during these seven to the first input of a NAND gate 312. The milliseconds no new data bit was sampled, Terminal 670 is connected to the output of the NAND-Glie- ', a "(!" Signal appears at the output of a NAND-des229 (Fig. 6B) connected. The "clock-3" signal element 311, its inputs with the outputs reaches the second input of the counter 310 via a terminal 672. The NAND element output of the NAND gate 312. The generated in this 35 311 generates a "transmission end signal" which is transmitted via th output signals reach an inverter 313 via an inverter to an output terminal 682 at-314 on a line 674. This line is placed in each case.

with the first input of a NAND gate group. The output of the inverter 325 is connected to the in-316 tied together. Of these logic gates connected to a NAND gate 326 whose is the second input with the output of a 40 second input with the Q output of a flip-flop Stage of counter 310 while its output 684 is connected. The flip-flop 328 generates outputs each with an input of a counter 318 output 684 a control signal that occurs after a are connected. The first color strip is scanned by the NAND elements 316. The K input that occur at the outputs of the counter 310 - this flip-top is connected to ground. being the signals are inverted if at the output of the NAND 45 J input is not occupied. To the clock input Element 312 a "(!" Signal occurs. The "data signal" is sent via a terminal 686)

Applied to the first input of a NAND gate 320, which comes from terminal 610 in Fig. 6B,

a »clock-5« signal is sent via a terminal 676 to the C input via a terminal 688 the

placed. The pulse repetition frequency of this "word transfer signal" signal from the control unit

is smaller than that of "Bar 1" and "Bar 3" - 50 142 (Fig. Ί).

Signal. For example, it can be increased by a factor of four be smaller. If the second input of the NAND terminal 688 takes the level “0”, the flip element is activated 320 the »value flop 328 is deleted via a terminal 678 and appears at its Q output! Transmission signal «from the control unit 142 a» (! «Signal. If a» 1 «at terminal 688 · (Fig. 4) applied. If there is also a »1« at the output of the NAND 55 signal and at terminal 686 · Element 320 a "(!" Signal occurs, if the value signal occurs, the flip-flop 328 is set, whereby of the counter 310 is increased by one each time. A "1" signal is produced at the (! output. If the

A "clock 6" signal is applied to the NAND gate 32 (

; applied to a logic element 322, which is also fulfilled, a signal is sent to the input one:

60 NAND gate 330 supplied by the control unit 142 (FIG. 4). To an input terminal 69f

On the other hand, the "Wertüncrlragimgssignal" is applied to the second, the "label end signal" sent by the

Input terminal 678 applied. The pulse re-control unit 142 (Fig. 4) is generated. If on ¹

The fetching frequency of the “clock 6” signal is in turn the output of the NAND element 326 a “0” signal and

less than the pulse repetition frequency at which a "1" signal occurs at the input of terminal 690

"Measure 5" signal. You can, for example, around 65 so the NAND gate 330 is set, and at his

Be smaller by a factor of five. The "bar 2" and "bar output" produces a "!" Signal. The NAND Gliec

4 "signals are switched to the" (! "State for the metal oxide half-metal 332)

The existing memory register 134 (Fig. 4) and the output terminal 692 are created because:

»End of label signal« with a »1« level. The generation of the "label end signal" will be described in detail later described.

Memory input synchronizing unit (Figs. 9 and 12)

The “value transfer signal” is applied from the control unit 142 (FIG. 4) to the first input of a NAND element 334 via a terminal 700. The "program counter reset signal" is applied to its second input via a terminal 702. The output of the NAND gate 334 is connected to the input of a NAND gate 338 via an inverter 336. The latter is cross-coupled to a NAND gate 340 and thereby forms a blocking circuit. In addition, the output of inverter 336 is connected to the reset input of an A counter 352. At the output of the NAND gate 340, a »data slide-

Terminal 642 (FIG. 7) is coupled to which a "shift signal A" is applied by the NAND gate 292. If the link condition for the element 356 is met, a “0” signal is generated at its output, which is inverted by the inverter 358 into a “!” Signal and is applied to the value increase input of the A counter 352 via a line 720 . If a "1" signal is applied to this input, the count value of this counter is increased by one. A decoding circuit 360 is also connected to the A counter 352 and generates a "1" signal at a terminal 722 when the A counter 352 has a count value that is not equal to zero. This indicates that there is only the last data bit in the input register 128. A conventional comparison circuit 362 is connected to the A counter 352 and via a terminal 728 to the program counter 400 (FIG. 13). The comparison circuit 362 generates at the terminal 726

signal «, which is taken at terminal 706 L '; a signal when the two counters mentioned can. At the output of the NAND gate 338, have the same value.

The output terminal 726 of the comparison circuit arises

is connected to a terminal 7 08, the "data send signal" is generated. The Λ counter 352 is

tert, which is applied to output terminal 710 as a "data shift pulse". Terminal 710 is connected to the auxiliary storage register 132 which is shown in detail in FIG.

The "clock 1" signal is sent to a NAND gate 346 via a first terminal 712 via a terminal 714 the "fade-out inhibition signal" generated by a NAND gate 350 (FIG. 10), and

The output terminal 726 of the (Fig. 9) is connected to the first via a terminal 740

reset when an input of a NAND gate 377 is connected to the output of inverter 336. A "0" signal occurs. This occurs when the logic operation is 25 second input with the output of a NAND condition for the link 334 is not fulfilled. Link 350, which prevents a “fade-out”

The output of the NAND gate 340 is generated with the approximate signal «. Connected to a third input, first input of a NAND gate 342, terminal 742, the "program counting signal DEKJ" is applied to its second input via a terminal 704 that is generated by counter 400 (FIG. 13). Applied to "measure 3" signal. The output of 30 an input terminal 744 becomes the “clock 1” signal NAND element 342 is also applied via an inverter 344. The program counter 400 in FIG. 13 is connected to one of the output terminals 710. If a "1" signal occurs at the output of the NAND element 340 at the output of the seven-stage binary counter, which can count up to 128, and at the input of the The last four stages of this counter are each terminal 704, the result is DEFG stages. The signal applied to the terminal 742 at the output of the NAND gate 342 is a "(!" Signal, 35) is a time signal that occurs when the program counter 400 converts a "1" signal into a "1" signal between

120 and 127. The NAND gate 377 generates thus a "1" signal if the link condition is not met at its inputs. Two NAND gates 368 and 370 (FIG. 10) are cross-coupled to one another and form one Trap circuit. The output of the NAND gate 377 is connected to the first input of the NAND gate 368, when the logic link 368 is in its

A Λ-8 signal 45 is saturated at the third input terminal 716 and the logic element 370 in its state opened by the /! counter 352 is applied to a "0" signal, which is connected. The A counter 352 is a "shift lock signal" is referred to, on the 4-bit counter that counts generates the number of "Λ-displacements line 746 and applied to an input gene" represented by a NA ND gate 292 (Fig. 7) of a logic element 368 and at the reset are generated when the "data shift signal" 50 input of a three-stage binary counter 378. An assumes the logic level "1". A conventional circuit is used as the decoding circuit counting input of this counter via a terminal 354, and 754 the "clock 3" signals are applied. If a "1" signal is applied to the output terminal 724 of the reset input, a "0" signal is generated when the count value eight in the A counter 352, the counter 378 is reset again. The exit is enough. This indicates that the first 55 of the NAND gate 368 is connected to the input of a bit entered into the input register 280 in the NAND gate 366, at the second eighth stage of which. Input via a terminal 748 also the »clock

The NAND gate 346 generates a "0" signal, 3 "signal is applied. If the »slide lockwenn three "1" signals simultaneously "0" at its input occurs at the output tig concern. If at the output of the inverter 336 60 of the NAND gate 366 a signal with the level "1". If a "1" signal is present at the same time, the 5 output of a flip-flop 380 is connected to the

NAND gate 340 is connected to its "1" state, the first input of a NAND gate 382 is connected, and the NAND gate 338 is connected to its "0" state. The second input of this via terminal 750 with This creates a "data shift signal" at the output of a NAND element 382 in the control unit 142 of the NAND element 340 be received with the receipt of a. J- and / (- input of the flip-flop NAND gate 356 connected, the second input of which is not occupied

α e η d

rn n,
lit
12th

e « ps ie r

tied together. The "TakT!""Signals are applied to the C input via a terminal 752. The Flipllop 380 remains in its deleted state until the" Takl-2 "signal takes on the value" I "and the last one Stage of the counter 378 also has the value "1." The counter 378 is reset when the "shift prevention signal" has the level "0." The (T output of the flip-flop 38 (1 has the level> 1 <- if the flip flop is in its deleted state. If the "value transfer signal" has the level "1" at the same time, a "(!" If a “(!” signal is present at the output of the NAND element 377 at the same time, the NAND element 370 can be in its “0” state and the NAND element 368 in its -I "state. The" shift change signal "will assume the level" I. "When a" clock 3 "signal occurs, the output of a NAND gate 366 a "0" signal is generated. After eight "Takl-3" signals, which are also applied to terminal 754 of counter 378, the last stage of this counter takes on the value "! <". These are set to "(!" From the output of NAND gate 746 via the reset input. A "(!" Signal occurs at output ~ Q , which also results in a "(!" Signal at the output of inverter 384) . The latter resets the counter 378 to "0".

The output of the inverter 384 is connected to the first input of a NAND gate 348 , which is cross-connected to a NAND gate 350 and forms a blocking circuit. The signal produced at the output of the NAND gate 350 is called the "fade-out prevention signal" and can be attacked at terminal 762. The output of the NAND gate 548 accordingly produces the “fade-out prevention signal”, which can be tapped at the output terminal 764. The NAND gate 384 is switched to the "()" and the NAND gate 350 is switched to the "!" State if the inverter 384 sends a "!" Signal and the NAND gate 386 a "0" Signal is generated. The “program counter signal”, which is generated by the program control unit, is applied to the NAND element 386 via a terminal 756. The "clock 1" signal is applied to a terminal 758 , while a signal that is not "0" is applied to an input terminal 760, which is connected to terminal 722 of the decoding circuit 360 (FIG. 9) . If the program counter has a value of 120, the NAND gate 386 generates the time of the "clock 1" signal to the last data bit in Eingancsregister 280 is stored, a signal of level "0". A "fade-out prevention" signal "with the level" 1 "appears at terminal 762 if a"! "Signal is present at the output of inverter 384.

The NAND gate 364 has a first input terminal 766 which is connected to an output terminal 636 of a NAND gate 278 (FIG. 7), from which a "blanking signal" is generated. The "label signal" is applied to a second input terminal 768 of the NAND gate 364 from an output terminal 692 (FIG. 8). The outputs of the NAND gate 364 and 366 are at the input of a NAND gate 372. At the output of this NAND gate a "!" Signal is generated when either the NAND gate 364 or the NAND gate 366 a "(!" The output of the NAND gate 372 is connected to the value increasing input of a three-stage binary counter 374.

Whenever a "1" signal is applied to this input, the counter 374 increments its counter each time. At this time, the inverter 384 generates a "1" signal each time.

The (7 output of a flipllop 376 is connected to the

ίο input of an inverter 337 connected. A “program counter reset signal” is generated at the output of the latter and is sent to an output terminal 770 . The ./ and Λ inputs of the flip-flop are not occupied, while the "clock!" signal is applied to the I / O input via a terminal 772. The flip-flop 376 remains in the cleared state until the last stage of the counter 374 is switched to the "1" state. When the counter 374 receives eight counting pulses, a "!" Signal is generated at its output, which is fed to the flip-flop 376. This signal sets the flip-flop, so that a "1" signal is produced at its (^ output, which is applied as a "(!" Signal via terminal 770 to counter 400 (FIG. 13), whereby the counter 400 is reset.

If the “Elikeltendcsignal” and the “Datenausblcndsignal” have the level “1”, a “0 *” signal is produced at the output of the NAND gate 364. It is possible that an erroneous "label end signal" is generated when the stylus 62 is guided over a container that is present as an object of sale, or when a label is scanned which is on! is arranged in a vehicle. The "0" signal arr output of the NAND gate 364 indicates that a "label end condition" has been scanned by the stylus 62 and that the "data fade-out signal" also has the value "1". When a label end signal «has been scanned, the output is generated. of inverter 384 a "0" signal, since the "value transfer signal!" at terminal 382 has the value "0". The "fade-out prevention signal" arr output of the NAND gate 348 has a level of "1".

The output of the Verknüpfungsgliedcs364 allows Eiiispcieherung new data in as ¹ input register 280 in Fig. 7 after a "Elikeltendesignal" has been generated (or, if an "end of media signal" is generated when scanning a record carrier other). As a result, no data can be lost if a "label end signal" is generated. B. occurs too early or is caused by another error. Data entered into register 280 after the occurrence of the "end of label signal" circulates in register 280 and is combined with the data entered previously. The combined data is checked when a second "label designal" is generated to determine whether the first was a value signal.

Storage unit (Fig. 11)

The first stage of a 5-bit auxiliary register 132 ii F i g. 11 receives 782 "data signals" and "data signals" via input terminals 780 , which are supplied by the output stages of register 280 in FIG. 7 via output terminals 657 and 659. The "data shift signal" from a terminal 710 " ii Fig. 9 causes the shift in the auxiliary

788 a
394 a
guided
Limb
390

register 132 stored data in the direction of the output stage. This pulse is applied to shift input 784. This is generated by inverter 344 in FIG. When the auxiliary storage register NtLT 132 is filled with data and an "I" signal occurs at the last stage, this is sent to the first input of a NAND gate 390. At the second input of this NAND element, the "data slide signal" is unselected via an input terminal 786, which is also sent by the NAND element 340 via the output terminal 706 in FIG. 9 is delivered. If the two signals are present at the input of the NAND element 3 ¹ JO, an "O" signal appears at its output.

The "data shift signal" is applied to the first input of a NA ND element 394 via a terminal 788, which is transmitted from the NAND element 338 via the output terminal 708 in FIG. 9 is delivered. The second input of this NAND gate is connected to the last stage of the storage register 134, which is also applied to the output terminal 790. If a "!" Bit is stored at the last level of the memory register 134 and the "!" Signal is applied to the terminal, the NAND element generates the "(!" Signal, which is sent to a NAND element 392. The second The input of this NAND gate is connected to the output of the NAND gate The output of the NAND gate 392 is controlled by the NAND gate 390 when new data are entered into the memory register 134 and by the NAND gate 394 when the data previously entered into the memory register 134 circulate therein.

The output of the NAND gate 392 is connected to the input of the register 134, in each time a bit can be entered if a "1" signal occurs at the output of the NAND gate 392. Conventional converter circles can be used for the storage register which convert the input and output signals into desired logic signals can turn back.

Comparison unit (Fig. 12)

The comparison unit in FIG. 12 accomplishes two tasks. First, the bits stored in the auxiliary storage register 132 (FIG. II) with the shifted and inverted count in the last four stages of the program counter 400 in FIG. 13 compared. The program counter 400 is a 7-bit module 128 counter. Strictly speaking, it consists of a modulo 8 and a modulo 16 counter, the modulo 8 counter from the first three stages or the A, B and C stages and the modulo 16 counter from the last four levels or the D, E, F and G levels. The value in the auxiliary memory 132 and the value in the modulo-16-digit part of the program counter 4UC are compared in order to be able to carry out the data from the memory register 134 into the output register 148 at a specific time.

As an example, assume that the currently stored section of information has the value 1011, which represents the decimal number eleven. Since it can be assumed that any information in can represent two values in a section is represented by the code section 1011 mentioned as an example practically 22 digits of four bits each, making a total of 88 bits. In addition to the 88 information bits there are twelve more iSiis in the label shown as an example in decoder form recorded. These consist of eight "code section bits", two RichUings bits and two Parile bits. The total of those recorded on the Elikeli Bits is thus 100. Of these K) OBiIs five bits are stored in auxiliary storage register 132 and 95 bits in storage register 134.

Around the crsic sampled bit being decoded is to bring into the output stage of the storage register 134, must be located in the memory Data towards the output stage of the storage register 134 shifted pastures. The shift must take place via '2S minus 95 33 digits, after that the program counter 4 (10 was reset. Every time the data in memory 130 shifted eight stages toward the output stage of storage register 134, will the modulo 16 part of program counter 4 (! 0 um the word "l" increased. After the information has been shifted by 32 places, the modulo 16 counter part the position 0010 on.

The Weil contained in the modulo-16 counter part of the program counter 400 represents the shifted and inverted value of the "Inloimalionabschnittes" located in the auxiliary storage register 132. By comparing the D, E, I and G columns of the program counter located value with the shifted and inverted value of the auxiliary storage

cherregister 132 stored "information section" becomes the line for the transfer of the data from the storage register 134 to the output register 148 established. In the present example this transmission begins after 33 bit lines.

In the example described here it is not a problem that the logic leads by one bit each time when the data is transferred from the output register 148 in the data processing system 114 the first BiI is ignored in each case.

The first five bits that are transferred into the output register 148 constitute the first group an "information section" read from the label 20. The last five bits which are entered into the auxiliary storage register 132 are those from the second "information section" sampled values.

The comparison unit in Fig. 12 then compares the information stored in the Hill memory register 132 with that in the output register 148.

The outputs from the NAND gates 101, 103, 105, 107 and 109 in FIG. 12 are connected to the inputs of a NAND gate 111. This generates an output signal with the level "0" if only "1" signals are present at its input. The output of the NAND gate 111 is connected to an inverter 113 which generates a comparison signal with the level “1” which is applied to the output terminal 800.
The outputs of the NAND elements 115, 117, 119 and 121 are connected to the inputs of a NAND element 101. At the first input of the NAND element 115, a "wrong side" signal from stage B is transmitted via a terminal 802 - The auxiliary storage register 132 is applied. This “entrance is with

»/I.A. Stage ?? ”. To the second input terminal 804 from stage G of program counter 400 of FIG. 13 a "false page a" signal is asserted. This is with "P.C. Stage G ~ «. With

a third input terminal 806 is the control unit 142 of I · 'i g. 4 connected, which delivers a "/ ^" signal. This signal is a clock signal that occurs if the one in the counter 400 matches the one in the IiIIsspeicherregister 132 is to be compared.

Λ η the inputs 808 and 81 »of a NAND gate 117 is the» correct side signal from the port B of the auxiliary storage register 132 and the »correct ropes« signal from the stage (V of the Pragninim- / UIiIl ¹ P. 400. At the third input there is also the signal "/: '". The condition function for this NAND element can be recognized from the explanations given above Program / counter 4CO are the same and the "/!" Signal is present, the NAND gates 101, 103, 105 and 1 (17 generate a "!" Signal.

The information stored in the auxiliary storage register 132 is shifted as a function of the information stored in the output register 148. In this way, as described above, the scanning direction read label is taken into account. The signal "correct page" obtained from stage B of the auxiliary storage register 132 is applied to the NAND element 119 via the input terminal 808, and the signal "incorrect page" derived from stage 1 of the output register 148 is applied to the input terminal 812 . The signal derived from the output .les register 148 is called "OK Siufen-D-Signal". The "false scite" signal from stage B of Hill's storage register 132 is njjelegl via terminal 802 to NAND element 121. The correct page signal from stage D read output register 142 occurs at terminal 814:; uf. A “/ -” signal is applied to terminal 816 on NAND gates 119 and 121. This signal '■■'. a time signal that appears when the values stored in the HiIIs- ^ j'eieherregister 132 are to be compared with those in the output register 148. If the values stored in the auxiliary storage register 132 and in the output register 148 are the same, if the "Fe signal is present," a "!" Signal occurs at the outputs of the NAND gates 101, 103, 105 and 107.

The "F" signal! Is also applied to a NAND element 109 via a terminal "18". The second and third inputs of this NAND element are connected to the outputs of the NAND elements 123 and 125 the NAND gate 123 applied a "correct page" signal from stage A of auxiliary storage register 132, and applied to terminal 822 the "false page" signal from stage E of auxiliary storage register 142. To terminals 824 and 826 of the NAND Gate 125 is applied with a "wrong page" signal from stage A of auxiliary storage register 132 and a "correct page K" signal from stage E of output register 142. Stage A of auxiliary storage register 132 and stage E of output register 142 hold As can be seen from Fig. I, the two direction bits have the same logical value, depending on whether they represent a “start bit” or a “stop bit.” Both “direction bits” must either be “1” or “ O "bits. That is why there will be an output g of the NAND gate 123 or 125 have a "0" signal and the output of the NAND gate 121 has a "!" signal, since both directions have the same logic level.

If the direction bits do not have the same logical value, both output

gen of NAND gates 123 and 125 a "!" signal if the "/" signal at terminal 818 is Has the value "I" and the value "ü" at the output of the NAND gate 109. A comparison signal with the Value "0" is generated by inverter 114 when

ίο the direction bits are different, ie when they have an opposite logic level. The direction bit which is stored in the auxiliary memory register 132 is stored in stage A of this register. The code weight of the in this

Register inverted bits present increases in direction B, C, D. The direction bit in the output register 148 is stored in the '/j.'- step of this register. The code weight also increases in this register in the direction of levels ü, C, B and A.

if from.

Program counter unit (Fig. 13)

The program counter 400 in FIG. 13 is connected to the output of an inv. At the entrance

“Clock 3” is applied via a terminal 130 to the inverter's output. The program counter 400 increases its value every time a "(!" signal occurs at the output of inverter 404. The output of the Inverter 337 is connected to the output terminal 770 in

Fig.lt) connected to the input terminal 132, which represents the reset input of the counter 400 and this when a "0" signal occurs at this Resets the terminal.

406 to 422 are conventional decoding circuits,

which evaluate the count of the program counter 440. A "1" signal occurs at the individual outputs of the decoding circuits 406 to 422 whenever the counter 400 has a certain count value. The decoding circuit 422 decodes the D, E,

F and (7 stages of the program counter 400 to generate a "program counter signal D, E, F, G" which indicates that all stages of the program counter 400 are in the "I" state. The decoding circuits 412, 414, 416, 418 and 420 are the Slu-

fen / 4, B and C , and the decoding circuits 406, 408, 410 and 422 are assigned to all stages of the program counter 400.

Parity check unit (Fig. 14)

y. By interconnecting flip-flops 440 and 442 in FIG. 14, a conventional modulo-3 counter is formed. The “increment 0 signal” is applied to the clock signal inputs of the two flip-flops via a terminal 840. A parity reset signal

with the level "0" is applied via an input terminal 842 to the reset inputs of the two flip-flops, which is controlled by the control unit 142 of FIG. 4 is delivered. The flip-flop 440 has a code weight "1" and the flip-flop 442 a code weight "2"

assigned. The two flip-flops can never be set to the same state at the same time, since the reset is carried out each time the count value two occurs. A “preselection signal 0” arrives at an input terminal 844

the flip-flop 442 and brings this into the set state if a parity check is to be carried out and if the data in the auxiliary storage register 132 and in the output register 148 are the

3014

have the same value. 448 is a conventional comparison circuit, e.g. a "1" signal is generated when a "Ü" signal is applied to input terminal 848 and the flipfiops 440 and and 442 have the same count as flip-flops 444 and 446. The flipfiops 444 and 446 are working in the same way as flip-flops 440 and 442. This is applied to terminals 848 and 850 Value increase signal »1« and the presetting signal »1« applied. The flip flop 442 is set in advance, if the "first direction bit" or the "start bit" was recognized as a "Ü" bit, and the flip-flop 446 is preset when the "first direction bit" was recognized as a "!" Bit. The flip-flops 444 and 446 are reset by the reset signal appearing at terminal 852.

Output register (Figs. 15A and 15B)

The complete block diagram of the output register 148 is shown by combining the FIGS. 15 A and 15B along line 15-15.

The data are transferred from the storage register 134 to the output register 148. The data can depending on the scanned and recognized information in the output register can be entered. Depending on whether the label is from the hand-held scanning style 62 in forward or is scanned in the reverse direction, the data entered in the output register 148 represents on the one hand the regular and on the other hand the supplementary ones Values of the recorded information. Therefore, the data becomes dependent the scanning direction when transferring from output register 148 to the data processing station 114 (Fig. 2) shifted in either a forward or a reverse direction.

The output stage of memory register 134 in FIG. 11 produces a "memory output" which is via a terminal 790 to the input terminal 860 of a NAND element 424 in FIG. 15 A is applied. The "register forward signal" is sent by the control unit 142 in FIG. 4 and applied to the second input 862 of the NAND gate 424. At a NAND gate 426 is also generated by the control unit 142 via a terminal 864 "Register backward signal" is applied, which has the value "ü", when the "register forward signal" the Has the value "1". Thus, the outputs of NAND gates 424 and 426 are opposite each other and both are at the inputs of a NAND gate 428. By a "0" signal from the storage register 134 a "0" signal is generated at the output of the NAND gate 428. A "1" signal from the output of the storage register 134 generates a "1" signal at the output of the NAND gate 428 when data is in the Output register 148 can be entered.

The output of the NAND gate 428 is fed via an inverter 430 to the K input of a flipllopslufc 432 created. The / input of the flipllop is directly connected to the output of the NAND gate 428 tied together. The clock input receives the "register clock signal" via a terminal 866, the is generated by the control unit 142. If a "(!" Signal from memory register 134 to the first At the input of a NAND gate 424, a "!" Signal is applied as the "regulator clock signal" at the same time is present, the flip flop 432 is deleted. If on the other hand a at the output of the memory register 134 "!" Signal occurs, the NAND gate 428 will generate a "!" Signal, whereby the "register read signal · »Is present at the same time, the Flip Flop 432 is set. This results in a cntspad.ci, -des at the Q output Signal on.

The remaining seven stages of the output register are constructed in the same way. In that thereby The shift registers formed can transfer the leveled data in the direction of the flip-flop stage 441 be pushed away. The last flip-flop stage 441 has only a NAND gate, as a NAND gate to initiate a data shift in backward resolution is not necessary, because the information entered in this stage can only be forwarded be moved.

The first input of a NAND element 434 in FIG. 15U is connected to the y output "of the flip-flop ₄₄ , in _honor of its second input for a clamp 862 there". "Ro" ister-Vor \\; iiis-Signal "is applied. The (J output of the flip-flop stage 432 is connected to the first input of an N \ ND element 436. The "register backward signal" is applied to the second input of this NAND element. The outputs of the NAND elements 434 and 436 are connected to the inputs of a NAND gate 438. At the output terminal 868 there is a »data output signal« with the level »!« if either at the output cL-s NAND gate 434 or at the output of the NAND gate 436 a »0« This output signal is fed to the data processing unit 114 in FIG.

When the "register forward signal" hits the pcgel "1" and the "register backward signal" has the level "0", data is transferred from the output register 148 supplied to the data processing device 114. This is done by the data in the output register from flip-flop 432 in the direction of be shifted to the flip-flop 441. The value stored in the flipflop 441 becomes the initial state of the NAND gate 434 is determined, whereby it is determined 00 at the output of the NAND gate 438 a "0" signal or a "1" signal is generated. When the stylus 62 hits the label 20 in Has traversed backward direction, the data from output register 148 must go into the data processing device 114 are transmitted in reverse order. That is why the "register backward signal" the level "1" and the "register forward signal" the level »0«. This removes the data stored in the output register 148 from the flip-hop stage 441 in the direction of the flip-flop stage 432. At that moment, he determines State of the flip-flop 432 the output state of the NAND gate 436, and thus the output state of the NAND gate 438. Thus, at the terminal of the flip-flop 432 the complement of the information read in the reverse direction can be taken. Through the

Connection with the (7 output, the complement is automatically formed during the transfer.

Control unit (Fig. 16 and 17)

With the first input terminal of a NAND element 502 in Figure 16 is the output of the inverter 337 via an output terminal 770 in Fig. 10 connected. The latter generates the »program / iihlerrüekselzignal. At the / while going is over

a clip 882 of FIG. 8 the »label end signal« applied. If there are “!” Signals at both inputs, the NAND element 505 generates a “(!” Signal, which is sent as a “parity reset signal” to output 884. The first input of a NAND element 504 is connected to an input terminal 886 applied from the decoding circuit 416 in F i g. 13, the "program counter signal 7 ', while the" Vergleiehssignal "is applied to the second input via a terminal 888 from the output terminal 800 in Fig. 12. at the output of the NAND gate 504 is to Beginning with a "!" Signal generated since the "comparison signal" from inverter 113 has the level "ü" that either the "E" signal or the "/ ·""signal from the control unit 142 in FIG. 4 has the level »1«, which also achieves the desired comparison. The »E« signal assumes a level »1« earlier than the »/ - '« signal Has assumed level “1”, the bit located in the auxiliary storage register 132 and the count value of the program counter 40 are set in the comparison circuit in FIG 0 in order to control the transfer of the data from the storage register 134 to the output register 148 in the manner previously described.

Hin NAND gate 506 is cross-coupled to a NAND gate 508 , whereby a trap circuit is formed. The first input of the NAND gate: 506 is connected to the output of the NAND gate 502 . The second input of the NAND gate 5G8 is connected to the output of the NAND gate 504 , while the first input is connected via a terminal 890 to the output of the inverter 510 in FIG. The "transmission world signal" arrives at this input. This signal initially has the level "1". And at the output of NAND gate 504 is at the beginning of a "" - signal ei / EUGT as the "comparison signal '' to the terminal 888 at this time a" (- has level Now, if the output of the NAND gate!. 502 has a “(!” Signal at the same time, the parity counter flip-flops 440 to 446 in FIG. 14 are reset, and the NAND gate 508 is in the “(!” State and the NAND gate 506 is in the “1 "Status set. The" E "output signal at a terminal 892 now has a"! "Signal.

If the "Werl transmission signal" to "(" - level thought to have been the sampled decoded and recognized as value data Now, if at the same time at the input terminal 888, the "Vergleiehssignal" and at the input terminal 896, the "program counter 7 signal" level ". 1 ”, a“ (! ”Signal occurs at the output of NAND element 504 , and if the“ program counter reset signal ”at terminal 880 also has a“ (! ”Level) at the output of NAND element 502 This sets the NAND element 506 to the “(!” state and the NAND element 508 to the “1” state, whereby the “E” signal at the output terminal 892 is set to the level "0" takes. with the first input of a NAND gate the output of the NAND gate 506 is also connected. to the second input of this gate is the Fig generated and the NAND gate 152 (to the output terminals via the iMutimc 894th 12 ) applied »comparison signal« is applied to the third input via the hang terminal mc 896 the "program counter 6 signal" generated by the decoder circuit 614 in FIG. 13 is applied. Thus, when the program counter 400 reaches the count six, the "£" signal at terminal 892 and the "compare signal" at terminal 894 each have a "1" level, the NAND element 512 can have a "(!" - Generate signal.

A NAND gate 514 is cross-connected to a NAND gate 516 , - whereby a trap circuit is formed. The “program counter signal” ÜÜÖ generated by the decoding circuit 406 in FIG. 13 is applied to the input of the NAND element 516 via a terminal 898. If the program counter 400 is not reset, the "clock 3" signal with a "1" level is applied to the input terminal of the NAND gate 516 from the decoding circuit 406. A "(!" Signal is applied to the input of the NAND gate 514 from the output of the NAND gate 512 if the "E" signal and the "compare signal" both have an "O" level and if the program counter 400 has the count value 6. This sets the NAND gate 516 to the “(!” state and the NAND gate 514 to the “!” state, whereby a “!” signal appears at the output terminal 900. The output of NAND gate 514 is connected to the inputs of NAND gates 518 and 520. The "clock 1" signal also reaches the two NAND gates via input terminal 902. Another input of NAND gate 518 is connected to the output of an inverter 522. The “program counter signal 1” generated in the decoding circuit 412 in Fig. 13 is applied to a further input of the NAND element 520 via a terminal 904. The “parity lock signal” at the output of the NAND element 514 remains on its "1" level until the "program counter signal" ööö a level "0" and the signal at the output of the NAND gate 512 simultaneously assumes a level "1".

A NAND gate 524 is cross-coupled to a NAND gate 544 , whereby a trap circuit is formed. The output of the NAND gate 534 is connected to the input of the NAND gate 524 . Another input of the NAND element 526 is connected via a terminal 906 to the data processing unit 114 in FIG. 2, which applies a “general reset signal” to this input. At the beginning, before a label is scanned, the NAND gate 524 is in a "0" state and the NAND gate 526 is in the "!" State. At the beginning there is thus a “coding comparison signal” with a “1” level at the output of the NAND gate 526 , which is sent to the line 908 . At the output of the NAND gate 524 , the corresponding inverted signal is produced, which is sent to the line 910 . The output of the NAND element 526 is connected to the first input of a NAND element 528. The “program counter 0 signal” generated by the decoding circuit 418 in FIG. 13 is applied to its second input via a terminal 928. The NAND gate 528 generates a "(!" Signal, which is inverted by an inverter 522 when the "Proj.'rammzähler-0-Signal" a "1" level and the NAND gate 518 also a signal The "program counter 1 signal" applied to the NAND gate 520 has a "()" level when the "program counter 0 signal" at the input of the NAND gate 528 has a "!"-Level

having. During this time, a “1” signal arises at the output of the NAND gate 520.

A NAND gate 530 is cross-coupled to a NAND gate 532, creating a trap circuit is formed. The output of the NAND element 518 is connected to the first input of the NAND element 530 tied together. The output of the NAND gate 520 is coupled to an input of the NAND gate 532. Thus "there is a connection between the inverter 510 in Fig. 17 through an input terminal 914 with the NAND gate 532, to which the "value transfer signal" is applied. If this signai has an “I” level and the NAND gate 520 generates a “0” signal and an “O” signal is also applied to the input terminal 914, the NAND gate 532 is set to the "(!" state. At the same time, the NAND gate 530 is set to the "1" status is set, resulting in a "/ ·" signal at output terminal 916.

A "comparison signal" is applied to the NAND gate 534 via a terminal 918, which is generated by the inverter 113 in FIG "/ -""signal has a"! "Level. The""fact-3" signal is applied to NAND gate 534 via input terminal 920. Another input of this NAND element is connected to the output of the NAND element 530. Since the “general reset signal” at terminal 906 has a “1” level at the beginning, NAND element 526 is set to “0” state and NAND element 524 to “!” State. Aul the line 910 a "Codiervergleichssignal" arises with the level "1".

The output of the NAND gate 524 is connected to the input of a NAND gate 527, the has a second input to which the "Parilats comparison signal" from the ;? balanced circuit 448 in FIG. 14 is applied. If the The linkage condition for a NAND element 527 is fulfilled, a "(!" Signal is generated at its output, which arrives on line 924 as a “data incorrect signal”. At the same time it is sent to an inverter 531, which generates a “data correct signal · · with the level“ I ”, which reaches the line 926.

The output of the inverter 531 is connected to the first input of a NAND gate 533. At the second input of this NAND element is applied to the "program counter signal" 127, which is generated by the decoding circuit 408 in FIG. 13 is generated. The "measure 3" signal is sent to the fourth input. If on If a "!" Signal occurs at the output of inverter 531, a "parity lock signal" is generated at the output of NAND gate 533 generated, which has the level »1« and which is transmitted via a terminal 932 as a »Datcnkorn-ktsignal« to an input terminal 934 of a NAND gate 535 in FIG. 17 is created.

The NAND gate 535 is cross-coupled to the NAND gate 536, whereby a trap circuit ⁶ <> is formed. The “general reset signal” from the data processing unit 114 is fed to the NAND element 536 via a terminal 938. If this has the level “I”, the NAND gate 536 is switched to the “(!” State and the NAND gate 535 to the “1” state At the output of the NAND gate 535 there is a "1" signal, which is fed as a "data correct lock signal" to the output terminal 940. The output of the NAND gate 536 is connected to the input of a NAND gate 538 at the second input of which a 2-signal is applied by a flip-flop 546. If a "(!" signal is present at the output of the NAND element 536 and a "1" signal is present at the output of the NAND element 538) at the output of the inverter 510 a "(!" signal, which is fed as a "data value signal" to an input terminal 942. The "data value signal" can be taken from an input terminal 944 if data representing real values are sampled from the label 20. This signal prevents newly scanned data from entering the memory 130 can arrive when the previously scanned data still in memory 130 have been supplied to the data processing device in FIG.

The ^ input of flip-flop 546 in FIG. 17 is connected to ground. The »SchwarvsignaK is applied to the ./ input via a 946 terminal. This signal is used by the decoder unit 126 in FIG. 4 generated. The “white signal”, which is also supplied by the decoding unit 126, arrives at the delete input C via a terminal 948. The "end of transmission signal" from terminal 682 in FIG. 1 arrives at the clock input via a terminal 950. 8. When the first white color strip is scanned, a “white signal!” With the level “0” appears at input C of the flpllop 546. This signal clears flip-flop 546. When the scanning pen 62 is removed from a label 20 that has just been scanned, a "black signal" with the level "1" is applied via the input terminal 946 to the / input of the flip-flop 446. At the same time, "Transmission design.il" appears at terminal 950 at the clock input of the flip-flop, also with a level of "1". The flip-flop is set by these two signals. As a result, a “(!” Signal appears at the 0 output, which is fed to a NAND element 538. A “1” signal is produced at the output of this NAND element, which is converted by the inverter 510 into a “(!” Signal This signal is applied to terminal 942 as a »value transfer signal.

One of the Decodicreinheit 408 in Figure 13 is generated "program counter signal." - with the value hundcrtsicbcnundzwanzig (PC 127), is supplied via a Hingangsklemme 928 a NAND Glied542. The »cycle 3« signal is applied to a further input via a terminal 930. The third input receives the “parity lock signal” which is generated by the NAND gate 514. The "data incorrect signal" is also fed to the NAND gate 542 via the line 924. If this signal has the level "0", the NAND gate 542 generates a "1" signal. Since the “value transfer signal” at terminal 952 also has the level “1” at the beginning, a “(!” Signal appears at the output of the NAND gate 540 when data is scanned by the label 20. This signal is generated by an inverter 544 converted into a "!" Signal, that is, the "label reset signal" is applied to output terminal 954. If a "(!" Signal occurs at the output of NAND gate 542 and the "value transfer signal"

lor

t- η

shows the level "1" at the same time, there is also an "O" signal at output terminal 954 !. by indicating that the “label design; was an error signal. The "reset signal" is with terminal 690 in FIG. 8 connected.

The output of the NAND gate 526 is connected to an inverter 548, the output of which is in turn coupled to the input of a NAND gate 550. With the second input of this NAND element, a connection is established via terminal 916 to the first stage of the auxiliary storage register 132 in FIG. 11, through which the "direction bit" is transmitted. The "0" signal produced at the output of the NAND gate 526 is converted into a "1" signal by the inverter 548. If the »Richturgbit« has the level »1«, a »(k signal.

The NAND gate 552 is cross-connected to the NAND gate 554, whereby a trap circuit is formed. The output of the NAND element 550 is connected to the input of the NAND element 552. The "general reset signal" is fed to the NAND gate 554 via a terminal 958. If the “direction bit” and the “general reset signal” are present at the same time on the NAND element 554, this is set to the “(!” State and the NAND element 552 to the “!” State. Element 552 'produces an "anti-reverse signal" with level "1", which can be picked up at output terminal 960. 3 "A m output of N AND element 554 produces an anti-reverse signal" with level "0" which is sent to the output terminal 962 reaches When the "direction bit having" a "O" level, the NAND gate 552 is in the "()." - connected state, whereby the both the - and the NAND gate 554 in the "!" Signals occurring at terminals 960 and 962 change their level.

The "direction bit" is applied to an inverter 556 from the auxiliary storage register 132 in FIG. 11 via an input terminal 964. The output of the inverter 556 is connected to the first input of a NAND gate 558. The “comparison signal” from the output terminal 800 of FIG. 12 is applied to a further input of this NAND element via an input terminal 968. The result of the comparison between the value of the program counter 400 and the value stored in the auxiliary storage register 1132 is represented by this signal. A third input of this NAND element is connected to the dimming circuit 412 of FIG. 13 via an input cycle 970. This circle generates a »program counter 1 signal« (PC 1). The »/: <signal is applied to a fourth input terminal 966. If the value contained in the steps /), E, F and G of the program counter 400 is equal to the value stored in the auxiliary storage register 132 and the "direction bit" has a "(" level, the NAND gate 558 generates a " Preselection signal 0 «, which is sent to the output terminal 972.

The "direction signal" is sent from the auxiliary storage register 132 to the first input terminal of a NAND element 560. The same signals are sent to the other inputs of this NAND element via terminals 974, 976 and 978 as to the corresponding terminals of the NAND element 558. The sienals produced at the outputs 972 and 980 thus behave in a complementary manner to one another. if

the "direction bit" has the level "1", a "0" signal is produced at the output of the NAND element 560 and a "1" signal at the output of the NAND element 558. These two signals reach the inputs 850 and 844 of the flip-flops 442 and 446, by means of which the parity check of the memory unit 130 is carried out in the prescribed manner. An input terminal 982 is used to apply data to an inverter 562 from the storage register 134 in FIG. 11 via an output terminal 790 . The output of the inverter 562 is connected to the input of a NAND gate 566. To a further input of this NAND gate of the "clock-1 is applied" pulse through an input terminal 984th The input terminal 986 is connected to an output terminal 900 of FIG. 16 so that the "parity lock signal" can pass to the NAND gate 566. The input of a NAND gate 564 is connected to the output stage of the memory register 134 via a terminal 982. The second fingong of this NAND element receives the "clock 1" signal via input terminal 988. About a third input terminal 990 reaches that of the output terminal 900 in FIG. 16 next »Paritiitssperrsignal".

If a “0” bit is stored in the last stage of the memory register 134, the NAND element 564 generates a “!” Signal. At the same time, a "0" signal is produced at the output of the NAND gate 566 during the time of the "clock 1" signal when the "parity lock signal" has a "!" Level. If a "!" Bit is stored in the output stage of the memory register 134 , a "(!" Signal is generated at the output of the NAND element 664 and a "!" Signal at the output of the NAND element 566. The output of the NAND Element 564 is connected to the input of an inverter 568 and inverted by the signal generated at this NAND element, which is present at output terminal 992. This signal is called:> Increment 1 signal. "The output of NAND element 566 is connected to an inverter 570, which is a "Inkremcnt-u-signal" delivers to the output terminal 994th is connected via terminal 992 to the clock inputs of Flipllops 444 and 446, the output of the inverter 568th the output of Inverte.s 570 is over the output terminal 994 is connected to the clock inputs of the flip-flops 440 and 442 .

The output of the coding circuit 420 in FIG. 13 is connected to a NAND gate 572 via an input terminal 996, whereby the "program counter 0-5" is applied to it. This signal indicates that levels A, B and C of the program counter 400 have counted from zero to five. The “comparison signal” from the inverter 113 in FIG. 12 is applied to the second input of the NAND element 572 via a terminal 998. In the present case, this has a "!" Level if the one indicated by the D, / '. F and (7 of the program counter 400 interpolated values coincide with the values stored in the auxiliary storage register 132. The "E" signal from the output of the NAND element 506 in FIG. 16 is applied to the NAND gate 572 via an input terminal 1000. At the output of the NAND gate 572 thus produces an "O" signal when the "program counter signal 0-5" (PC 0-5) has a "(!" Level and a comparison between the D, E, F and G stages of the program counter and the in the auxiliary storage register 132 hefindlirhpn Wpi-tp

was performed, whereby a code section was transferred from the storage register 134 to the output register 138 . The output of the NAND gate 572 is connected to the input of a NAND gate 574 , which generates the "register forward signal" at the output terminal 1002.

A Eingangskiemmc 1004 573 the "Registcrladesignal" is applied from the data processing device 114 to the NAND gate. The “data correct interlocking signal” from the NAND element 535 via the output terminal 940 is applied to the same NAND element via a second input terminal 1006. At the output of the NAND element 573 there is a "0" signal and at the output of the NAND element 574 a "1" signal, which is called the "Registcr forward signal", when at the two inputs of the NAND element 573 a "1" signal is present. In this case, the D: "cn stored in the storage register 134 are transferred to the output register 148.

The "reverse blocking signal" is applied to the NAND gate 576 from the output terminal 962 of FIG. 16 via a terminal 1008. The data processing device 114 in FIG. 2 applies the “transmission signal” to a second input of this NAND element via an input terminal 1010. A third input of this element is connected via an input terminal 1012 to an output terminal 940 of the NAND element 535 , whereby the "data correct lock signal" is applied to it. If the output register 148 has been loaded correctly, the data processing device 114 supplies a transfer signal with the level "1" to the NAND gate 576 via the terminal 1010. If the "direction bit" is an "O" bit and the "reverse lock signal" at the Kicmmc 1008 has a level of “1”, a “0” signal is produced at the output of the NAND element 576 and a “Ιβ signal is produced at the output of the NAND element 573. The output of the NAND gate 962 in FIG. 16 is connected to a first input of the NAND gate 578 via a terminal 1014 , whereby the "reverse blocking signal" is applied to this NAND gate. A second input receives the “transmission signal” from the data processing device 104 via an input terminal 1016. The “data corrector signal” is also applied to the NAND element 578 via an input terminal 1018 from the NAND element 535 via an output terminal 940 . The output of the NAND gate 578 is connected to the input of an inverter 580 , which generates a "regulator reverse signal" at its output, the

ίο reaches the output terminal 1020.

If there is a "!" Signal at output terminal 1002. is applied and the "transfer signal" also has a logic level "1", the data stored in the output regulator 48 are transferred from the input flow in the direction of the output stage. If the "Rc register reverse signal" is present at output terminal 1020 and the "transmission signal" has the logic level "1" and the "data correction signal" is also present with a level "1", the values stored in the output register 148 are transferred from the output stage in Moved towards the entrance step. Thus, each of the data stored in the output register 148 can be moved in a left-to-right direction

or in a right-to-left direction, depending on the direction in which the stylus 62 is moved over the label 20 .

The output of the NAND element 574 is connected to the input of a NAND element 582 , the second input of which receives the "clock 1" signal via terminal 1022. The output of the inverter 580 is connected to an input of the NAND gate 584 , to its second input via the terminal. 1022 the "bar 1" signal is also applied. The outputs of the NAND gates 582 and 584 are connected to the inputs of a NAND gate 586. If both outputs of the NAND gates generate a "1" signal, a "Ü" signal is produced at the output of the NAND gate 586, the is applied to terminal 1024 . The output signal at terminal 1024 is called the "register clock signal" and is sent to the flip-flops of output register 148 in FIGS. 15A and 15B.

In addition 6 sheets of drawings

Claims (8)

Patent claims: 1. Device for serial optical scanning and evaluation of data which are represented by at least three different areas lying next to one another _; wherein each area in the scanning direction is different from each preceding area, and in which at least two photosensitive elements are provided, each responding to at least one type of area, characterized in that a video processing unit (115) in dependence on the sequence of the Photosensitive elements (102, 104) on two lines (108, 110 in Fig. 4) generated signals on at least one of at least three lines (120, 122, 124 in Fig. 4) a signal is generated, and that the sequence of the signals interprets the sequence of the ranges, each signal being stored in a decoding unit (126) until the next signal is generated, and this depends on the signals on the three lines (120, 122, 124 in Fig 4) first and second binary signals (L, 0) generated, with range transitions of a first sequence (1 to 2, 2 to 3, 3 to 1) each having a first binary signal (/. B. L) on a z wide sequence (1 to 3, 3 to 2, 2 to 1) a second binary signal (e.g. B. 0) is assigned, and that the binary signals (L, 0) are fed to a memory (130) from which they are stored depending on the scanning direction in a known manner in a first or second sequence, each binary signal ( L, 0) is inverted if the withdrawal is carried out in the second sequence. 2. Device according to claim 1, characterized in that the decoding unit (126) with one of the lines (120, 122, 124 in Fig. 4) connected to flip-flops (210, 214, 218 in Fig. 6A), each with the inputs of NAND gates 226, 238, 258, 262 in Fig. 6B) are connected and that the signals occurring at the latter are fed to the memory (130). 3. Apparatus according to claim 1, characterized in that a clock signal source (127 in FIG. 4) is provided, through whose clock signals a program counter (400) is stepped on, and that the memory (130) contains a memory register (134) , which has the same number of stages as the program counter (400) and is constructed as a circular shift register which is incremented by clock signals derived from the clock signal source (127 in FIG. 4) ;;. 4. Device according to claims 1 to 3, characterized in that a label end detection device (138) is provided which generates an output signal when all the data recorded on a label (20) have been scanned, and that a comparison (147) by an output signal of the label detection device (138) is caused to initiate a comparison, in which a section of information stored in the memory (130) is compared with a part of the program counter sequence and that, as a function of this comparison, the comparison unit (147) generates an output signal which causes the data stored in the storage register (134) to be transferred to an output register (148). 5. Apparatus according to claim 4, characterized in that the label end detection device (138) contains a first counter (310) which is incremented with pulses of a first frequency and that the label end detection device (138) has a second counter (318) which is acted upon with a second lower frequency, and that the content of the first counter (310) is transmitted as a complement to the second counter (318) as a function of a first detected range transition, and that the outputs of the stages of the second counter ( 318) are connected to a NAND gate (324) which controls the output signal generation of the label end detection device (138). 6. Device according to one of the preceding claims, characterized in that the output of the memory register (134) is connected to a parity check unit (146) which contains counters from flip-flops (440, 442, 444, 446) , which are constructed as follows for all binary "1" and for all binary "0" of a stored word a modulo 3 count is carried out, and that a comparison circuit (448) compares the corresponding count values of the said counters with one another. 7. Device according to one of the preceding claims, characterized in that the output signals of the NAND gates (226, 238, 258, 262 in Fig. 6B) are fed to an input register (128) which contains the memory (130) data in a sequence which is controlled by the clock signals generated by the clock signal source (127). 8. Apparatus according to claim 7, characterized in that a manually operable scanning lift (62) is provided for serial optical scanning, which can be guided over the label (20) and that a portion (78) is provided through which a light beam the label (20) is directed, and that a further section (80) is provided through which the light reflected from the label (20) is received and fed to the photosensitive elements (102, 104).