DE2032240A1 - Data sampling and decoding system - Google Patents

Description

THE NATIONAL CASH REGISTER COMPANY Dayton, Ohio (V.St.A.)

Patent application

Our Az: 1203 / Germany

DATA SCANNING AND DECODING SYSTEM

The invention relates to a data scanning and decoding system in which data is transmitted on a recording medium serially arranged different areas are displayed and in which this data is read by scanning the data carrier and decoded.

In known systems of the type mentioned above, the binary data are represented on a recording medium daduroh ^, that a first binary information by a first recognizable area and a second binary information is represented by a second recognizable area. The two recognizable areas are on the recording medium spaced from each other, whereby the recording medium section lying between these areas only for the. Clock signal recovery can be used, and thus as data transfer area is lost.

In the known systems, it is disadvantageous that the above intermediate areas are not used for information recording can be used so that for a particular to be transmitted information section a relatively large recording medium is required.

It is the object of the invention to provide a data sampling and decoding system which is used for the transmission of information manages with a smaller recording medium,

».6U970. 009884/1923

and in which the record carrier is in a first or can be scanned in a second opposite direction.

The invention is characterized in that each area in the scan direction of each preceding Area is different, and that every transition between the recognizable areas represents binary information, and that a transition in the scanning direction from a first to a second, or from a second to a third or a first binary information item and a transition in the scanning direction from a third to a first area from a first to a third, or from a third to a second, or from a second to a first Area each represents a second binary information item.

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All transitions that represent a binary "1" when scanning in a first direction represent a binary ¹¹ O "when scanning in a second direction, ie if scanning is not carried out in the forward direction but in the reverse direction, the complement of the recorded information is created.

Since the information is not represented by the areas themselves but by the area transitions the requirement of the time system in the present invention is not very critical. Therefore one can take advantage of Hand scanners are used, which are guided at different speeds over the recording medium can. Another advantage is that the recording areas do not have to be of the same size in the scanning direction.

An embodiment of the invention is described below with reference to drawings. In these shows: -

Flg. 1 a record carrier on which data are applied in coded form;

2 shows a basic illustration of the hand-held scanner, a dichroic mirror and in the form of a block diagram the data recognition and processing device;

3 shows a sectional view along the line 3-3 i * ^{1 in} FIG. 2j

4 shows a detailed block diagram of the recognition device; .

FIG. 5 shows a part of the detection circuit according to FIG. to display the synchronization for the data transmission in the memory area;

6a shows the first part of a block diagram of the decoding circuit;

6b shows the second part of the decoding circuit; Fig. 7 shows an input register circuit;

Fig. 8 shows a circuit for processing the data recorded at the ends of the record carrier;

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Pig. 9 shows the first part of a circuit for the synchronization of a memory input;

10 shows the second part of a circuit for the synchronization of the memory input; Flg. 11 shows a circuit of the memory unit; Fig. 12 shows a circuit of the comparison unit; Fig. 13 shows a circuit of the program counter unit; Fig. 14 shows a circuit of the parity check unit; 15A shows the first part of the output register circuit; 15B shows the second part of the output register circuit; 16 shows the first part of a control unit, and FIG 17 shows the second part of the control unit.

In Fig. 1, a recording medium is shown on which a plurality of strip-shaped juxtaposed different colored stripes are applied. Side by side of the three different color strips used are each different. On the recording medium according to FIG. 1, strips with the colors green, black and white used. The green and black stripes are printed on the white support so that there are white everywhere Stripes appear where no green or black stripes are printed. The label serving as a recording medium described in the present invention was thus made with provide the encoded data so that it can be scanned in both the forward and reverse directions. The on Code sections applied to the carrier are combined in such a way that on one section four bits, which are carried by four transitions are shown, each can be summarized.

Instead of the recording medium structure described above a recording medium can also be used on which, for example, magnetic areas with different

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union magnetization properties are provided.

In the present example it is assumed that the label 20 shown in Fig. 1 from left to right is to be scanned, as indicated by arrow 12. The first color transition is a white-green Transition, and occurs at strip 22. This transition represents a bit whose value is changed by the left-right direction is given. The next four transitions will arise on strips 24, 26, 28 and 30. The following transitions occur: from green to black, from black to green, from green to black and from black after green. This code section indicates the number of data bits recorded on the label 20. The transition from the strip 22 to the strip 24 represents a bit that is weighted sixteen. The transition from 28 to JO represents a data bit that is provided with the weight two. The transitions from 24 after 26 and from 26 to 28 are accordingly with eight and four rated. -

The first color transition that is scanned after the aforementioned recording section is a first parity transition from strip 30 to strip 32. This transition is a transition from green to black. The next four transitions that occur when scanning from left to right arise on strips 34, 36, 38 and 40. Also rated these four transitions / mTt corresponding weights. The transition from 32 to 34 is from black to green and is provided with the code weight one. The transition from 38 to 40 takes place from white to black and is with rated the weight eight. The evaluation sequence of the transitions thus increases in a scanning direction from the left to the left right on.

The transitions created by the color strips 42, 44, 46 and 48 represent e.g. a number; with the lowest

009884Π923 June 12, 1970

Weight. From 42 to 44 there is a transition from black after white, which is evaluated with the code weight one. The transition from black to white of the color strips 48 and 50 is weighted with a code weight of eight. Both the sequence of the individual bits and the sequence of the individual bit segments is evaluated with an ascending weight sequence for a scanning direction from left to right. The transition from strip 50 to strip 52 is a transition from white to black and just like the transition from 30 to 32 this represents a parity bit. Independent of In the scanning direction, signals with opposite binary values are distinguished from these two transitions.

The colored stripes 52, 5 ^> The four transitions associated with 56 and 58 are thus also represented by the colored stripes 24, 26, 28 and 30 associated transitions are shown. However the information assigned to the last-mentioned strips is the complement to the first-mentioned transitions The code weight assigned to the transition from 52 to 54 is two and that of the transition from 58 to 60 assigned code weight, on the other hand, sixteen. It can be seen that the code weights of the by the stripes 52, 54, 56 and 58 are sloping in a scan direction from left to right. The transition from 60 to the white background of the label 20 is a transition from black to white and represents a bit, which is defined by the second scanning direction.

The two parity bits are chosen so that the total number of all "O" bits modulo 3 of the total number of "1" bits modulo 3. This allows the white background on the label to be the first color area at both ends be used.

The data bits represented by the color transitions are under the label in Fig. 1 / SargestefIt. Through the two

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Arrows 12 and 14 become the two possible scan directions indicated. When scanning in the direction of arrow 14, the recorded bits are reversed and sampled inverted. The following describes how the sampled data is decoded in this case. Of the Transition from a white stripe to a black stripe or from a black stripe to a green stripe or from a green stripe to a white stripe represents the binary information "l". A transition from one white stripe onto a green stripe or from one green stripe to a black stripe or from one black stripe on a white stripe represents the binary information "0".

From the above definition it can be seen that all information recognized as "1" in a first scanning direction recognized as "O" when scanned in a second direction will. The characters recognized in a first scanning direction represent the complement to those in a second scanning direction recognized characters.

In Fig. 2, a scanning device is shown which comprises a stylus 62 which, for example, is provided by a sales person is operated at an automatic cash register terminal. The follower pin 62 has the shape of a pen holder, so that it can easily be passed over a label. Other useful scanning devices are well known, and can also be used with success in the present invention. It is not absolutely necessary that the The scanner is moved over the label. It is only important that a relative movement between the scanner and the label comes about.

The light source 64 is in a housing 68 in a conventional manner Way attached. In this housing there is also a converging lens 70 and a converging lens 72, the of the light source 64 generated light in a branch 78 of a

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June 12, 1970

an optical fiber bundle existing transmission arrangement transferred. The converging lenses can, if desired, together with the light source 64 as an integrated module being constructed.

Section 78 of optical fiber assembly 74 conducts the light generated by the light source 64 through the stylus 62 onto the label 20. The line section 80 consists also made of optical fibers and directs the light reflected from the label onto a dichroic mirror 100, which is arranged in a housing 76. The optical fiber assembly 74 is surrounded by an abrasion-resistant protective cover. One end of the optical fiber bundle is at 82 with the Follower pin 62 connected.

In Fig. 3, the stylus 62 is shown in section along the line J5-J5. Epoxy layers surrounding the optical fiber bundle 90 are shown at 86 and 88. The individual optical fibers can, for example, have a diameter of 0.076 mm. The small white circles in FIG. J5 represent the optical fibers running in the section 78 ', while the small black circles in FIG. J> indicate the optical fibers of the stylus 62 via the section 80 to the housing 76 to lead.

A conventional objective lens 94 is located in the stylus 62 arranged that the from the light source 74 via the section 78 light received from the transmission assembly 74 onto the label 20 focused. The light spot produced on the label 20 is approximately as large as the width of the light spot on the label 20 Color stripes. The light reflected from the label 20 passes through the objective lens 94 into the optical transmission device 74 and the section 80 on the dichroic mirror 100 in the housing 76.

The housing 98, which surrounds the dichroic mirror 100 and the photosensitive elements 102 and 104, is impermeable to light. The dichroic mirror 100 reflects one

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Part of the received light on the photosensitive Element 102, while the remaining part of the light passes through the mirror 100 onto the photosensitive element got. The mirror is for the infrared part of the light transparent, so that it can reach the infrared-sensitive element 104. The rest of the light will reflected from the mirror 100 onto the non-infrared sensitive element 102. Both components of radiation will be reflected off the label 20 when a beam of light is directed by the stylus 62 onto a white stripe. If the. If the light beam is directed onto a black stripe, none of the components are reflected. If the Beam of light on a green stripe, it just becomes the infrared part of the light reflects. In the device described, green, black are on the label 20 and white stripes are used, but others can be used Color combinations are applied. When the infrared and non- "infrared signal components are used for evaluation can be a white stripe instead of a color stripe be used, the both non-d-nfrarote and also infrared components or components in the vicinity of infrared would have to reflect. Instead of the green stripes, stripes containing non-infrared components can also be used absorb, and infrared or near the infrared Areas of lying light components reflect or are transparent to them. Instead of the black stripes, colors that are both infrared and also do not absorb infrared light components.

The output signals of the light-sensitive elements 10 and 104 pass into an amplifier device 106 in which two separate amplifiers are provided. The amplified signals enter the detection device via lines 108 and 110 112. This device decodes the

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over the lines 108 and 110 incoming signals, and generates a binary data signal corresponding to the signals arriving on these lines. These signals get over the line 113 into a data processing device 114. The latter is connected to an input device or to a display device, e.g. a cash register can.

In Fig. 4, a video processing unit 115 is provided, to those via lines 108 and 110 that are not infrared Signal components and the infrared signal components are applied. The video processing unit 115 is described in detail in the German patent application corresponding to this application, which was filed under the designation "data scanning system". The binary appearing on lines 108 and 110 Data represent the color transitions of the color stripes white, green and black. According to these signals appear on lines 120, 122 and 124 signals. A signal is generated on the line when both the light-sensitive element 102 and the light-sensitive element 104 has generated a signal. A signal is then produced on line 122, when only the photosensitive element 104 has generated a signal. A signal is produced on line 124 if neither the element 102 nor the element 104 has generated a signal.

A decoder unit 126 (Fig. 4) receives the signals "white", "green" and "black" from the video processing unit II5. Corresponding to these signals, signals with the logic level "1" or "0" are generated, which one Input register 128 are supplied. In the input register 128, the data is temporarily stored after it have been decoded in unit 126. From the input register 128 they are stored in a memory at a specific time 130 transferred.

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The memory 130 contains a 5-bit auxiliary storage register 152, the input of which is connected to the output of the input register 128. Between the auxiliary storage register I32 and an output register 148, a storage register 134 is arranged. The storage register 134 can be from a 128-bit metal oxide semiconductor shift register or off consist of a different type of shift register. A total of 33 bits can be stored in the memory, which are derived from the Label have been scanned. Thus, on the label thirty digits of four bits each are recorded. The memory 1 "50 is constructed in such a way that the newly arriving Data are transferred from the auxiliary storage register 132 into the storage register 134. The ones in the storage register The data located in it can circulate in it.

A memory input synchronization unit I36 is included the input register 128, an end-of-label detector 138, a comparison unit 147 and a program counter unit 140 connected. She receives signals from the Label end detector I38, from the comparison unit 147 and from the program counter unit 140. It controls the data transfer to the auxiliary storage register 132 a certain time.

The stylus 62 in FIG. 2 can be guided over the label 20 at various speeds. For example, the speed can be 1520 mm / sec for each digit. or more. It is therefore necessary to determine when the stylus 62 has completely scanned the label 20. This task is accomplished by the label end detection ^{device 138 in that it generates a signal "label end 11} " when the stylus 62 is moved over a white stripe which is at least four times as wide as a black or green color stripe. generated by the color end detection unit I38, those in the memory I30 and im

009884/1923 June 12, 1970

Output register 148 located data is checked, it is determined whether they represent value information.

The last five bits read from the label _; represent a code section consisting of four bits and a direction bit. These bits are stored in the auxiliary storage register 152. The bits belonging to the code section, which are now located in the auxiliary storage register 132, are compared by the comparison unit with the bits which represent a code section and are located in the output register 148 when a "label end signal" is generated by the device 138. If two numbers are the same, a signal is applied to the parity check unit 146, thereby initiating the parity check. A parity check signal occurs when the sum of the "1" bits is equal to the sum of the ¹¹ O "bits. The stored bits are added up modulo 3 (only the digits O, 1 and 2 may result in the sum if 1 is 2 is added, the result is o).

The program counter unit 140 contains a 7-bit program counter that can count up to 128. The count of this The counter is incremented each time the data in the memory register is shifted by one position. the

Program counter unit applies a control signal to the memory input -Synchronizing unit, which ensures that the input register 128 from the front is in the auxiliary storage register The data to be transmitted can only be transmitted in the counting range between 127 and 007. The maximum count 127 is followed by the counter reading 000.

The input of the output register 148 is connected to the storage register 134. Its exit leads to the data processing device 114 shown in FIG. 2. The output register 148 is a shift register to which the Data bits are applied in one direction and that these data bits in forward or backward direction ^ as a function from the direction in which the stylus 62 crosses the label

009884/1923 June 12, 1970

is performed, the data processing system 114 supplies.

sometimes The data to be transferred are thus / in their consequence - ' swept before they are further processed.

A conventional circuit that generates two main clock signal trains is used as the clock generator. The first is drawn below as "bar 1" and "bar 3". Both Clock signals have the same pulse repetition frequency, however, they have a different temporal position within this frequency. The two clock signals can also pass through the data processing system as a function of the main clock signal 114 can be generated. They are required at the storage register.

The logic circuit of the recognition system can be in housed in a separate function block. The main functions performed by the logical unit are (1) converting the video signals to binary signals; (2) Storage of the decoded bitsj (3) Identification of the label; (4) Evaluation of the information on the label and (5) Output of the data to a display device, a Cash register or a data processing system.

The decoding unit 126 in Fig. 4 converts the "black" "green" and "white" signals in binary "l" or "θ" signals around. The logic consists of flip-flop elements, in which it is stored whether a first or a second color strip is scanned became. When a first color has been saved and a second occurs, a "data transfer pulse" is generated, which indicates that a color transition has occurred. The second detected color stripe is again in a flip-flop stored until a next color stripe is detected.

Every time a "data blanking pulse" is generated, the binary signal arriving on the data transmission line is stored in the input register 128. This register is required, since the data is scanned asynchronously, but is supplied to the memory 130 at a specific time

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should be. The size of this register depends on the access time of the main memory. In the one described here An 8-bit register is used for execution.

The program counter unit 140 contains a seven-stage binary counter, which controls the flow of data into memory 1 ^ 0. The value of the program counter increases each time by one increases when the data is shifted one place in memory. If new data has already been sampled and if previously scanned data are still in the memory, the new bits are stored in the positions in which the previously sampled data was previously located. The program counter carries out this control together with the memory input -Synchronizing unit 136 through.

New data can only be entered into the memory register lj> k in the period in which the program counter has the count value "O". When new data bits are entered into memory, the program counter is reset to "0" each time after the last data bit has been entered. Each time the program counter reaches the "0" count, the input register 128 is checked to see if any new data bits were sampled in the previous period while the counter was at the "o" count.

In Figure 5, three new bits of data entered into the first three stages of the input register 128 have been sampled. When the program counter reaches the count "0", the three data bits are entered into the auxiliary storage register 132 and at the same time the last scanned three bits on the left in the input register 128 are shifted to the right. The bits in the three right memory locations of the auxiliary memory register Ij52 are shifted into the memory register \ y \. If the input register 128 no longer stores any data, the program counter is reset to the value "O". The reset

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of the program counter takes place at the moment in which the last bit is inserted into the memory register 134 and takes place automatically through the necessary synchronization. The data transfer from the input register 128 to the auxiliary storage register 132 and to the storage register 134 takes place whenever the input register contains new data bits and the program counter shows the count value ¹¹ 0 ", but the end of the label has not yet been determined.

The auxiliary storage register 132 contains the last ones five pits scanned by the stylus 62. The value of the data in auxiliary storage register 132 is compared with the counter reading of the program counter in order to determine the time in which the data is transferred from the storage register to the output register 148. Afterward becomes the code section stored in auxiliary storage register I32 compared with the code section located in the output register, and if a match is found, a label value signal is generated that carries out a modulo 3 parity check initiates.

A modulo 3 parity check is carried out each time if a V / ertetiKetty is determined. According to the the above-mentioned test procedure must be the sum of all "1" bits equal to the sum of all "0" bits taking into account of modulo 3 counting ». The table below gives an overview of the modulo 3 parity check procedure for different recording media, each with a different one Number of recorded data bits included.

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EAD ORlGSIsiÄL

MODULO 3 PARITY CHECK

SiMUQe Digits Bits Modulo 3 count Sum "O" 2 20th Sum "1" 1 4th 28 1 2 6th 36 2 0 8th 44 0 1 IO 52 1 2 12th 60 2 0 14th 68 O 1 16 76 1 2 18th 84 2 0 20th 92 O 1 22nd 100 1 2 24 108 2 0 26th 116 0 1 28 124 1 2 30th 132 2 O O

With the modulo parity test method described above, ⁿ l ^w bit errors and multiple errors are detected that do not arise due to a multiplication by three. Errors based on the fact that an ⁿ 0 ^{ff is} read as ^w l ^w and at the same time an "l ^w as" 0 ™ cannot be determined either.

Whenever the values of a label have been decoded and the parity check has determined that it is a matter of a value or amount, the data bits are fed to a data processing device. The output register 148 consists of an eight _T stage 5: shift register in which the data can be shifted to the left as well as to the right. The data are each through

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009884/1823

Right shift entered into output register 148. During the transfer from the output register 148 into the data processing system, the shift direction is through the value of the "direction bit" scanned from the label was decided. If a label was scanned from right to left instead of left to right, all sampled bits form the complement. The transfer from the output register 148 to the data processing device occurs in a reverse order than it does would occur if one were to scan from left to right,

Decoder circuit, Figures 6A and 6b

Bringing FIGS . 6k and 6B together along line 6-6 results in the decoder circuit indicated by 126 in FIG. The input lines 120, and 124 are connected to inverters 182, 184 and 186. A NAND gate 188 has a first input which is connected to the line 120. A second input is connected to the output of inverter 184 and its third input is connected to the output of inverter 186. The NAND gate 188 generates a "0" output signal when the line 120 has a "white signal" and the lines 122 and 124 have neither a "green signal" nor a "black signal". The inverter 190 inverts the output signal of the NAND gate I88, ie it generates an output signal with the level "1" if only a "white signal" occurs at the input of the line 120, but no "black signal" and no "green" Signal "is present on lines 122 and 124.

A NAND gate generates 192 on the same principle and an inverter 194 has a logic "1" output signal when a "green signal" occurs on line 122, however lines 120 and 124 no "black signal" and "white signal" is available. A NAND gate 196 and an inverter

.197α 0098 8471923

generate a logical "1" signal when a "black signal" occurs on line 124, but neither a "white signal" or a "green signal" is present on lines 120 and 122 1st.

The output of inverter 190 is connected to the first input a NAND gate 200, while its second input is connected to the output of an inverter 267 (Pig · βΒ) is. A "transmission blocking signal" is applied to the second input mentioned last. The "transmission blocking signal" prevents new data from entering the memory 130 are entered although the data that were scanned from a previous label are still in memory I30, since these could not yet be fed to the data processing system 114 (Pig. 2). In this case the Entering new data for a predetermined time (e.g. 100 microseconds) delayed. After this time, the transmission interference signals have also subsided.

The output signal of the NAND gate 200 is at C with connected to the unconditional clear input of a flip-flop 205. Flip-flop 205 is shown and represented in somewhat greater detail the mode of operation of all used in the circuit Flip flops. The following is a truth table used for flip-flop 205 and for all used in the circuit Flip-flops has validity.

FLIP-FLOP TRUTH TABLE

^Y n ^K n

0 0 Q _n (no change)

10 1 (set)

0 1 0 (delete)

1 1 Q +1 (change depending on

state)

(n means a clock time which is defined by the clock pulses that are applied to the clock signal T. It is assumed that η = 0, 1, 2, 3 ».etc., can be).

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The signals appearing at J and K determine the state of the flip-flop according to the aforementioned truth table. When a "θ" signal is applied to C, the flip-flop is cleared. ^{If a signal with the level W} O ^{M is} applied to P or to the preset input, the flip-flop is set.

If the flip-flop 205 is unconditionally cleared, a signal with the level "0" occurs at Q and a signal with the level ¹¹ I "at Q. The flip-flop 205 is cleared when a signal with the level at the output of the NAND gate 200 The outputs of the NAND gates 202 and 20 ¹ I are connected in the same way to the C inputs of the flip-flops 206 and 207. The clock signal inputs T of the flip flops 205, 206 and 207 are NAND gates 246, 252 and 256, through which you receive the signals "wgj ^ set", "green set" and "black set". The "transmission lock signal" from the inverter 267 assumes the value "1" is produced at the output of the NAND gate 2CO then a signal "O" when the output of the inverter 190 has a "1" signal at the same time. When the "transmission ^blocking signal w assumes the value ^w 0", the NAND gates 200, 202 and 20 * 1 can ^{No longer generate an 11} O "signal at their output, which is fed to flip-flops 205, 206 and 207 as a clear signal.

The input K of the flip-flop 205 is permanently connected to the cash register, so that a "0" signal is constantly applied to it. The input J is not occupied, which means that there is a constant "1" signal at this input. When the signal "white set" assumes the value "1" and at the same time a "1" Signal is applied to the C input, the flip-flop can be set. The Q output of flip-flop 205 becomes to "0" and to the input J of a flip-flop 210 and to the Input C of a flip-flop 212 applied. The signal Q at the output of flip-flop 205 is referred to as the "white lock signal".

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Before the scanning pen 62 is initially moved over a white strip, there is a "0" signal at the J input of the flip-flop 210, which is fed from the Q output of the flip-flop 205. The flip-flop 210 is cleared when a "1" signal is simultaneously applied to its clock signal input. This is the case because the Q output of flip-flop 205 is cleared via NAND gate 200. This produces at its output Q a "l" signal to the J input of flip "flop 210 is applied and when the" clock 1 "signal level" 1 ", at the same time this signal flop to flip _T is applied 210 whereby this is set. When the flip-flop 210 is set, a "1" signal is produced at its output Q and an "o" signal is produced at its output Q. The signal arising at the output Q of the flip-flop 210 is referred to as "white pulses".

When flip-flop 205 is cleared by the NaI-JD-member 200, a reaches "1" signal to the input C of flip-flop 212. The J input of flip-flop 212, which is connected to the Q output of flip-flop 210 receives a " 1 "signal when the flip-flop 210 is set. Since the flip-flop 212 was initially cleared by the "θ" signal appearing at the output Q of the flip-flop 205, a "1" signal initially arises at the output Q of the flip-flop 210, which is connected to the input K. When the "clock 1" signal assumes the value "1", the flip-flop 212 is set. When the flip-flop 212 is set, an "o" signal is produced at its output Q, which signal is applied to the input C of the flip-flop 210. This clears flip-flop 210 again. If a "1" signal is applied to the clock signal input of flip-flop 205, this is reset to its initial state.

When the stylus 62 is swept over a green stripe, the flips-flops 206, 214, and 216 are actuated in the same manner as the flip-flops 205, 210 and 212 when a white stripe is scanned by the stylus 62.

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When the stylus 62 crosses a black stripe, the flip-flops 207, 218 and 220 become in the same way actuated like flip-flops 205, 210 and 212 when a white stripe is scanned.

The NAND gates 222-228 in Figure OB received receives the corresponding "color lock signals" and "color pulses" from flip-flops 205-220. For example the NAND gate 222 a "green signal" from the output "Q of flip-flop 214 and a "black signal" from the Q output of the flip-flop 218. A "1" signal at the output of the NAND gate indicates that either a "green pulse" or a "black pulse" was generated. The NAND gate generates in the same way 224 a "1" signal indicating that a "white signal" or a "black signal" has been generated. The NAND gate 226 then generates a "1" signal when a "white signal" or a "green signal" has been generated.

The output signals of the NAND gates 222, 224 and are applied to NAND gates 240, 250 and 254 to produce a "White reset signal" and a "black reset signal" to produce. The output of the NAND gate 222 is with a first input of NAND gate 240, the output of NAND gate 224 is connected to the first input of NAND gate 250 and the output of NAND gate 226 is connected to the first of NAND gate 254. Each of the named NAND elements receives a "value transfer signal" from the terminal 602, which is connected to the control unit 142 of FIG. That "Value transmission signal" assumes the level "1" when Video signals from the video processing unit 115 of FIG. 4 can be transmitted to the decoding unit 126.

During the time during the signals from the video processing unit 115 are transmitted to the decoding unit 126, the NAND gate 240 then generates one in each case Signal with the level "0" if a "green signal" or a "Black signal" occurs. The first input 6o4 of a NAND gate 242 receives a "clock 1" signal and the second Input 606 a "value transfer signal". The NAND gate 242

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generates a signal of level 1 when information is transmitted from the video processing unit II5 to the decoding unit 126 / when no information is transmitted between the aforementioned units, the NAND gate 242 'generates a "0" signal during the occurrence of a "clock 1""Signal with the level" 1 ".

The output of the NAND gate 240 is connected to the first input of a NAND gate 246, the second input of which is coupled to the output of the NAND gate 242. That

. NAND gate 242 causes NAND gates 246, 252 and 256 Generate reset signals for flip-flops 210-220 when stylus 62 has completely traversed the label. The stylus 62 has crossed both all the color strips and a white section that is four times as large as one single color stripe is.

In the same way, the NAND gate 252 generates a "green reset signal" of level "1" when a "white signal" or a "black signal" with the level "l" is generated and the "value transfer signal" also has the level "1". In the same way, the NAND gate 256 generates a "black reset signal" with the level "1" when a "white signal" or a "green signal" with the level "1" is generated.

If the flip-flop 205 is cleared by the appearance of a "white signal" on the line 120, it remains in its cleared state until a "green signal" or a "black signal" is generated and thereby the NAND gate 246 a "white reset signal" of level "1" is generated. This signal is applied to the clock input of flip-flop 205, whereby it can be reset if a "1" signal is applied to its input C at the same time.

The NAND gates 222-238 are with the flip-flops 205 to 220 and receive the various color locking and color pulses generated by said flip-flops. The NAND gate 228 has the

6/12/1970 '0Q988Ä / 1923

"Green locking and black pulses", at its inputs lie and therefore generates a signal with the level "O" if both impulses occur at the same time. The "white lock and green signals" arrive at the inputs of the NAND gate 230 and the "black lock and white signals" at the inputs of NAND gate 232. The last two NAND gates generate a signal with the level "1" if the respective pulses are simultaneously at their inputs appear. The outputs of NAND gates 228, 230 and 232 are connected to the inputs of a NAND gate 25 $, its Output then generates a "1" signal when three "θ" signals are present at its inputs. The output of the NAND gate is connected to the input of inverter 260.

When the stylus 62 is passed over the label 20, when a green stripe is scanned, a "1" level "green interlock" signal is generated , and when a black stripe is subsequently detected, a "1" level "black signal" is generated whereby a recorded "θ" bit signal is recognized. If a recorded "ü" bit is detected, outputs a signal of level ¹ O ". The outputs of the NAND gates 234, 236 and 238 of a NAND gate 262 are connected nr.it three inputs, which is formed of the inverter 260 Output is coupled to the input of an inverter 264. The "white locking signal" and the "black signal" are thus at the inputs of the NAND gate 234, while the "black locking signal" and the "green signal" at the input of the NAND gate 236 and the "green lock signal" and the "white signal" appear at the inputs of the NAND gate 238. A signal with the level "1" occurs at the output of the inverter 264 when a recorded "O" bit is detected Inverter 260 a signal with the level "1" on and at the output of the inverter 264 a signal with the level "O" when a recorded "1" bit has been recognized.

June 12, 1970 009884/1923

The NAND gates 266 and 268 are cross-connected to form a locking circuit. If an ¹¹ I "bit signal was detected _; the ^M 1" signal from the output of the inverter 260 and the "O" signal from the output of the inverter 264 switches the NAND gate 266 to the ¹¹ O ¹¹ state and the NAND gate 268 to the "1" state. If the NAND gate 268 has been switched to the "1" state, a "1" signal appears on the data line and at the output terminal 6o8 and the "O ^w signal from the output of the inverter, the NAND gate 266 into the" 1 "state and the NAND element into the" θ "state. This produces a signal with the level" 0 "at the output terminal 6o8. The outputs The inverters 260 and 264 are connected to the inputs of a NAND element 270, the output of which is in turn coupled to the input of an inverter 272. Every time an ¹¹ I "bit or a ^Μ 0" bit is detected, the output of the NAND - Link a signal with the level "1" to "which appears at the output of the inverter as a signal with the level" 0 ". If neither a" 1 "bit nor an ¹¹ O" bit is recognized, the output terminals of the inverters and 260 and 264 signals with the level "1". The output of inverter 272 represents a "data pulse" which can be tapped off at terminal 610.

The NAND gates 274 and 276 are crossed with each other connected and form a blocking circuit. The output signal of the NAND gate 274 is applied to an output terminal and is called "data value signal". That at the output of the NAND gate 276 is sent to an output terminal 614 and is called the "data value signal". If at the exit of the Inverter 272 generates a "0" signal, the NAND gate is in the "1" state, and the NAND gate 276 in the "θ" state switched when the "data reset signal" is applied to an input 616 of the NAND gate 276 at the same time.

June 12, 1970 009884/1923

This signal comes from the input register 128 (Fig. 4). The "data reset signal" at terminal 616 changes to an "O" level when the "clock 1" signal has a level "1" having.

The output of an inverter 308 is connected to the input of a NAND gate 261, which is cross-connected to a NAND gate 263 and forms a blocking circuit. At the input of the NAND element 229 are the "white pulses ¹¹ , the" green pulses "and the" black impulses ". At the terminal 618 a" color signal "arises when the linkage condition for the NAND element 229 is met« The fourth stage a counter 310 in Fig. 8 generates the "delayed reset signal" which occurs at the terminal 629 and arrives at the input of the NAND gate 263. Whenever a "1" signal occurs at the output of the NAND gate 229 and at the same time at the Terminal 623 the "clock 1" signal is present, a "reset signal 310" is produced on line 621 by a NAND gate 306 (FIG. 8) which resets the counter 310. If a "color signal" with the level ' ¹ I "occurs, the NAND gate 261 is switched to the" 1 "state and the NAND element is switched to the" 0 "state, since the" delayed reset signal "and the signal at the terminal 620 have a logic level" 1 ".

The counter 310 in FIG. 8 is increased by one each time when a "1" signal is produced at the output of the NAND element 320 and is applied to the value increasing input of the counter 310. The "delayed reset signal" at the terminal 622 will assume a logic level "0" after the "reset signal 310" has assumed the value "1". For example, this happens 100 microseconds after the "reset signal 310" on the line 621 has assumed the value "1" again. If the "color signal" was generated by the logic element 229, an ¹¹ O "signal occurs at the output of the inverter 308, and if the" delayed reset signal "is at the terminal 620

6/12/1970 0 0 98 8 4/1 923

If the value has the value "I", the NAND gate 263 is switched to its "©""state and the NAND gate 261 is switched to its" 1 "state. The output of the NAND gate is connected to the input of the NAND gate 265 the second input of which is coupled to the control unit 142 (FIG. 4), which means that a "wertransmission signal" is applied to the terminal 62h . When two "1" signals use the input NAND gate abut 265 "is produced at its output © to" 0 "Signal * üüb as" transmission blocking signal "beaeictoet nira tmü ISIbex ³ the inverter 2β7 • to the inputs of the NAND gates SOO ^ 2Q2 and 204 (Fig. 6A) *. The delay of the ^ ftoertraguBgggpeirsign & ls ⁸⁹ is caused by the "delay ^{reteefcasigaal 83} sm uew terminal 62o ^ which ensures that interference signals transmitted over transmission do not get into the irteMswagssysfeai ^ when new information bits are recognized«,

Input register »Pig« 7

The input terminal, which is connected to a NAND element §8, is coupled to the output terminal 612 of the MMD element 2-4 (FIG. 6B), as a result of which ^w data value ^{signal © w} vqb are transmitted to the NAND element. At the second input 632 come the. "Clock 1" signals »The third input 634 of the NAND element 278 receives the" THIsBlendunterdrücicungsimpuls "of the memory input synchronization unit I36 (Pig. 4). This pulse prevents new data from being entered into register 280 during the time that data is being transferred from input register 280 to memory 130 (Pig. 4). Thus, when the "clock 1" signal at terminal 632 and the "data value signal" at terminal 630 and. the "output suppression signal" applied to terminal 634 each have the value "1" and a "0" signal is generated at the output of the NAND element 2-8.

June 12, 1970 009884/1823

The "clock 3" signal is applied to an input terminal 638 of a NAND gate 290, and the "fast shift inhibition ^{signal 11 is} applied to the second input terminal 640, which is connected to the memory input synchronizer 136 (FIG. 4). This signal has as long as the data is stored in the input register 280 and is then transferred to the memory 130 (FIG. 4) "0 ^M signal.

The outputs of the NAND elements 28 and 290 are connected to the input of a logic element 292. The output of the NAND element 292 is connected to the shift input of the shift register 280. Every time the NAND ^{gate generates an n} 1 ^M signal, the data stored in the shift register are shifted by one position in the direction of the output. The shift signal also appears at terminal 642.

The NAND gates 284 and 286 are cross-connected to one another and form a trap circuit. The output of a NAND gate 282 is connected to an input of the NAND gate, while its first input is connected to a terminal 644 to which the "clock 1" signal and its second input to a terminal 646 are connected to the terminals 614 (Fig 6B) the "Dafcenwertsignai" is applied. The output of the NAND element 282 only has an ^M 0 ^w signal when the two signals present at the inputs have the values "l ⁿ .

The "data value signal" present at the terminal 63O has the value "O ^w if the" data value signal "which is sent to the NAND element 282 has the value * .l * "1" signal when the NAND gate 286 is switched to the ⁿ 0 "state and the NAND gate 284 is switched to the" I ^H state.

June 12, 1970. »09884/1923

If at the output of the NAND gate 282 an "i" signal arises, arises at the output of the NAND gate 278 an "O" signal, the NAND gate 284 in the "O" state, and the NAND gate 286 is switched to the "1" state, as a result of which a "1" signal is produced at the output of the NAND gate 286. A NAND gate 288 has an input which is connected to the output of NAND gate 286. Its second entrance is with a terminal 648 connected to the "clock 1" signal is created. If the "Clock 1" signal has the value "1"

k points and at the same time a ^W 1 ^{M level is present at the output of the NAND element 286, a w} data reset value signal ⁿ with a level "0" is produced at the terminal 650. This signal is connected to input terminal 616 of NAND gate 276 in Pig. 6B connected.

At the first input of a NAND gate 294 is from the output terminal 608 of the NAND gate 268 (Fig. 6B) a "data line signal" is applied, while at the second input, which is connected to the memory synchronization unit I36 (Fig. 4) is connected, the "masking prohibition signal" is applied. The output of the NAND gate 294 is connected to an input of a NAND gate 296 connected, the second input to the Output of a NAND gate jJOO is connected. The NAND element 296 generates a "1" data signal at its output, which is an line 656 is applied. In addition, the output of the NAND gate 296 is connected to the input of the first flip-flop Stage of the register 280 connected. In this connection an inverter 204 is connected. Every time the logic element 292 sends a shift pulse to the shift register 280 is applied, a new data bit is entered into the shift register and the ones in it Data is shifted one place towards the exit.

The output of the NAND gate 300 is with one Input of the NAND gate 296 connected. One input of the NAND gate 300 is via 660 with the last flip-flop stage of shift register 280 is coupled and receives

009884/1923

June 12, 1970

a "data output signal", while the other input is connected to a terminal 662 to which the "fade-out prevention signal" from the memory synchronization unit (Fig. 4). Every time the link conditions for the NAND gate 300 are satisfied, the data stored in the register 280 can circulate.

Label end detection device, FIG. 8

A NAND gate 306 in FIG. 8 generates a "reset signal 31o" which is sent via line 621 to the reset input a counter 310 is applied. The "warning signal" reaches the first input of a NAND gate 312 via a terminal 67O. Terminal 670 is connected to the output of NAND gate 229 (Fig. 6B-). The "cycle 3" signal arrives via a terminal 672 to the second input of the NAND element 312. The output signals generated in it reach a line 674 via an inverter 314. This Line is connected to the first input of a NAND ' GlMergruppe 316 connected. Of these logic elements, the second input is in each case with the output of a stage of the counter 310-connected, while their outputs respectively are connected to an input of a counter 318. By the NAND gates 316 are those at the outputs of the counter 310 occurring signals inverted when at the output of the NAND gate 312 an "O" signal occurs.

A "clock 5" signal is applied to the first input of a NAND element 320 via a terminal 676. the The pulse repetition frequency of this signal is less than those of the "clock 1" and "clock 3" signals. For example, Sfekann be smaller by a factor of four. At the second input of the NAND gate 320, the "Value transmission signal" from the control unit 142 (Fig. 4) created. If at the output of the NAND gate 320 a "0" signal

009884/1923 June 12, 1970

occurs, the value of the counter 310 is increased by one each time .

A “clock 6” signal is applied to a logic element 322 via a terminal 680; The pulse repetition frequency of the "clock 6" signal is in turn lower than the pulse repetition frequency of the "clock 5" signal. For example, it can be reduced by the factor five. be. The "clock 2" and "clock 4" signals are used for the memory register 134 (FIG. 4) consisting of * metal oxide semiconductors and the "clock 5" and "clock 6" signals are used by the "clock 1" and "iTakt 3" signals derived in a known way. If a "0" signal occurs at the output of the NAND gate 322, the value of the counter 318 is increased by one in each case.

Due to the pulse repetition frequency, the counter 310 counts six times as fast as the counter 318. If all stages of the counter 318 are in their "1" state before the new information is transferred from the counter 310 to the counter 318, a NAND- Gliedes ^ 24, whose inputs are connected to the individual stages of the counter 318, an "O" signal. The signal appearing at the output 'of the NAND gate 324 ⁸¹ O "signal indicates that a strip is scanned by the stylus 62, which is four times as wide as the preceding streaks. The latter signal is inverted by an inverter 325th

It can thus be determined when the stylus 62 has crossed the label 26. The data can with can be sampled at a rate not less than five milliseconds per bit. Through some exercise you can the operator can satisfy the condition without difficulty. The "clock 5" signals present at the NAND gate 320 are dimensioned so that all stages of the 1 counter 310 within seven milliseconds after resetting the

009884/1923

June 12, 1970

Counter 310 are switched to their ¹ M "state, from which they are reset by the" reset signal J10 ". If no new data bit has been sampled during these seven milliseconds, a * 0" signal appears at the output of a NAND gate 311 whose inputs are connected to the outputs of the counter 310. The NAND gate generates an "end of transmission signal" which is applied to an output terminal 682 via an inverter 313.

The output of the inverter 325 is connected to the input of a NAND gate 326, the second input of which is connected to the Q output of a flip-flop 684. Flip-flop 328 generates a control signal at output 684 which occurs after a first color stripe has been scanned. The K input of this flip-flop is connected to ground. His J entrance is not busy. The "data signal" is applied to the clock input via a terminal 686, which is derived from Flg. 6B comes from terminal 610. The "value transfer signal" from the control unit 142 (FIG. 4 ) is applied to the C input via a terminal 688.

When the ^w value transfer signal ⁿ at the terminal 688 takes the level ^M 0 ^w , the flip-flop 328 is cleared and an ¹¹ O "signal appears at its Q output ^M 1 ^M signal occurs, the flip-flop 328 is set, which results in a ^w 1 "signal at the Q output. If the linkage condition for the NAND element 326 is met, a signal is sent to the input of a NAND element 330. The "label reset signal", which is generated by the control unit 142 (FIG. 4), is applied to an input terminal 690. ^{1 If an "O * 1} signal appears at the output of the NAND element 326 and an * I" signal occurs at the input of the terminal, the NAND element 330 is

June 18, 1970 009884/1923

sets and a "1" signal is generated at its output. That NAND gate 332 is switched to the "O" state at the same time. This arises at output terminal 692 the "label end signal" with a "1" level. The generation of the "label of reset signal" will be discussed later in detail described. .

Memory input synchronization unit, Flg. ft, Fig. 12

The "value transfer signal" is transmitted via a terminal 700 from the control unit 142 (FIG. 4) to the first input of a NAND gate 334. At his second entrance the "program counter reset signal" is set via a terminal 702 created. The output of the NAND gate 334 is via a Inverter 336 connected to the input of a NAND gate 338. The latter is crosswise with a NAND gate 340 coupled and thereby forms a blocking circuit. aside from that the output of the inverter 336 is connected to the reset input of an A counter 352. At the output of the NAND gate a "data shift signal" is generated, which can be picked up at terminal 706. At the output of the NAND gate 338, the is connected to a terminal 708, the "data shift signal" is generated. The A counter 352 is reset when an "o" signal occurs at the output of the inverter 3? 6. This occurs when the link condition for the link is not met.

The output of NAND gate 340 is with the first Input of a NAND gate 342 connected to the second Input via a terminal 704 the "cycle 3" signal is applied. The output of the NAND gate 342 is via an inverter 344 connected to output terminal 710. If on Output of NAND gate 340 and at the input of terminal 704 Whenever a "1" signal occurs, a "0" signal is generated at the output of the NAND gate 342, which is generated by the inverter

June 12, 1970 009884/1923

is inverted into a "1" signal, which is called a "data shift pulse" is applied to output terminal 710. Terminal 710 is connected to auxiliary storage register 132, which is shown in Fig. 11 is shown in detail.

The "clock 1" signal is sent to a NAND gate 346 via a first terminal 712, the "fade-out prevention signal" generated by a NAND gate 350 (FIG. 10) via a terminal 714, and the third input terminal 716 A-8 signal from decoder circuit 354 connected to A counter 352 is applied. The A counter 352 is a 4-bit counter which counts the number of "A shifts" produced by a NAND gate 292 (FIG. 7) when the "data shift signal" assumes the logic "1" level . A conventional circuit is used as the decoding circuit 354 which generates an ¹¹ I "signal at an output terminal 724 when the count value eight is reached in the A counter 352. This indicates that the first bit input into the input register 280 is in the eighth Level is located.

The NAND gate 346 generates a "θ" signal when three "1" signals are simultaneously present at its input. If a "1" signal is simultaneously present at the output of the inverter 336, the NAND gate 340 is switched to its "1" state and the NAND gate 338 is switched to its "0" state. This creates a "data shift signal" at the output of the NAND gate 340. The output of the NAND gate 338 is connected to the input of a NAND gate 356, the second input of which is connected to a terminal "J18 , which is connected to a terminal 642 (FIG. 7) is coupled to the NAND gate 292 a "shift

■ felenn
signal A is applied / the link condition for the member 356 is met, a "0" signal is generated at its output, which is inverted by the inverter 358 into a "1" signal and via a line 720 to the value increase input of the A counter 352 is applied. If a "1" signal is applied to this input, the count value of this counter becomes

June 12, 1970 009884/1923

increased by one. With the A counter 352, a de » coding circuit 36O connected to a "1" signal at a Terminal 722 generates when the A counter 552 has a count which is not equal to zero. This indicates that in the input register 128 only the last data bit is available. A conventional comparison circuit 362 is with the A counter 552 and via a terminal 728 ro.lt dem Program counter 400 (Fig. 13) connected. The comparison circle generates a signal at terminal 726 if the two mentioned Counters have the same value, "

The output terminal 726 of the comparison circuit (FIG. 9) is connected to the first input of a WAND element 377 via a terminal 740. A second input is connected to the output of a NAND gate 350 which produces a "Ausblendverhinderungssignal" ¹ Programmsählsigna? PSFG "" This is due to a drdiften Eingahgsklemme 742 ", which from the counter 400 (Fig. 13) is generated" An, an input terminal 744 the "clock 1" signal is applied »The program counter 400 in Fig. 13 is a seven-stage flashing counter, which came up to 128 * The last four stages of this counter are referred to as DSFG stages., The to the terminal Signal applied to 742 is a timing signal that occurs when the program counter 400 has a count between 120 and 127. The NAND element 377 thus generates a "1" signal when the linkage condition is not met at its inputs.

Two NAND gates 368 and 370 (Fig. 10) are crossed coupled with each other and form a blocking circuit. The output of the NAND gate 377 is connected to the first input of the NAND gate 368 connected when the gate 368 in its saturated and the gate 370 in its is open, a "0" signal, referred to as the "shift inhibit signal", is asserted on line 746 generated and arrives at an input of a logic element 368 and to the reset input of a 3-stage

009884/1923 ■ June 12, 1970

Binary counter 378. The "cycle 3" signals are applied to the counter input of this counter via a terminal 754. ^{If an 11} O "signal is applied to the reset input, the counter 378 is reset again. The output of the NAND element 368 is connected to the input of a NAND element 366, at the second input of which is also the" clock 3 "via a terminal 748. If the "slide lock signal" has the value ¹¹ O ", a signal with the level" 1 "is produced at the output of the NAND gate 366.

The ζ output of a flip-flop 380 is connected to the first input of a NAND element 382, the second input of which is connected via terminal 750 to a NAND element 382 in the control unit 142, via which "data value transmission signals" are received. J and K inputs of the flip-flop are not occupied. With its clock input it is connected to the output stage of the counter via a line. The "Clock 1" signals are applied to the C input via a terminal 752. The flip-flop 38Ο remains in its cleared state until the "clock 2" signal assumes the value "1" and the last stage of the counter 378 also has the value "1". The counter 378 is reset when the "shift prohibition signal" is "O". The Q output of the flip-flop 38Ο has the level "1" when the flip-flop is in its cleared state. If the “value transfer signal” simultaneously has the level “1”, an ^{11 O ”signal is produced at the output of the NAND element 282 and an H} 1” signal, analogously, at the output of the inverter 384. If a * "0" signal is present at the output of the NAND element 377 at the same time, the NAND element 370 can be switched into its ^M 0 ^H state and the NAND element 368 into its "1" state. The "shift prevention ^{signal 11} " will assume the level "1." When a "clock 3" signal occurs, a "0" signal is generated at the output of a NAND element 366. After eight "clock 3" signals, which are also sent to terminal 754 of the Counter 378

009884/1923

June 12, 1970

are placed, the last stage of this counter takes the value "1". via the reset input, these are sent from The output of the NAND gate 746 is set to zero. At the exit Q, an "O" signal occurs, which also produces an "O" signal at the output of inverter 384. By the latter, the counter 378 is reset to "θ".

The output of the inverter 384 is connected to the first input of a NAND gate 348, which is cross-connected to a NAND gate 350 and forms a blocking circuit. The signal produced at the output of the NAND element 35O is called the "fade-out prevention signal" and can be tapped at terminal 762. At the output of the NAND gate 548 there is accordingly the "fade-out prevention signal", which can be tapped at the output terminal 764. The NAND gate is switched to the "θ" and the NAND gate 350 is switched to the "1" state when a "1" signal is generated by the inverter 384 and a "θ" signal is generated by the NAND gate 386. The “program counter signal” 120, which is generated by the program control unit, is applied to the NAND element 386 via a terminal 756. The "clock 1" signal is applied to a terminal 758, while a signal which is not "O" is applied to an input terminal 76O, which is connected to the terminal 722 of the decoding circuit 36O (FIG. 9). If the program counter thus has the value 120, the NAND element 386 generates a signal with the level "θ" at the time of the "clock 1" signal at which the last data bit is stored in the input register 28o. A "fade-out prevention signal" with the level "1" appears at the terminal 762 when a "1" signal is present at the output of the inverter 384.

The NAND gate 364 has a first input terminal 766 to which an output terminal 636 of a NAND gate 278 (Pig. 7) is connected from which a "Datenausblendsignal" is generated. The "label end signal" is applied to a second input terminal 768 of the NAND gate 364 from an output terminal 692 (FIG. 8). The outputs of the NAND gates

009884/1923 June 12, 1970

'364 and 366 are at the input of a NAND gate 372. A "1" signal is produced at the output of this NAND element if either the NAND element 364 or the NAND element 366 has a "0" signal. The output of the NAND gate 372 is connected to the value increase input of a 3-stage binary counter 374. If there is a "1" signal at this input is applied, the counter 374 increments a count each time at one. At this time, the inverter 384 generates every time a "1" signal.

The Q output of a flip-flop 376 is with the input an inverter 337 is connected. At the exit of the latter will generates a "program counter reset signal" which is applied to an output terminal 770 arrives. J and K inputs of the flip-flop are not occupied, while the delete input with the "cycle 1" Signal is applied via a terminal 772. The flip-flop 376 remains in the deleted state until the final stage of the counter 374 is switched to the "1" state. If the When eight counting pulses are applied to counter 374, a "1" signal is produced at its output, which signal is fed to flip-flop 376 will. This signal sets the flip-flop, so that a "1" signal is produced at its Q output, which is called "0" signal via terminal 770 to counter 400 (Fig. 13) is applied, whereby it is reset.

If the "label end signal" and the "data fade-out signal" have the level "1", the output of the NAND gate 364 an "o" signal. It is possible that an erroneous "label end signal" will be generated if the stylus 62 is over a container that is intended as a sales item is present ^ is guided or when a label is scanned, which is arranged on a vehicle. Dan "O" signal on Output of NAND gate 364 indicates an "end of label condition" from the stylus. 62 was scanned ^, and that the "data fade-out signal" also has the value "1" a "label end signal" has been scanned, arises at the output of the inverter 384 a "0" signal, since the "value transfer

009814/1923

I2.6.I97O ■■ - =. .; ■■■

38 - 2Ü32240

signal "at the terminal 382 has the value" O " . The" fade-out prevention signal "at the output of the NAND element has a level" 1 ".

The output of the logic element 364 enables new data to be stored in the input register 280 in FIG. 7 after a "label end signal" has been generated (or if a "medium send signal" is generated while scanning another record carrier). This means that no data can be lost if a "label end signal" is generated, which occurs too early or is caused by another error. Data entered into the input register 280 after the occurrence of the "label end signal" circulates in the register 28o and is combined with the previously entered data. The combined data is checked when a second "end of label" signal is generated to determine whether the first was a value signal.

Storage unit _f Fig. 11

The first stage of a 5-bit auxiliary register 132 in FIG. 11 receives "data signals" and "data signals" via input terminals 78O and 782, which are supplied by the output stages of register 280 in FIG. 7 via output terminals 657 and 659. The "data shift signal" from a Klenge 710a in FIG. 9 causes the data stored in the auxiliary register 132 to be shifted in the direction of the output stage. This pulse ■ is applied to the shift input 784. This is generated by the inverter J> kk in FIG. When the auxiliary storage register 132 is filled with data and a "1" signal occurs at the last stage, this is passed to the first input of a NAND gate 390. The "data shift signal" is applied to the second input of this NAND gate via an input terminal 786, which is also supplied by the NAND gate 3 ^ 0 via the output terminal 706 in FIG

8 8 4/1923 12.6 «1970

Signals are present at the input of the NAND gate 390, an "O" signal is produced at its output.

At the first input of a NAND gate 394 is over a terminal 788 is applied the "data shift signal" which is supplied by the NAND gate 338 via the output terminal 708 in FIG will. The second input of this NAND gate is connected to the last stage of the storage register 134, which is also is applied to output terminal 790. If a "1" bit is stored in the last stage of the memory register 134, and a "1" signal is present at terminal 788, the NAND gate 394 generates a "θ" signal which is fed to a NAND gate 392 will. The second input of this NAND element is connected to the output of the NAND element 390. The output signal of the NAND gate 392 is through the NAND gate 390 controlled when new data is entered into storage register 134 become, 'and from the NAND gate 394 if the foregoing inputted into the storage register 134 in circumnavigate this.

The output of the NAND gate 392 is with the input of the register 134, in which one bit is entered each time can be when a "1" signal occurs at the output of the NAND gate 392. Conventional Conversion circuits are provided which convert the input and output signals into desired logic signals can turn back.

Comparison unit, FIG. 12

The comparison circle in Fig. 12 accomplishes two tasks Fulfills. First, the "code section bits" stored in the auxiliary storage register (Fig. 11) are rearranged with the and inverted count in the last four stages of program counter 400 in FIG. 13 are compared. The program counter 400 is a 7-bit module 128 counter. It consists precisely taken from a modulo 8 and a modulo 16 counter, where the modulo 8 counter from the first three stages or the

009884/1923

June 12, 1970

A, B and C stages and the modulo 16 counter from the last four levels or the D, E, F and G levels. The value in the auxiliary memory 132 and the value in the modulo 16 counter part of the program counter 400 are compared to the data from the storage register 134 in the output register 148 to one to be able to carry out a certain period of time.

It is assumed as an example that the "code section" has the value 1011, which is the decimal number eleven. Since it can be assumed that every location in the code section can represent two values, the code section 1011 mentioned as an example represents practically 22 digits of four each Bits, so that a total of 88 bits result. In addition to the 88 information bits, there are twelve more bits in recorded in decoded form on the label shown as an example. These consist of eight "code section bits", two direction bits and two parity bits. The total sum. of the bits recorded on the label is thus 100. Of these 100 bits, five bits are stored in auxiliary storage register 132 and 95 bits are stored in storage register 134.

To bring the first sampled bit to be decoded into the output stage of storage register 134, the data in memory must be shifted towards the output stage of memory register 134. The shift must take place over 128 minus 95 = 33 places, after the program counter 400 has been reset. Every time the data in memory I30 increases by eight levels shifted towards the output stage of the storage register 134 the modulo 16 part of the program counter is increased by the value "1". After the information by 32 digits was shifted, the modulo 16 counter part gives way to the position 0010.

The one in the modulo 16 counter part of the programmer 400 The value contained represents the shifted and inverted value of the "code section" in the auxiliary storage register I32 By comparing those in D, E, F and G

June 12, 1970 009884/1923

Levels of the program counter values with the shifted and inverted value of the in the auxiliary storage register The time for the transfer of the data from the storage register 134 to the output register 148 is specified in the stored “code section”. In the present example this transmission begins after 33 bit times in the one described here For example, it is not a problem that the logic leads one bit each time when the Data from the output register 148 into the data processing system 114 the first bit is ignored in each case. -

The first five bits which are stored in the output register 148 are the first group of a "code section" which were read from the label 20. The last five bits that are stored in the auxiliary storage register 132 represent the values sampled by the second code section.

The comparison unit in FIG. 12 then compares the information stored in auxiliary storage register 132 with that in output register 148.

The outputs from the NAND gates 101, 103, 105 * 107 and 109 in FIG. 12 are connected to the inputs of a NAND gate 111. This generates an output signal with the level "0" ^ if at its input only ^w l "signals are present. The output of the NAND gate 111 is connected to an inverter 113, which generates a comparison signal with the level" 1 "which is sent to the Output terminal 800. _v ■ ■

The outputs of the NAND gates 115, 117, 119 and 121 are connected to the inputs of a NAND gate 101. At the first input of the NAND gate 115 is a terminal 802 a "wrong side" signal from stage B of the Auxiliary storage register 132 is created. This entrance is with "A.R. Level B". To the second input terminal 8θ4 a "wrong side" signal is asserted from stage G of program counter 400 of FIG. This is with "P.C. Level G" ■ ' designated. With a third input terminal 8θβ is the

009884/1923

June 12, 1970,

- ⁴² - 2Ü32240

Kontrollelnhelt 142 from Pig. 4 connected to an "E" signal supplies. This signal is a clock signal that occurs when the one in the counter 400 with the one in the auxiliary storage register 132 Value is to be compared "

The "correct side" signal from stage B of the auxiliary storage register 132 and the "correct side" signal from stage G of the program counter 400 are applied to the inputs 808 and 810 of a NAND element 1.17. The signal "E" is also present at the third input. . The Bedingungsfunkti on for this NAND gate can be seen from the foregoing explanations. If the values stored in the auxiliary storage register 132 and the shifted and inverted values in the program counter 400 are equal and the "E" signal is present, the NAND gates 101, 103, 105 and ΙΟΥ generate a "1" signal.

Fii 1 fs

The information stored in / storage register I32 are shifted based on the information stored in output register 148. As in the described above, the scanning direction of the label is taken into account. The input terminal is connected to the NAND gate II9 808 the signal "correct side" obtained from stage B of the auxiliary storage register is applied and to the input terminal 812, the "wrong page" signal derived from stage D of the output register is applied. That from the exit of the register 148 derived signal becomes "O.R. stage D signal" called. The "wrong page" signal from stage B of the auxiliary storage register is sent to NAND gate 121 via terminal 802 132 created. The "right side" signal from the Level D of output register 142 occurs at terminal 814 » An "F" signal is applied to terminal 816 on NAND gates II9 and 121 «This signal is a time signal, the appears when the in auxiliary storage register 132 with those values stored in output register 148 are to be compared. If the 'values stored in the auxiliary storage register 132 and in the output register 148 are the same, and the "P" Signal is present, occurs ao the outputs of the NAND gates

009884/1923 June 12, 1970

101, 103, 105 and 107 have a "1" signal.

The "F" signal is also applied to a NAND element 109 via a terminal 818. The second and third input of this NAND gate is connected to the outputs of the NAND gates 123 and 125, via the input 820 a "correct page signal" is sent to the NAND gate 123 from stage A of the auxiliary storage register 132, and to the Terminal 822 applied the "wrong page" signal from stage E of auxiliary storage register 142. A "wrong side" signal from stage A of auxiliary storage register 132 and a "correct side" signal from stage E of output register 142 are applied to terminals 824 and 826 of NAND gate 125 Stage E of output register 142 hold the "direction bits". As can be seen from the figure, the two direction bits have the same logical value, depending on whether they represent a "start bit" or a "stop bit". Both "direction bits" must be either "1" bits or "θ" bits. Therefore, an output of the NAND gate 123 or 125 will have a ¹¹ O "signal and the output of the NAND gate 121 will have a" 1 "signal, since both direction bits have the same logic level.

If the direction bits do not have the same logical value, an ¹¹ I "signal is produced at both outputs of NAND gates 123 and 125 if the" F "signal at terminal 818 has the value" 1 "and at the output of NAliD element 109 is "O." A comparison signal with the value "θ" is generated by the inverter 114 when the direction bits are different, that is, when they have the opposite logic level The code weight of the inverted bits in this register increases in direction B, C, D. The direction blt in output register 148 is stored in the "E" stage of this register. The code weight increases in this register in the direction of the stages D, C, B and A as well.

».6.1970 00988V / .1923

Program counter unit, Flg. 13th

The program counter 400 in FIG. 13 is connected to the output of an inverter 404. To the input of the inverter "Cycle 3" is applied via a terminal 130. The program counter 400 increases its value every time a "θ" signal occurs at the output of inverter 4o4. The output of the inverter 337 is via the output terminal 770 in FIG. 10 with the Input terminal 132 connected, which is the reset input of the Counter 400 represents, and this resets when a "0" signal occurs at this terminal.

406 through 422 are conventional decoding circuits that implement the Evaluate the count of the program counter 440. At the decoding circuits 406 to 422 there is one output each then a "1" signal when the counter 400 has a certain count value. The decoding circuit 422 decodes the D, E, F and G stages the program counter 400 by a "program counter signal D, E, F, G "which indicates that all stages of the program counter 400 are in the" 1 "state. The decoding circuits 412, 414, 416, 418 and 420 are assigned to levels A, B and C, and the decoding circuits 4o6, 408, 410 and 422 are assigned to all stages of the program counter 400 .

Parity check unit, Fig. 14

By interconnecting flip-flops 440 and 442 in FIG. 14, a conventional modulo 3 counter is formed. The "Increment 0 signal" is sent to the Clock signal inputs of the two flip-flops applied. A parity reset signal the level "0" is applied to the reset inputs of the two flip-flops via an input »klenune 842, which is supplied by the control unit 142 of Fig. 4. The flip-flop 440 is a code weight "1" and dsm flip » Flop 442 is assigned a code weight "2". The two flip-flops can never be in the same state at the same time

009884/1923 June 12, 1970

can be set, since the reset occurs when it occurs of count two is made. A "preselection signal O" reaches the flip-flop 442 via an input terminal 844 and sets it to the set state when a parity check is carried out should be made and if the in the auxiliary memory register 1J52 and the data in the output register 148 have the same value. 448 is a conventional comparison circle, which generates a "1" signal when a "0" signal is applied to input terminal 848 and the flip-flops and 442 the same count as flip-flops 444 and 446 exhibit. Flip-flops 444 and 446 operate in the same manner as flip-flops 440 and 442. To terminals 848 and the value increase signal becomes "1" and the preset signal "1" created. The flip-flop 442 is preset when the "first direction bit" or the "start bit" is deemed to be an "O" bit has been detected and the flip-flop 446 is preset if the "first direction bit" was recognized as a "1" bit. Flip-flops 444 and 446 are reset by the reset signal appearing at terminal 852.

Output Register, Figures 15A and 15B

The complete block diagram of the output register is shown by combining FIGS. 15A and 15B along the lines of FIG Line 15-15 formed.

From the memory register 1 ^ 4, the data is stored in the Output register 148 transferred. The data can vary depending on the scanned and recognized information into the Output registers are entered. Depending on whether the label from the hand-held stylus 62 is in forward or is scanned in the reverse direction, place the in the output register 148 entered data, on the one hand the regular and on the other hand the complementary values of the recorded This is why the data is transferred from the output register depending on the scanning direction when it is transferred

₁₂ .6. ₁₉ 70 009884/1923

shifted into data processing station 114 (Fig. 2) in either a forward or a reverse direction.

The output stage of the memory register 1} 4 in Fig. 11 generates a "memory output signal" which is applied via a terminal to the input terminal 860 of a NAND gate 424 in Pig «, 15A. The “register forward signal” is generated by the control unit 142 in FIG. 4 and applied to the second input 862 of the NAND gate 424. The "register backward signal", which is likewise generated by the control unit 142 and has the value "0" when the "register forward signal" has the value "1", is applied to a NAND gate via a terminal 864. The outputs of the NAND elements 424 and 424 are thus opposite and both are at the inputs of a NAND element 428. An "O" signal from the storage register generates a "0" signal at the output of the NAND element 428. A "1" signal from the output d6s of storage register Ij54 produces a "1" signal at the output of the NAND gate 428 when data is input to the output register 148.

The output of the: NAND gate 420 is via an inverter 4j5O is applied to the K input of a flip-flop stage 4j52. The J input of the flip-flop is directly connected to the output of the NAND gate 428 connected. The clock input is with the "Register clock signal" applied via a terminal 866, the is generated by the control unit 142. When a "0" signal from the storage register 1J54 to the first input of a NAND gate 424 is applied and a "l" signal as "Register clock signal" is present at the same time, the flip-flop is cleared. If on the other hand at the output of the memory register 1 ^ 4 a "1" signal occurs, the NAND gate 428 will generate a "1" signal, whereby the "register clock signal" is simultaneous is present, the flip-flop 4 ^ 2 is set. This occurs a corresponding signal at the Q output.

The remaining seven stages of the output register are constructed in the same way. In the one thus formed Shift registers can move the entered data towards the

June 18, 1970 009884/1923

20322A0

Flip-flop stage 441 are shifted. The last Fljfcflopstufe has only one NAND gate, there is a NAND gate for introduction a data shift in the reverse direction is not necessary 1st, because the information entered in this stage can only be shifted in the forward direction.

The first input of a NAND gate 4j54 in Fig. 15B is connected to the Q output of the flip-flop stage 441 while on its second input via a terminal 862 the "register forward signal" is created. The ζ output of the flip-flop stage 4J2 is connected to the first input of a NAND gate 4j6. The "register backward signal" is applied to the second input of this NAND gate. The outputs of the NAND gates 4J4 and 4) 6 are with the inputs of a NAND gate tied together. There is a "data output signal" at output terminal 868 with the level "!", if either at the output of the NAND gate 4j> 4 or a "θ" signal at the output of the NAND gate 4} 6 occurs. This output signal is fed to the data processing unit 114 in FIG. 2.

When the "register forward signal" has the level "1" and the "register backward signal" has the level "o", data are supplied from the output register 148 to the data processing unit 114. This is done by shifting the data in the output register from flip-flop 4] J2 in the direction of flip-flop 441. The value stored in the flip-flop 441 determines the output state of the NAND element 454, which determines whether a "0" signal or an "1" signal is produced at the output of the NAND element 4j8. When the stylus 62 has crossed the label 20 in the reverse direction, the data must be transferred from the output register 148 to the data processing unit 114 in reverse order. Therefore, the "register down signal" has the level "I" and the "register ^{forward signal 11" has} the level "0." As a result, the data stored in the output register 148 are transferred from the flip-flop stage 441 in the direction of the flip-flop stage 4 ^ 2. At this moment, the state is determined the flip

12. ₆ . ₁₉ 7O 009884/1923

flops 4 ^ 2 the output state of the NAND element "436 _β and thus the output state of the NAND element 438. Thus, the complement of the information read in reverse direction can be picked up at the terminal of the flip-flop" 432. which is connected to the <§ output. Through the connection with the Q output, the complement is formed automatically during the transfer. .

Control unit, flg. 16 and 17

ψ The output of the inverter 337 is connected to the first input terminal of a NAND gate 502 in FIG. 16 via an output terminal 770 in FIG. The latter generates the "program counter reset signal". The "label end signal" is applied to the second input via a terminal 882 of FIG. If "1" signals are present at both inputs, the NAND gate 505 generates an "O" signal which is applied to the output 884 as a "parity reset signal". The "program counter signal 7" is applied to the first input of a NAND element 504 via an input terminal 886 from the decoding circuit 416 in FIG. 13, while the "comparison signal " is applied to the second input via a terminal from the output terminal 800 in FIG. is created. At the output of the NAND gate 504 is at the beginning

' generates a "1" signal, since the "comparison signal" ¹ from the inverter has the level "0", unless either the "E ^ft signal or the" F "signal from the control unit 142 in Pig The "E" signal assumes a level "1" earlier than the "F" signal. As soon as the "E" signal assumes the level ^M l ^w , the The comparison circuit in FIG. 12 compares the bit located in the auxiliary storage register 132 and the count value of the program counter 400 in order to control the transfer of the data from the storage register 13 ^ to the output register 148 in the manner described above.

009884/1923

12; 6.1 970

A NAND gate 506 is cross-coupled to a NAND gate 508, whereby a trap circuit is formed. The first input of the NAND gate 506 is connected to the output of the NAND gate 502. The second input of the NAND gate 508 is connected to the output of the NAND gate, while the first input is connected to the output of the inverter 510 i & FIG. 17 via a terminal. The "transfer _value signal" is sent to this input. This signal initially has the level "1". ^{A 11} I ¹ V signal is also generated at the output of the NAND element 504 at the beginning, since the "comparison signal" at the terminal 888 has an "O" level at this time. If the outcome of the NA ^! ND element 502 has an "O" signal at the same time, the parity counter flip-flops Λ40 to 446 in Fig. Are reset, and the NAND element 508 is in the "0" state and the NAND element 506 in the "1" state set »The" E "output signal at a terminal 892 now has a" 1 "signal. ■

If the "value ^{transmission signal u} " assumes the ■ "0 ^ir level, the sampled decoded and recognized as value data." If now at the same time at input terminal 888 ■ the comparison ^{signal 11} and at input terminal 896 the "program counter 7 signal" the level " l ", an" o "signal occurs at the output of NAND element 504, and if the" program counter reset signal "at terminal 88Ο also has an ¹¹ O" level at the same time, * at the output of NAND element 502 a " 1 "signal. As a result, the NAND gate 506 is set to the" 0 "state and the NAND element is set to the" 1 "state, whereby the" E "signal at the output terminal assumes the level" 0 ".

With the first input of a NAND gate 512, the output of the NAND gate 506 is also connected, to the The second input of this element is via terminal 894 generated by the NAND gate 152 and to the output terminal 800 (Fig. 12) applied "comparison signal" applied. To the

■■:. ■■■ 009884 / 1S23 June 12, 1970

third input is '* I3 ^B generated ProgrammsMhler applied to the decoding circuit 6X4 -in 6 signal. "Thus, when the Progpammgänler' via di © input terminal 896 which of 4OQ reaches the count of six, the ⁿ E ⁿ signal at the terminal and ^a ¥ ergleiehssignal ⁿ aa el @ ^ © IClerosa 89 ^ © each inen ¹¹ I "level have ^ NAND gate 512 is a '' O ¹¹ may generate signal.

A NAND-Gliod 51% is tex-euswoise connected to © iraem NAND-member 516, w @ Äretr @ ia Sgoxrkreis is formed. In the input of the NAND element 516, via © in © terminal, the code from the D®codierta§! S 4ö6. ta FIg ₀ 13 generated "program counter signal OÖO applied _o Ifeön of the» program counter 400 is not reset ^ isti? a aa d £ © liag®agskl © roai © of the MAMD element 516 from the DeeoäS. © ste © is% O6 the "Tekt 3 ⁵⁸ signal with a "1" level applied, lisa ^w 0- ^w signal wi? Ä applied to the input of the lfIlB »member @ s 51% ¥ © sn iteggiag ö» s MÄMD member to whom the ⁵⁵ I ⁵⁸ Sigaal yaä äas "forglelchssignal" -gleichiseifcig © inea ^iS O ^K F © g © l uf ^ 3®lB <BU .and when the program counter 400 to _ZHsi? iSFiä s © ehs has. As a result, the NAND element 516 la ä © a ^w 0 ^M Ziastand w & d the NAND element in the "1" Ziisfcaaä gosefeat ^ woäurefe eia ¹¹ I "" signal at the output terminal 900 erselieinfeo

The output of the NAND gate 52% is connected to the inputs of the NAND gate 518 and 520. The "clock 1" signal also arrives at <ä © n NAND elements via the input terminal © 902 _o lia ineltew ^ the input of the NAND element 5X8 is connected to the output © ines inverter _522 ^{Another limgaag of the NAND element 520, the “program counter signal} generated in the decoding circuit 4X2 in FIG.” is applied via a terminal 904. The “parity lock signal” ara output of the NAND element 5X4 remains at its “1” level as long as it is ⁿ Pri%? atii6izählerlgnal ⁿ (5ÖÜ a level "0 ^M and the signal at the output of the NAND element at the same time a level ^W 1 ^M

X2.6.1970

A NAND gate 524 is cross-coupled to a NAND gate 544, thereby forming a trap circuit. The output of the NAND gate 53 ¹ * is connected to the input of the NAND gate 524. Another input of the NAND element * 526 is connected via a terminal 906 to the data processing unit 114 in FIG. 2, which applies a "general reset signal" to this input. At the beginning, before a label is scanned, the NAND gate is in a V state and the NAND gate 526 is in the "1" state. At the beginning there is thus at the output of the NAND element 526 a "Codler comparison signal" with an "1 ^M level, which is sent to the line 908. The corresponding inverted signal is produced at the output of the NAND element 524 and arrives at the line 910 The output of the NAND element 526 is connected to the first input of a NAND element 528. The "program counter 0 signal" generated by the decoding circuit 418 in FIG. 13 is applied to its second input via a terminal 928. The NAND element 528 generates a ¹¹ O "signal which is inverted by an inverter 522 when the" program counter 0 signal "supplies a" 1 "level and the NAND gate 518 also supplies a signal with a" 1 "level. The “program counter 1 signal” applied to the NAND element 520 has a “0” level when the “program counter O signal” at the input of the NAND element 528 has a “1” level. During this time there is a "1" signal at the output of the NAND element,

A NAND gate 530 crosses with a NAND gate coupled, whereby a trap circuit is formed. With the first The input of the NAND gate 530 is the output of the NAND gate tied together. The exit of the * NAND element 520 1st rides an entrance of the NAND gate 532 coupled. Thus, there is a connection between the inverter 510 in Fig. 17 via an input terminal 914 with the NAND gate 532, to which the "value transfer signal" is created. When this signal has a "1" level and the NAND gate 520 generates a "θ" signal and an "O" signal is also sent to input terminal 914

009884/1923

June 12, 1970

is set, the NAND gate 532 is set to the "O" state. At the same time, the NAND gate 530 is set to the "1" state, as a result of which at the output terminal. 916 an ^M F "signal arises.

A "comparison signal" is applied to the NAND gate 534 via a terminal 918, which is generated by the inverter 113 in FIG Pig. 12 is generated and indicates that the 132 is equal to the value stored in the output register, while the "F" signal is a "1" Level, via the input terminal 920 is on. the NAND gate 534 applied the "clock 3" signal »Another The input of this NAND element is connected to the output of the NAND element 530 connected. Since the "general reset signal" at the terminal 906 has a "1" level at the beginning, becomes the NAND gate 526 to the "©" state and the NAND gate set to the "1" state. A “coding comparison signal” with the level “1” is produced on line 910.

The output of the NAND element 524 is connected to the input of a NAND element 527 which has a second input to which the “parity comparison signal” from the comparison circuit 448 in FIG. 14 is applied via a terminal 922 is satisfied for a NAND gate 527, a "θ" signal is produced at its output, which is sent to the line 924 as a "data incorrect signal". At the same time it arrives at an inverter 531 * which generates a “data correct signal” with the level “1”, which arrives at line 926.

The output of the inverter 531 is connected to the first input of a NAND gate 533. The "program counter signal" I27, which is generated by the decoding circuit 408 in FIG. 13, is applied to the second input of this NAND element. The "cycle 3" signal is sent to the fourth input. If a "1" signal occurs at the output of the inverter 53I, a "parity ^{lock signal 11 is} generated at the output of the NAND element 533, which signal has the level" 1 "and which is sent via a terminal 932 as a" data correct signal "to an input terminal 934 of a NAND Member 535 in Fig. I7 is applied.

009884/1923

June 12, 1970

The NAND element 535 is cross-coupled to the NAND element 536, as a result of which a blocking circuit is formed. The "general reset signal" from the data processing unit 114 is fed to the NAND element 536 via a terminal 938. When this has the level "1", the NAND gate 536 is switched to the "O" state and the NAND gate 535 is switched to the "1" state. The "data correct signal" at terminal 934 must, however, have a "0" level at the same time. At the output of the NAND gate 535 a "1" signal is produced, which is fed to the output terminal 940 as a "data correct blocking signal". The output of the NAND gate 536 is connected to the input of a NAND gate 538, to whose second input a Q signal from a flip-flop 546 is applied. ^{If an 11} O "signal is present at the output of the NAND element 536 and a" 1 "signal is present at the output of the NAND element 538, a" 0 "signal is produced at the output of the inverter 5IO, which is used as a" data value signal "at an input terminal 942 The "data value signals" are picked up at an input terminal 944, when data representing real values are scanned from the label 20. This signal prevents newly scanned data from reaching the memory 130 until the previous one scanned data still in the memory were fed to the data processing unit in FIG. 2.

The K input of flip-flop 546 in FIG. 17 is connected to ground. The "black signal" is applied to the J input via terminal 946. This signal is generated by the decoding unit 126 in FIG. The “white signal”, which is also supplied by the decoding unit 126, arrives at the erase input C via a terminal 948. Is applied to the clock input via a terminal 950, the "Ubertragungsendesignal" from the terminal 682 in Fig. 8. When the first white color strip is scanned, the flip "appears at the input C flops 546, a" white "signal with the level of ¹¹ O ', by this signal clears flip-flop 546. When the stylus

009884/1923

June 12, 1970

is removed from a currently scanned label 20 * is ^"5 applied black signal ^'1 with the level ⁸⁹ I' the same on Talcteingang the flip-flop appearing at terminal 950" via the input terminal 946 to the J input of the Plipflops a ⁿ end of transmission signal likewise with a Level "1 ^{! 8} " These two signals wtvu set the flip-flop "At the output there appears an ⁿ Q ⁿ signal which is fed to an IAMD ™ circuit 538" At the output of this NAMD element there is a "1" signal which is converted into an ⁿ Q ⁿ signal by the inverter ¹ 510. This signal is present at the terminal 942 as a "value transfer signal".

^{A program counter signal 127 W} generated by the decoding unit% 08 in Pig _o 13 is fed to a NAND element 542 via <stae FtQgangsklerame 928. ^{The "falfc 3 M} signal" is applied to a further input via a terminal 930. The 'third input is acted upon with the'"Parltätssperrsigna} ⁸⁵ , which is transmitted to the line 924 by the NAID element 514 © rseugt wirö _{a tfees"} HAND gate 542 außeräeii as & Datenlnkorrektsignal ⁿ "supplied. Menu this signal has the level ^8S O ", the NAND gate 542 generates a" 1 "signal» Ds at the "value transmission signal" at the terminal 952, at the beginning also has the level "1", appears at the output of the IAIB-ßliedes' 540 an ¹¹ 0 "signal when data is sampled from the tag 20. This signal is converted into a "1" signal by an inverter 544

that
converts, ie / 3as "EtlkettenderUcksetzsignal" .at the output terminal 954._When a "0" signal occurs at the output of the NAND element 542 and the "value transfer signal" has the level "1" at the same time, this also occurs at the output terminal 954 a "0 ^IF signal, which indicates that the" label end signal "was an error signal. The" label reset signal "is connected to terminal 690 in FIG. 8. The output of NAND gate 526 is connected to an inverter 548, the output of which is in turn coupled to the input of a NAND element 550. A connection is established with the second input of this NAND element via terminal 9I6

I2.6.I970

with the first stage of the auxiliary storage register 132 in Fig., through which the "direction bit" is transmitted. The "0" signal produced at the output of the NAND gate 526 is converted into a "1" signal by the inverter 548. If the "direction bit * ^{1" has the level "1", an 11} O "signal is produced at the output of the NAND gate 550.

The NAND gate 552 is cross-linked with the NAND gate 554, whereby a trap circuit is formed. The output of the NAND element 550 is connected to the input of the NAND element 552; the "general reset signal" is fed to the NAND element 554 via a terminal 958. If the "direction bit" and the "general reset signal" are present at the same time on the NAND gate 554, this is set to the "0" state and the NAND gate 552 is set to the "1" state. At the output of the NAND gate 552 there is a "reverse blocking signal" with the level "1", which can be picked up at the output terminal 96O. At the output of the NAND gate 554 there is a "reverse blocking ^{signal 11} with a level" O ", which is applied to the output terminal 962. If the" direction bit "has a" 0 "level, the NAND gate 552 switches to" O "and the NAND gate 554 is switched to the "1" state, as a result of which the two signals appearing at the terminals 960 and 962 change their levels.

The "direction bit" is applied to an inverter from the auxiliary storage register .132 in FIG. 11 via an input terminal 964. The output of inverter 556 is with the first input of a NAND gate 558 connected. At one Another input of this NAND element is the "comparison signal" from the output terminal 800 of FIG. 12 via a Input terminal 968 applied. This signal becomes that Result of comparison between the value of the program counter and the value stored in the auxiliary storage register 132 shown. A third input of this NAND element is via an input terminal 970 with the decoding circuit 412 of the

June 12, 1970 009884/1923

Pig. 1J5 connected. This circle generates a "program counter signal". The "E" signal is applied to a fourth input terminal 966. If the value contained in the stages D, E, P and G of the program counter 400 is the same as the value stored in the auxiliary storage register I32, and the "direction bit" has an ¹¹ O "level, the NAND gate 558 generates a" preselection signal 0 ". which reaches the output terminal 972.

The "direction bit signal" arrives from the auxiliary storage register 132 to the first input terminal of a NAND gate 560. The other inputs of this NAND gate get over terminals 974, 976 and 978 have the same signals as on the corresponding terminals of the NAND gate 558. The Signals generated at outputs 972 and 980 thus behave in a complementary manner to one another. If the "direction bit" denotes the Level "1", there is an "O" signal at the output of the NAND element, and a "1" at the output of the NAND element 558 Signal. These two signals reach the inputs 85O and 844 of the flip-flops 442 and 446, through which the parity check of the memory unit I30 in a prescribed manner is done via an input terminal 982 to an inverter 562 data from storage register 1J4 in FIG applied via an output terminal 790. The output of the inverter 562 is connected to the input of a NAND gate 566 tied together. The "clock 1" pulse is sent to another input of this NAND element via an input terminal 984

created. The input terminal 986 is connected to an output terminal 900 of FIG. 16, so that the NAND gate the "parity lock signal" can arrive. The input of a NAND gate 564 is via a terminal 982 with the output stage of the memory register 1 ^ 4 connected. The second entrance this NAND element receives the "clock 1" signal via the input terminal and via a third input terminal 990 that comes from the output terminal 900 in FIG. 16 "Parity lock signal.

12.6.197c 009884/1923

If an "0" bit is stored in the last stage of the memory register, the NAND gate 564 generates a "1" signal. At the same time, an "0" signal is produced at the output of the NAND gate 566 during the time of the "clock 1" signal, when the "parity ^{lock signal 11 has} a" 1 "level. When a" 1 "bit is stored in the output stage of the memory register is, an "0" signal is produced at the output of the NAND gate 664 and a "1" signal at the output of the NAND gate 566. The output of the NAND gate 564 is connected to the input of an inverter 568, and through the on This NAND element is inverted and is present at the output terminal 992 «. This signal is called the“ increment signal. ”The output of the NAND element 566 is connected to an inverter 570, which supplies an“ increment signal ”to the output terminal. The output of the inverter is connected to the clock inputs of the flip-flops 444 and 446 via the terminal 992. The output of the inverter 570 is connected to the clock inputs of the flip-flops 440 and 442 via the output terminal 994.

The output of decoder circuit 420 in FIG. 13 is connected to a NAND gate 572 via an input terminal 996, whereby the "program counter 0-5" is sent to it. is created. This signal indicates that levels A, B and G of program counter 400 from zero to have counted five. To the second input of the NAND gate the "comparison signal" is sent via a terminal 998 from the Inverter 113 in Fig. 12 is applied. In the present case this has a "1" level when the D, E, F and G of the program counter 400 with interpreted values the values stored in the auxiliary spelcher register I32 matches. An input terminal 1000 is used to connect to the NAND gate 572 applies the "E" signal from the output of the NAND gate in FIG. At the output of the NAND gate 572 arises thus a "0" signal when the "program counter signal 0-5"

June 12, 1970 009884/1923

has an ¹¹ O "level and a comparison has been made between the D, E, P and G stages of the program counter and the values in the auxiliary storage register 132, as a result of which a section of code was transferred from the storage register 1354 to the output register I38. The output of the NAND -Glee 572 is roughly connected to the input of a NAND gate 574 ^, the "register forward signal" at the output terminal 1002 @rzeygt _o

^{The "Hegisterladesignal 118"} from the data processing unit is applied to the MAND element via an input terminal 1004; the "DatenlcorrektverriegelQlungssignal" from the NAND element 535 is applied to the same NAND element via a second input element 1006 via the output terminal 940. At the output of the IAND element 573 results in an ^M 0 ^M signal and at the output of the NAND element 57% an ¹¹ I "signal, which is called the" register forward signal ", when Bn the two inputs of the NAND element 573 a ⁹⁸ I ' ⁸ SigfSiO. is present. In this case, the data stored in the memory register 134 are transferred to the output register 148.

Via a terminal I008, the "reverse blocking signal" is applied to the NAND element 576 from the output terminal 962 of the pig 16 '. To a second input of this NAND-. Link is from the data processing unit 114 in Pig. 2 via an input ^{terminal, 1010 the st} tfto @ rtragungssignal "is applied. A third input of this element is connected via an input terminal 1012 to an output terminal 940 of the NAND element 535, whereby the" data correct lock signal "is applied to this. If the output register 148 is correct has been loaded, the data processing unit supplies a transmission signal with the level "!" to the NAND gate via the terminal 1010. If the "Richtußgsbit" is a "θ" bit and the "reverse blocking signal" at the terminal IOO8 has a level "1 "is produced at the output of the NAND gate 576

a "

I2.6.I97O

a "0" signal and a "1" signal at the output of the NAND gate 573. The output of the NAND gate 962 in FIG. 16 is connected to a first input of the NAND gate 578 via a terminal 1014, whereby the "reverse blocking signal ^{11 is applied} to this NAND gate. A second input is received via an input terminal 1016 from the data processing unit 1014, the "transmission signal", "via an input terminal 1018 is also applied from the NAND gate 535 through an output terminal 940 the Dat ¹¹ enkorrektsperrs ignal" to the NAND gate 578th The output of the NAND gate 578 is connected to the input of an inverter 580, which generates a "register reverse signal" at its output, which is applied to the output terminal 1020.

If an "1" signal is applied to output terminal 1002 and the "transmission signal" is also one has logic level "1", the data stored in the output register are transferred from the input stage in the direction of the Output stage shifted. If the "register down signal" is present at the output terminal 1020 and the "transfer signal" has the logic level "1", and the "data correct signal" is also present with a level "1", the values of stored in the output register 148 become the output stage moved towards the input stage. Thus, each stored in the output register 148 can Data in a left-to-right direction or be shifted in a right-to-left direction, je according to which direction the stylus 62 is guided over the label 20. .

The output of the NAND gate 574 is with the input a NAND gate 5 & 2 connected, the second input via terminal 1022 receives the "cycle 1" signal. The output of the inverter 58O is connected to an input of the NAND gate 5 & 4, at its second input via Klemx.e 1022 as well the "cycle 1" signal is applied. The outputs of the

009-884 / 1923

June 12, 1970

NAND elements 582 and 584 are connected to the inputs of a NAND element 586. If both outputs of the NAND elements generate a "1" signal, an ¹¹ O "signal is produced at the output of NAND element 586 and is sent to terminal 1024 The output signal at terminal 1024 is called the "register clock signal" and is applied to the flip-flops of output register 148 in Figures I5A and I5B.

June 12, 1970 009884/1923

Claims (1)

- ■ 61 - Patent claims . (T7. Apparatus for serially scanning data represented on a record carrier by three different adjoining areas and means for decoding the scanned data, characterized in that each area in the scanning direction is different from each preceding area, and that each transition between the recognizable areas represents binary information, and that a transition in the scanning direction from a first to a second, or from a second to a third or from a third to a first area a first binary information and a transition in the scanning direction from a first to a third, or from a third to a second or from a second to a first area each represents a second binary information item. 2. Device according to claim 1, characterized in that that the data is in the form of a word on the record carrier are recorded containing first and second code sections characteristic of the length of this word, which occupy the same relative position with respect to a corresponding end of the data word, and that the information bits contained in the second code section have a reverse sequence with respect to that in the first code section have recorded information bits and form the complement to these. 3. Device according to claim 2, characterized in that that the recorded data word contains two parity bits, which are selected so that the total number of binary "!" in the data word congruent modulo j5 to the total number of the binary "O" is in the same data word, and that each 6/12/1970 009884/18 * 4 Parity bit occupies the same relative position with respect to the corresponding end of the recorded data word . 4. Apparatus according to claim 3 # _s characterized in that the second and thirds recognizable range © are displayed on a background ,, which forms the "first recognizable range, and CiÄ as in a · first, Dept. t direction of the first ascertainable by transition © in © a first and a second area, and when scanning in the opposite direction the first detectable transition is formed by a first and a third area, 5. Device according to. In one or more of the preceding claims, characterized in that the scanning and decoding device contains a scanning circuit (115) which has three output terminals _f and 'which is constructed in such a way that one of the scanned areas is connected to a corresponding output terminal derived signal occurs, and that a decoding circuit (126) is provided which has three input terminals corresponding to the three output terminals mentioned and contains a memory device (210, 214, 218) which is connected to the three input terminals, the arrangement being constructed so that due to a scanned area a signal occurs at one of the corresponding input terminals, which is stored in a corresponding memory part until a signal occurs at another of the input terminals mentioned and is stored in a corresponding other memory part, and that the decoding circuit (126) Contains links (226, 2 ^ 8, 258, 262) that mi t are connected to the stores (210, 214, 218), as a result of which they generate binary output signals in accordance with the information stored on the record carrier by area transitions. Ί
June 12, 1970 6. Apparatus according to claim 5 »characterized in that that the output signals of the logic elements (226, 238, 258, 262) are placed in a memory (130). 7. Apparatus according to claim 6, characterized in that a clock pulse source (127) is provided, by the clock signals of which a program counter (400) is incremented, and that the memory (130) contains a storage register (134) which has the same number of stages as . has the program counter (400) and is constructed as a circulating shift register which progressively is incremented by clock pulses derived from the clock signal source (127). . 8. Device according to one or more of the claims 2 to 7 »characterized in that a detector circuit (138) is provided which generates an output signal when all of the data recorded on the recording medium (20) is scanned were, and that a comparison circuit (147) is caused by an output signal of the detector circuit (I38), initiate a comparison in which a memory (I30) Stored code section with part of the program counter content is compared, and that depending on this comparison, the comparison circuit (147) an output signal .generated by which the transmission of the in the memory recorder (134) stored data in an output register (148) is effected. 9. Apparatus according to claim 8, characterized in that the detector circuit (138) contains a first counter (310) which is incremented with pulses of a first frequency and that the detector circuit (I38) contains a second counter (3l8), which with a second lower frequency is applied, and that the content of the first counter (310) as a complement in the second counter (318) Θ0988Α / Τ923 6/12/19 " ⁷ O transferred depending on a detected area transition and that the outputs of the stages of the second counter (318) are connected to a logic device (j524) which controls the output signal generation of the detector circuit (138). 10. Device according to one or more of the claims 3 to 9, characterized in that the output of the memory register (1? 4) is connected to a parity check unit (146) , which includes counters (440, 442, 444, 446) so are constructed so that a modulo 3 count is made for all binary "1" and for all binary "O" of a stored word is, and that a comparison device (448) the compares corresponding count values of the said counters with one another. 11. Device according to one or more of the claims 7 to 10, characterized in that the output signals of said linking elements are fed to a buffer register (128) which stores data in a sequence which is controlled by the clock signals generated by the clock pulse source (127). 12. Device according to one or more of the preceding Claims, characterized in that the recognizable areas on the recording medium consist of areas of different color. 13. The device according to claim 12, characterized in that that the scanning and decoding device includes a manually operable scanning pen (62) which is positioned over the recording medium can be guided and has a device (78) through which a light beam onto the recording medium 009884/1923 June 12, 1970 ■ is directed, and which has a further device (8O), through which the light reflected from the recording medium is received and a light-sensitive device (76) is supplied. June 12, 1970 009884/1923