DE2007322A1 - Transport and testing device for semiconductor wafers - Google Patents

Transport and testing device for semiconductor wafers

Info

Publication number
DE2007322A1
DE2007322A1 DE19702007322 DE2007322A DE2007322A1 DE 2007322 A1 DE2007322 A1 DE 2007322A1 DE 19702007322 DE19702007322 DE 19702007322 DE 2007322 A DE2007322 A DE 2007322A DE 2007322 A1 DE2007322 A1 DE 2007322A1
Authority
DE
Germany
Prior art keywords
box
transport
testing device
semiconductor
semiconductor wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702007322
Other languages
German (de)
Inventor
George Streetly. Staffordshire Coffin (Großbritannien)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Joseph Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Joseph Lucas Industries Ltd filed Critical Joseph Lucas Industries Ltd
Publication of DE2007322A1 publication Critical patent/DE2007322A1/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333Trays for chips
    • H01L21/67336Trays for chips characterized by a material, a roughness, a coating or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68313Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

Traneportier- und Prüfeinrichtung für Halbleiter-PlättohenTransport and testing device for semiconductor plates

Die Erfindung betrifft eine Transportier- und Prüfeinrichtung für HaIbleiter-Plättohen. Dtr Begriff "Halbleiter-Plättohen" kennzeichnet kier la wesentlichen jedes Plättchen aus einem Halbleiterwerkstoff, bei dem es sich um einen getrennten Teil oder einer Anzahl von Teilen oder um eine komplexe Sohaltung handeln kann, gleichgültig ob die Fertigungsrerfahren beendet worden sind oder nicht, denen das Plättchen unteraogen wird.The invention relates to a transporting and testing device for semiconductor plates. The term "semiconductor plates" identifies la essentially every plate made of a semiconductor material in which it is a separate part, or a number of parts, or a complex attitude can act, regardless of whether the manufacturing process finished or not to which the platelet was subjected will.

liu linriohtung gemäfi der Erfindung besteht aus einem aus Kunststoff geformten Kasten mit offener Oberseite und mit dem Kasten in einer YIeX-saal Ton Täohera unterteilenden Trennwänden, wobei die !fächer jeweils sä* Aufnahme eines Halbleiter-Plättchens Torgesehen sind und der lasten mit einem Beokel Tersehea ist und so beschichtet ist, daß mindestens derLiu linriohtung according to the invention consists of a plastic shaped box with open top and with the box in a YIeX hall Clay Täohera dividing walls, with the! Compartments respectively sä * recording of a semiconductor wafer are seen and the loads with a Beokel Tersehea and is coated so that at least the

009841/1088 - 2 -009841/1088 - 2 -

Boden des jeweiligen Faoh leitend iat, derart, dafl daa Plättohen im jeweiligen ?aoh geprüft werden kann.The soil of the respective Faoh is conductive in such a way that the plates are in the respective? aoh can be checked.

Sie lrfindung ist im nachfolgenden anhand einee Ausführungsbeispiels unter Bezugnahme auf die Zeichnung näher erläutert. In der Zeichnung sind ιThe invention is based on an exemplary embodiment below explained in more detail with reference to the drawing. In the drawing are ι

Tig. 1 eine Draufsicht auf eine Xinriohtung gemäfi der Erfindung und Fig. 2 ein Schnitt an der Linie A-A der Fig. 1.Tig. 1 shows a plan view of a device according to the invention and FIG. 2 is a section on line A-A of FIG. 1.

Die linriohtung besteht aue einem Kasten 11 mit offener Oberseite» der au* A, B, S geformt ist und eine Vielzahl einstückig angeformter Trennwände 12 aufweist» die im reohten Winkel zueinander stehen und den Kasten in eine große Anzahl getrennter Fäoher 13 unterteilen. Bas jeweilige Faoh ist zur Aufnahme eines Halbleiter-Plattchens vorgesehen, bei dem es sioh beispielsweise um eine Diode handeln kann. Der Kasten ist vernickelt, derart, daß die jeweilige Diode in ihrem Faoh 1} auf leitendem Material liegt und unter Verwendung einer normalen Prüfsonde geprüft werden kann. Im Kasten ist ein Deokel 14 zugeordnet, der zweokmaßigerweise im Gleit-SIIFZ auf dem Kasten sitzt, so daß während der Herstellung die Dioden in ihre Fäoher 13 gelegt werden können und dann innerhalb des Kastens entweder gleichzeitig unter Verwendung eines Hehrfaohprüfgeräte oder nacheinander unter Verwendung einer Prüfrorrlohtung geprüft werden können, die automatisch die Teile nacheinander prüft. Babei eind die Abmessungen der Fäoher 13 eo gewählt, daß der Abstand der Teile ein Arbeiten mit einer solchen Prüfvorrichtung geetattet. Als Beschichtungswerkstoff wird ' liokel bevorzugt. Naohdem eine Prüfung erfolgt ist« kann der Deokel 14 auf den Kasten 11 aufgeschoben werden, und danaoh können die Teile transportiert werden. The line direction consists of a box 11 with an open top au * A, B, S is shaped and a large number of integrally molded partitions 12 has »which are at a right angle to each other and the box divide into a large number of separate skippers 13. Bas respective Faoh is intended to hold a semiconductor plate, in which it sioh can for example be a diode. The box is nickel-plated in such a way that the respective diode in its Faoh 1} is on conductive material and can be tested using a normal test probe. A deodorant 14 is assigned in the box, the two-dimensional SIIFZ sits on the box so that during manufacture the diodes can be placed in their Fäoher 13 and then inside the box either simultaneously using a Hehrfaohprüfgerät or can be tested one after the other using a test tube, which automatically checks the parts one after the other. Here and the dimensions der Fäoher 13 eo chosen that the spacing of the parts works with such a test device geetatte. Oil is preferred as the coating material. After an examination has been carried out, the Deokel 14 can be pushed onto the box 11, and then the parts can be transported.

Patentansprücheι Claims ι

009841/1088009841/1088

BAD ORIGINALBATH ORIGINAL

Claims (1)

PatentansprücheClaims Traneportier- und Prüfeinrichtung für Halbleiter-Plättohen, gekennzeichnet durch einen au· Kunststoff geformten Kasten (11) ait offener Oberseite und mit den Kasten (11) in eine Vielzahl von Pächern(i3) unterteilenden Trennwänden (12), wobei die Fächer (13) jeweils zur Aufnahme eines Halbleiter-Plfcttchena vorgesehen sind und der Kasten (11) mit einem Deckel (Η) versehen ist und so beschichtet ist, daß mindestens der Boden des jeweiligen Fachs (υ) leitend ist, derart» daß das lAttchen im jeweiligen Fach geprüft werden kann.Transport and testing device for semiconductor plates, marked through a plastic box (11) with an open top and with the box (11) in a large number of compartments (i3) dividing partitions (12), the compartments (13) each for Accommodation of a semiconductor plfcttchena are provided and the box (11) is provided with a cover (Η) and is coated so that at least the bottom of the respective compartment (υ) is conductive, so » that the lAttchen can be checked in the respective subject. transportier- und Prüfeinrichtung nach Anspruch 1, ' durch gekennzeichnet, daß der Kasten (11) vernickelt ist.transport and testing device according to claim 1, 'characterized by, that the box (11) is nickel-plated. 024
Wa/Se
024
Wa / Se
π ο 9 ^ w r nsπ ο 9 ^ w r ns LeerseiteBlank page
DE19702007322 1969-03-21 1970-02-18 Transport and testing device for semiconductor wafers Pending DE2007322A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1486669A GB1284742A (en) 1969-03-21 1969-03-21 Transporting and testing device for use with semi-conductor wafers

Publications (1)

Publication Number Publication Date
DE2007322A1 true DE2007322A1 (en) 1970-10-08

Family

ID=10048890

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702007322 Pending DE2007322A1 (en) 1969-03-21 1970-02-18 Transport and testing device for semiconductor wafers

Country Status (4)

Country Link
JP (1) JPS4840813B1 (en)
DE (1) DE2007322A1 (en)
FR (1) FR2037235B1 (en)
GB (1) GB1284742A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2130383B (en) * 1982-09-14 1986-06-04 Risho Kogyo Kk Test board for semiconductor packages
FR2562372B1 (en) * 1984-04-03 1986-08-08 Ramy Jean Pierre MICRO COMPONENT TRANSPORT STORAGE RECEPTACLE

Also Published As

Publication number Publication date
GB1284742A (en) 1972-08-09
FR2037235B1 (en) 1975-12-26
FR2037235A1 (en) 1970-12-31
JPS4840813B1 (en) 1973-12-03

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