DE19983476T1 - Einplanung von Operationen unter Verwendung einer Abhängigkeitsmatrix - Google Patents

Einplanung von Operationen unter Verwendung einer Abhängigkeitsmatrix

Info

Publication number
DE19983476T1
DE19983476T1 DE19983476T DE19983476T DE19983476T1 DE 19983476 T1 DE19983476 T1 DE 19983476T1 DE 19983476 T DE19983476 T DE 19983476T DE 19983476 T DE19983476 T DE 19983476T DE 19983476 T1 DE19983476 T1 DE 19983476T1
Authority
DE
Germany
Prior art keywords
scheduling operations
dependency matrix
dependency
matrix
scheduling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983476T
Other languages
English (en)
Other versions
DE19983476B4 (de
Inventor
Amit A Merchant
David J Sager
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19983476T1 publication Critical patent/DE19983476T1/de
Application granted granted Critical
Publication of DE19983476B4 publication Critical patent/DE19983476B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
DE19983476T 1998-08-18 1999-08-18 Verfahren und Schaltungsanordnung zur Einplanung von Operationen unter Verwendung einer Abhängigkeitsmatrix Expired - Fee Related DE19983476B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/135,170 1998-08-18
US09/135,170 US6334182B2 (en) 1998-08-18 1998-08-18 Scheduling operations using a dependency matrix
PCT/US1999/018715 WO2000011545A1 (en) 1998-08-18 1999-08-18 Scheduling operations using a dependency matrix

Publications (2)

Publication Number Publication Date
DE19983476T1 true DE19983476T1 (de) 2001-07-26
DE19983476B4 DE19983476B4 (de) 2006-12-14

Family

ID=22466869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983476T Expired - Fee Related DE19983476B4 (de) 1998-08-18 1999-08-18 Verfahren und Schaltungsanordnung zur Einplanung von Operationen unter Verwendung einer Abhängigkeitsmatrix

Country Status (6)

Country Link
US (1) US6334182B2 (de)
CN (1) CN1158596C (de)
DE (1) DE19983476B4 (de)
GB (1) GB2357869B (de)
HK (1) HK1042566B (de)
WO (1) WO2000011545A1 (de)

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US20060165606A1 (en) 1997-09-29 2006-07-27 Nektar Therapeutics Pulmonary delivery particles comprising water insoluble or crystalline active agents
US7016910B2 (en) * 1999-12-30 2006-03-21 Decode Genetics Ehf. Indexing, rewriting and efficient querying of relations referencing semistructured data
US6356900B1 (en) * 1999-12-30 2002-03-12 Decode Genetics Ehf Online modifications of relations in multidimensional processing
US6434557B1 (en) 1999-12-30 2002-08-13 Decode Genetics Ehf. Online syntheses programming technique
AU6124601A (en) 2000-05-10 2001-11-20 Alliance Pharmaceutical Corporation Phospholipid-based powders for drug delivery
US8404217B2 (en) 2000-05-10 2013-03-26 Novartis Ag Formulation for pulmonary administration of antifungal agents, and associated methods of manufacture and use
US7871598B1 (en) 2000-05-10 2011-01-18 Novartis Ag Stable metal ion-lipid powdered pharmaceutical compositions for drug delivery and methods of use
GB0022189D0 (en) * 2000-09-11 2000-10-25 Univ Loughborough Method and apparatus for analytical problem solving
JP3567878B2 (ja) * 2000-10-02 2004-09-22 日本電気株式会社 パケット交換装置
US6950927B1 (en) * 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
GB2398412B (en) * 2001-10-12 2005-02-09 Pts Corp Processors and Compiling methods for Processors
US7055021B2 (en) * 2002-02-05 2006-05-30 Sun Microsystems, Inc. Out-of-order processor that reduces mis-speculation using a replay scoreboard
JP3577052B2 (ja) * 2002-03-19 2004-10-13 株式会社東芝 命令発行装置及び命令発行方法
US7571302B1 (en) * 2004-02-04 2009-08-04 Lei Chen Dynamic data dependence tracking and its application to branch prediction
US20050216900A1 (en) * 2004-03-29 2005-09-29 Xiaohua Shi Instruction scheduling
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US20070043932A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
US20070136699A1 (en) * 2005-12-08 2007-06-14 International Business Machines Corporation Dependency matrices and methods of using the same for testing or analyzing an integrated circuit
US20080320016A1 (en) * 2007-06-19 2008-12-25 Raza Microelectronics, Inc. Age matrix for queue dispatch order
US20080320274A1 (en) * 2007-06-19 2008-12-25 Raza Microelectronics, Inc. Age matrix for queue dispatch order
JP5142132B2 (ja) * 2007-11-01 2013-02-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 設計プロセスの順序の決定を支援する技術
US7958336B2 (en) * 2008-06-30 2011-06-07 Intel Corporation System and method for reservation station load dependency matrix
US8135942B2 (en) 2008-08-28 2012-03-13 International Business Machines Corpration System and method for double-issue instructions using a dependency matrix and a side issue queue
US8239661B2 (en) * 2008-08-28 2012-08-07 International Business Machines Corporation System and method for double-issue instructions using a dependency matrix
US8099582B2 (en) * 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US20100257341A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Selective Execution Dependency Matrix
US20100257339A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Dependency Matrix with Improved Performance
US8127116B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Dependency matrix with reduced area and power consumption
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
US8977810B2 (en) * 2011-04-08 2015-03-10 Altera Corporation Systems and methods for using memory commands
US10235180B2 (en) * 2012-12-21 2019-03-19 Intel Corporation Scheduler implementing dependency matrix having restricted entries
US20140258697A1 (en) * 2013-03-07 2014-09-11 Mips Technologies, Inc. Apparatus and Method for Transitive Instruction Scheduling
US9400653B2 (en) 2013-03-14 2016-07-26 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies
US9665280B2 (en) * 2014-09-30 2017-05-30 International Business Machines Corporation Cache coherency verification using ordered lists
US10296337B2 (en) 2016-03-21 2019-05-21 International Business Machines Corporation Preventing premature reads from a general purpose register
US11803389B2 (en) * 2020-01-09 2023-10-31 Microsoft Technology Licensing, Llc Reach matrix scheduler circuit for scheduling instructions to be executed in a processor
US11934834B2 (en) * 2021-10-19 2024-03-19 Ampere Computing Llc Instruction scheduling in a processor using operation source parent tracking
US20230195517A1 (en) * 2021-12-22 2023-06-22 Advanced Micro Devices, Inc. Multi-Cycle Scheduler with Speculative Picking of Micro-Operations
US20240004657A1 (en) * 2022-06-30 2024-01-04 Advanced Micro Devices, Inc. Encoded data dependency matrix for power efficiency scheduling

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5655096A (en) * 1990-10-12 1997-08-05 Branigin; Michael H. Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution
US5546597A (en) * 1994-02-28 1996-08-13 Intel Corporation Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
US6216200B1 (en) * 1994-10-14 2001-04-10 Mips Technologies, Inc. Address queue
US5745726A (en) * 1995-03-03 1998-04-28 Fujitsu, Ltd Method and apparatus for selecting the oldest queued instructions without data dependencies
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US5884059A (en) * 1996-01-26 1999-03-16 Advanced Micro Devices, Inc. Unified multi-function operation scheduler for out-of-order execution in a superscalar processor
JP3720371B2 (ja) * 1995-10-06 2005-11-24 アドバンスト・マイクロ・デバイシズ・インコーポレイテッド スーパースケーラープロセッサにおけるｏｕｔ−ｏｆ−ｏｒｄｅｒ実行のための統一化された機能オペレーションスケジューラ
US5778438A (en) 1995-12-06 1998-07-07 Intel Corporation Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5796975A (en) * 1996-05-24 1998-08-18 Hewlett-Packard Company Operand dependency tracking system and method for a processor that executes instructions out of order
US5913925A (en) * 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
US6016540A (en) * 1997-01-08 2000-01-18 Intel Corporation Method and apparatus for scheduling instructions in waves
US5923862A (en) * 1997-01-28 1999-07-13 Samsung Electronics Co., Ltd. Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions
US5850533A (en) * 1997-06-25 1998-12-15 Sun Microsystems, Inc. Method for enforcing true dependencies in an out-of-order processor

Also Published As

Publication number Publication date
GB0103430D0 (en) 2001-03-28
US6334182B2 (en) 2001-12-25
DE19983476B4 (de) 2006-12-14
GB2357869A (en) 2001-07-04
GB2357869B (en) 2003-05-21
CN1158596C (zh) 2004-07-21
WO2000011545A1 (en) 2000-03-02
HK1042566A1 (en) 2002-08-16
CN1331816A (zh) 2002-01-16
HK1042566B (zh) 2005-04-22

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: G06F 922

8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20110301