HK1042566B - 使用相關矩陣的調度操作 - Google Patents

使用相關矩陣的調度操作

Info

Publication number
HK1042566B
HK1042566B HK02103762.8A HK02103762A HK1042566B HK 1042566 B HK1042566 B HK 1042566B HK 02103762 A HK02103762 A HK 02103762A HK 1042566 B HK1042566 B HK 1042566B
Authority
HK
Hong Kong
Prior art keywords
scheduling operations
dependency matrix
dependency
matrix
scheduling
Prior art date
Application number
HK02103762.8A
Other languages
English (en)
Other versions
HK1042566A1 (en
Inventor
A Merchant Amit
J Sager David
Original Assignee
英特爾公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾公司 filed Critical 英特爾公司
Publication of HK1042566A1 publication Critical patent/HK1042566A1/xx
Publication of HK1042566B publication Critical patent/HK1042566B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
HK02103762.8A 1998-08-18 2002-05-17 使用相關矩陣的調度操作 HK1042566B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/135,170 US6334182B2 (en) 1998-08-18 1998-08-18 Scheduling operations using a dependency matrix
PCT/US1999/018715 WO2000011545A1 (en) 1998-08-18 1999-08-18 Scheduling operations using a dependency matrix

Publications (2)

Publication Number Publication Date
HK1042566A1 HK1042566A1 (en) 2002-08-16
HK1042566B true HK1042566B (zh) 2005-04-22

Family

ID=22466869

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02103762.8A HK1042566B (zh) 1998-08-18 2002-05-17 使用相關矩陣的調度操作

Country Status (6)

Country Link
US (1) US6334182B2 (zh)
CN (1) CN1158596C (zh)
DE (1) DE19983476B4 (zh)
GB (1) GB2357869B (zh)
HK (1) HK1042566B (zh)
WO (1) WO2000011545A1 (zh)

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US8404217B2 (en) 2000-05-10 2013-03-26 Novartis Ag Formulation for pulmonary administration of antifungal agents, and associated methods of manufacture and use
US7871598B1 (en) 2000-05-10 2011-01-18 Novartis Ag Stable metal ion-lipid powdered pharmaceutical compositions for drug delivery and methods of use
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US6950927B1 (en) * 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
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US7055021B2 (en) * 2002-02-05 2006-05-30 Sun Microsystems, Inc. Out-of-order processor that reduces mis-speculation using a replay scoreboard
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US7571302B1 (en) * 2004-02-04 2009-08-04 Lei Chen Dynamic data dependence tracking and its application to branch prediction
US20050216900A1 (en) * 2004-03-29 2005-09-29 Xiaohua Shi Instruction scheduling
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US20070043932A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
US20070136699A1 (en) * 2005-12-08 2007-06-14 International Business Machines Corporation Dependency matrices and methods of using the same for testing or analyzing an integrated circuit
US20080320016A1 (en) * 2007-06-19 2008-12-25 Raza Microelectronics, Inc. Age matrix for queue dispatch order
US20080320274A1 (en) * 2007-06-19 2008-12-25 Raza Microelectronics, Inc. Age matrix for queue dispatch order
JP5142132B2 (ja) * 2007-11-01 2013-02-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 設計プロセスの順序の決定を支援する技術
US7958336B2 (en) * 2008-06-30 2011-06-07 Intel Corporation System and method for reservation station load dependency matrix
US8135942B2 (en) 2008-08-28 2012-03-13 International Business Machines Corpration System and method for double-issue instructions using a dependency matrix and a side issue queue
US8239661B2 (en) * 2008-08-28 2012-08-07 International Business Machines Corporation System and method for double-issue instructions using a dependency matrix
US8099582B2 (en) * 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US20100257341A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Selective Execution Dependency Matrix
US20100257339A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Dependency Matrix with Improved Performance
US8127116B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Dependency matrix with reduced area and power consumption
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
US8977810B2 (en) * 2011-04-08 2015-03-10 Altera Corporation Systems and methods for using memory commands
US10235180B2 (en) * 2012-12-21 2019-03-19 Intel Corporation Scheduler implementing dependency matrix having restricted entries
US20140258697A1 (en) * 2013-03-07 2014-09-11 Mips Technologies, Inc. Apparatus and Method for Transitive Instruction Scheduling
US9400653B2 (en) 2013-03-14 2016-07-26 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies
US9665280B2 (en) * 2014-09-30 2017-05-30 International Business Machines Corporation Cache coherency verification using ordered lists
US10296337B2 (en) 2016-03-21 2019-05-21 International Business Machines Corporation Preventing premature reads from a general purpose register
US11803389B2 (en) * 2020-01-09 2023-10-31 Microsoft Technology Licensing, Llc Reach matrix scheduler circuit for scheduling instructions to be executed in a processor
US11934834B2 (en) * 2021-10-19 2024-03-19 Ampere Computing Llc Instruction scheduling in a processor using operation source parent tracking
US20230195517A1 (en) * 2021-12-22 2023-06-22 Advanced Micro Devices, Inc. Multi-Cycle Scheduler with Speculative Picking of Micro-Operations
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US5850533A (en) * 1997-06-25 1998-12-15 Sun Microsystems, Inc. Method for enforcing true dependencies in an out-of-order processor

Also Published As

Publication number Publication date
GB0103430D0 (en) 2001-03-28
US6334182B2 (en) 2001-12-25
DE19983476B4 (de) 2006-12-14
GB2357869A (en) 2001-07-04
GB2357869B (en) 2003-05-21
CN1158596C (zh) 2004-07-21
WO2000011545A1 (en) 2000-03-02
HK1042566A1 (en) 2002-08-16
DE19983476T1 (de) 2001-07-26
CN1331816A (zh) 2002-01-16

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20110818