DE19849586C1 - Three-dimensional IC production comprises opening of filled trenches before cutting a three-dimensional circuit structure into individual circuits - Google Patents

Abstract

Three-dimensional circuit production comprises opening of filled trenches (16) before cutting a three-dimensional circuit structure into individual circuits. A three-dimensional circuit production process comprises mounting chips (14) separated by trenches (16) on a substrate (10) having a metallization structure (24a, 24b, 24c), filling the trenches to obtain a planar substrate stack, connecting the metallization structure with the chip metallization structure (36a, 36b, 36c) and cutting the resulting three-dimensional circuit structure into individual three-dimensional circuits. The trenches are opened before the cutting operation.

Description

The present invention relates to manufacture integrated circuits and especially on the manufac development of three-dimensional integrated circuits under Ver tested, selected and separated chips.

The expression "three-dimensional integration" or "three-dimensional sional circuits "should include integrated circuits, where components are made by a planar Standard semiconductor technology have been manufactured are vertically connected. The advantages of a three-dimensional integrated microelectronic system are in particular in that with essentially identical design rules higher packing densities and switching rates compared to two-dimensional systems can be obtained. The The main advantages are shorter Conductor tracks or connections between individuals Components or circuits and by the possibility parallel data processing. The increased efficiency of the Systems is further optimized by a connection technology is used, the vertical connections makes it possible to freely choose their positioning are bar, and which are suitable for high integration.

U.S. Patent No. 5,563,084 describes a method of Manufacture of a three-dimensional integrated circuit, in which a completely processed first substrate ver a connection layer with individual circuit chips is bound. The individual circuit chips that are on the first Be applied by separating a substrate won second substrate. The same are so on the Connection layer applied and thus with the first sub  strat glued that trenches between the circuit chips are available. After placing the circuit chips on the first substrate, the trenches are filled to planar To be able to use disc technologies for the surface structure the resulting substrate stack can to necessary metallization connections shape. The individual integrated circuits are by separating the finished processed stack of substrates won along the filled trenches.

Although the known method is advantageous in that it delivers a very high yield since the individual scarf tung chips before applying to the first substrate on ih Pro functionality are tested, but Pro arise blemish when separating the individual three-dimensionally to get integrated circuits. Scattered three dimes Regional integrated circuits showed off, for example breaks at the saw edges, which led to loss of yield.  

DE 917 35 041 A1 discloses a method for separating Micro components of integrated circuits. The micro construction elements are on a substrate in a predetermined Structure formed. To protect the micro components from back a separation process is on the entire surface of the substrate a protective layer is applied, which when sawing the substrate, to achieve a separation of the micro-components, immediately is removed in front of the saw blade to prevent the blade from sticking Avoid saw blades.

The object of the present invention is a Methods of making three-dimensional circuits create that enables a high yield.

This object is achieved by a method according to claim 1 solves.

The present invention provides a method for producing three-dimensional circuits with the following steps:
Providing a first substrate with at least one metallization structure;
Placing a plurality of circuit chips side by side on the first substrate and connecting to the first substrate to obtain a substrate stack, wherein individual circuit chips of the plurality of circuit chips are spaced apart by a trench;
Filling the trench with a fill material to obtain a substantially planar surface of the substrate stack;
Connecting the metallization structure of the first substrate to a metallization structure of a circuit chip in order to obtain a three-dimensional mother circuit arrangement; and
Dividing the three-dimensional mother circuit arrangement to obtain three-dimensional circuits;
the trench being opened before the step of dividing.

The present invention is based on the finding that that the yield losses in the known method by the separation of the processed three-dimensional integrated circuits have occurred on the Planari coating layer that was applied, around the trenches between the individual on their functionalities Ability to fill tested chips. The planarization layer is required to standard planar structure approximately, such. B. metallization connections with Metallization levels of the chip or the first substrate to be able to perform.

To eliminate the problems from the prior art, the have resulted in loss of yield when separating according to the present invention the trenches in front of the club opened again. When separating the three-dimensional integrated chips from the substrate stack are thus on due to the elimination of the planarizing layer for filling The trenches have no layers other than the first To cut substrate, which is advantageous by sawing can be executed.  

Furthermore, the regions of the first substrate can now be between the chips that defined the trenches before they were separated, advantageously used for bond or measurement pads to those who, after the three-dimensional inte circuits at most a very thin passive layer on them that are easy to open can. In the prior art, the opening of the layer was Filling the trenches is very difficult since their thickness is about the same the amount of the circuit chips applied corresponded to the is several micrometers. This costs accordingly according to the present Er finding.

According to a preferred embodiment, it comprises Process according to the invention for producing three-dimensional Circuits first the step of making a he Most substrate, such that the same at least one elec tronic component and a metallization structure points. Furthermore, a second substrate is processed, such that the same a plurality of electronic components and has at least one metallization structure where be defined by individual circuit chips. The second Substrate is diced to get circuit chips wherein a circuit chip has at least one electronic construction Element and has a metallization structure. Preferential the individual chips are either singled out Chips or as circuit chips in the second substrate are formed, side by side before applying the same on a surface of the first substrate to form a Obtain substrate stacks on their functionality checked. By applying the tested circuit chips trenches arise between the individual circuit chips that vertically from the surface of the first substrate to the Extend surface of the circuit chips that the Surface of the first substrate is opposite.

Depending on the technology used, continuity holes are made in the chips for metallization  structures within the chips or metallization structure ren of the chips and the first substrate with each other tie.

The trenches are cut during the manufacture of the three-dimensional nalen integrated circuit with a filling material fills to a substantially planar surface of the sub to obtain stratstapels if such a planar upper area is necessary, for example, to make contact connections integrated circuits through techniques that planar upper need areas to manufacture (e.g. standard lithography method). The trenches can alternatively be filled before Connecting the metallization structures by means of a passage holes. Before cutting one like that obtained three-dimensional mother circuit arrangement ent long trenches to the individual three-dimensional scarf to maintain the trenches between the brought circuit chips of the three-dimensional mother scarf opened so that only the first one when cutting Substrate must be cut, which results in losses in yield Splitting can be essentially avoided.

Preferred embodiments of the present invention are referred to below with reference to the attached drawing explained in detail. Show it:

Figure 1 is a sectional view of the three-dimensional mother circuit arrangement before filling the trenches.

Fig. 2 is a sectional view of the three-dimensional mother circuit arrangement after filling the trenches; and

Fig. 3 is a sectional view of the three-dimensional mother circuit arrangement before dividing in order to obtain the individual three-dimensional circuits.

Fig. 1 shows a sectional view of the three-dimensional Mut circuit arrangement before filling the trenches. The mother circuit arrangement comprises a first substrate 10 , on which a layer 12 comprising a plurality of circuit chips ( 14 ) is applied. The individual circuit chips 14 of the layer 12 are processed independently of the processing of the first substrate 10 from a wafer, which is also referred to as a second substrate or top substrate. Analogously, the first substrate 10 is also referred to as a bottom substrate. The individual circuit chips 14 are separated from one another by trenches 16 . Although only a trench 16 is shown in Fig. 1, it should be noted that a mother circuit arrangement, as shown in Fig. 1 in cross section during a certain manufacturing stage, is flat and can have a plurality of circuit chips 14 , so that if the circuit chips have a rectangular shape, the trench or trenches 16 extend along the edges of the individual circuit chips.

In a preferred exemplary embodiment of the invention, the first substrate 10 comprises a semiconductor wafer 18 , which may have completely processed MOS circuits 20 , which are shown schematically in FIG. 1 as the three contacts of a transistor. On the surface of the semiconductor wafer 18 is also a dielectric layer 22 , for. B. an intermetallic dielectric, on or in which different tallization levels 24 a, 24 b and 24 c are applied or embedded, which together form a metallization structure of the first substrate 10 . Since FIG. 1 is a Querschnittsdar position, the compounds of the metallization are planar to the individual terminals of the MOS circuit 20 and the semiconductor wafer 18, ie, to bulk, does not Darge.

The fully processed first substrate 10 comprises the semiconductor wafer 18 , the MOS circuits 20 , the intermetallic electrical 22 and the metallization levels 24 a to 24 c. Finally, a passivation layer 26 can be applied to the first substrate 10 , as is customary in semiconductor technology, which passivation layer can already perform a planarizing function for the subsequent production of the three-dimensional circuits. On the passivation layer 26 , a connection layer 28 is applied, through which the individual circuit chips 14 are connected to the first substrate 10 in an adjusted manner. The tie layer 28 is preferably made of polyimide.

The individual circuit chips 14 of the layer 12 have a structure similar to that of the first substrate 10 . They each comprise a wafer section 30 , in which one or more MOS circuits 32 are preferably integrated. A dielectric layer 34 , e.g. B. an intermetallic dielectric, arranged on or in the tallization levels 36 a, 36 b, 36 c applied or embedded. The surface of the individual circuit chips 14 is also preferably covered with a passivation layer 38 . The metallization levels 36 a, 36 b and 36 c together form a metallization structure of the circuit chips 14 . The circuit chips 14 further include through holes or via holes 40 , which are formed as interchip vias at the locations within a circuit chip at which an electrical contact to the underlying circuit structures of the first substrate 10 is to take place later.

The arrangement shown in FIG. 1 is referred to as the mother circuit arrangement, since the three-dimensional circuits are obtained by dividing the same after several further processing steps which are carried out later. The point at which the mother circuit arrangement, which is shown in FIG. 1 during its production, will be divided later, is indicated schematically by a dividing line 42 .

The mother circuit arrangement shown in Fig. 1 is manufactured as follows. First, as he already mentioned, the first substrate 10 and a second substrate, from which the circuit chips 14 of the layer 12 are obtained, are processed independently of one another. The second substrate, from which the individual circuit chips 14 are finally obtained, is then subjected to a functional test in order to be able to distinguish functional circuit chips 14 from non-functional circuit chips. In order to substantially increase system efficiency, according to the prior lying invention, the first substrate and the second substrate are not simply connected but the second sub is strat cut to obtain the individual circuit chips 14, but only the functional circuit chips 14 can be used in other to form the layer 12 of circuit chips 14 .

In order to maintain the mother circuit arrangement shown in FIG. 1, the individual circuit chips 14 are finally placed next to one another on the first substrate 10 , as a result of which the trenches 16 are formed. The circuit chips of the layer 12 are only mechanically connected to the first substrate 10 in FIG. 1. No electrical connection has yet been made to obtain a three-dimensional circuit.

In order to produce a vertical connection of a metallization level 36 a, 36 b, 36 c of a circuit chip 14 of the layer 12 with a metallization level 24 a, 24 b or 24 c of the first substrate 10 , the following steps are carried out according to a preferred embodiment of the present invention . First, the connection layer 28 , that is, the adhesive layer, and the passivation layer 26 of the first substrate 10, for example by anisotropic dry etching, whereby the through holes 40 up to a metallization level of the first substrate 10 , in FIG. 3 to the metalization level 24 a , which is applied to the intermetallic dielectric 22 , are opened. In a preferred exemplary embodiment of the present invention, the adhesive layer 28 and the passivation layer 26 in the trenches 16 are also removed by this step of dry etching. Before preferably, a dielectric layer can now be deposited on the surface of the substrate stack for the electrical insulation of the through holes, so that after an anisotropic etching back step after the so-called spacer process, only the side walls of the through holes 40 and the side walls of the circuit chips in the trenches of one pass dielectric layer 44 (see FIG. 2) are covered.

Subsequently, by means of the so-called plug technique according to a preferred embodiment of the present invention, metal of suitable thickness can be deposited on the surface, which is then anisotropically etched back, so that 40 metal plugs or "plugs" 46 remain in the through holes. When using this plug technique, the side walls of the circuit chips 14 , that is to say the side walls of the trench ( 16 ), are also covered with metal, as is indicated by the reference symbol 48 . However, as can be seen from FIG. 2, the bottom surfaces of the trenches 16 are free of metal due to the greater width after the plug technique has been used.

As can be seen from FIG. 2, the metal contact extends from the uppermost metallization level 24 a of the first substrate 10 to the dielectric layer 38 which is applied to the circuit chips 14 . If a metallization layer 24 b, 24 c arranged in the inter-metal dielectric 22 of the first substrate 10 is to be contacted, the through holes 40 must be provided at a corresponding location in the circuit chips 14 , and the through holes must be made deeper than in the example shown, so that The metal plug that is produced later comes into contact with the corresponding metallization level.

A planar surface must be created so that the substrate stack shown in FIG. 2, ie the mother circuit arrangement being manufactured, can be processed further by means of standard photolithographic processes. For this purpose, the trenches 16 are filled with a filling material 50 . In a preferred exemplary embodiment, the filling material can be applied by spinning on a lacquer layer of suitable thickness and then etching back with an anisotropic dry etching step until the surface of the circuit chips 14 is exposed, but the trenches between the circuit chips are filled with the filling material 50 , that is to say have lacquer inserts. Then, in accordance with a standard semiconductor technology step, a photoresist layer 52 is applied to the now planarized surface, which is structured by means of a conventional lithography process, in order to produce holes 54 in the photoresist layer 52 at a suitable location, for example in order to raise the metallization level 36 a via contact holes that can be etched into the passivation layer 38 . If the metallization level 36 b is to be contacted, the contact hole, which is then necessary, must be made deeper, ie the same must extend through the passivation layer 38 and the intermetallic dielectric 34 up to, for example, the metallization level 36 b or 36 c. Of course, contact holes for the through holes 40 can also be produced in this step in order to have a connection for a metallization level of the first substrate 10 directly from the outside.

Fig. 2 shows only the arrangement with the patterned photoresist layer 52, a connection of a metallization plane of the first substrate 10 having a metallization level of the circuit chip 14 is not yet carried out. A Kon of the metallization to allow clocking of, in the embodiment shown in FIG. 2 arrangement, the passivation layer 38, for example. B. etching, in the area of the contact hole 54 opens ge. Then the photoresist 52 z. B. removed by so-called ashing in an oxygen plasma reactor and by a subsequent cleaning. An upper metallization 56 (see FIG. 3) is then carried out by a standard metallization, e.g. B. by deposition and structuring of an aluminum alloy, so that the metallization level 24 a of the first substrate 10 is metallically connected to the metallization level 36 a of the corresponding circuit chip 14 . Since the trench or trenches 16 are filled with the filling material, it is advantageously achieved that the metal is removed from the regions of the trench 16 by the structuring of the standard metalization. After completion of the upper metallization, the filler 50 is removed from the trench 16 , e.g. B. by so-called ashing in an oxygen plasma reactor gate and by subsequent cleaning. The removal of the filler material 50 from the trenches 16 can of course also be implemented using other methods.

As a final step, the substrate stack with the three-dimensionally integrated circuits according to standard methods is provided with a dielectric surface passivation 57 in order to obtain a completely processed three-dimensional mother circuit arrangement. The three-dimensional mother circuit arrangement is now divided along the dividing line 42, for example by sawing or similar known methods, in order to obtain the individual three-dimensional integrated circuits.

From Fig. 3 it can clearly be seen that only the lower substrate 10 , ie the semiconductor wafer 18 , and the interme talldielectric 22 and the surface passivation layer 57 must be divided, since the trenches 16 are open. In the prior art, on the other hand, the trenches were filled, which had resulted in the described disadvantage of lower yield when the three-dimensional mother circuit arrangement was broken up in order to obtain the individual three-dimensional circuits.

After dividing the three-dimensional mother circuit arrangement, which is shown in Fig. 3, the individual three-dimensional integrated circuits 1 are available. It is obvious to those skilled in the art that a flat wafer must be diced in both the x and y directions in order to obtain a plurality of three-dimensional integrated circuits 1 by dicing, only the first substrate 10 and not the whole Mother circuit arrangement must be cut because the trenches 16 have been opened before the Zertei len.

Although in the described embodiment, the through holes 40 have already been produced during the processing of the second wafer to obtain the individual circuit chips 14 , it is obvious to experts that these through holes also after the application of the circuit chip 14 and after filling the trenches Füllma material could be produced by appropriate processes that are suitable for planar surfaces.

So that three-dimensional circuits with standard semiconductor technologies, which are proven on the one hand and on the other hand cheaper than special technologies, can be produced, the method according to the invention provides a temporary planarization of the trenches during manufacture and, on the other hand, open trenches in front of the ceramics, such that Standard methods for planar, ie two-dimensional, circuits can be used and, in addition, the division can also be carried out with a high yield. Although the present invention has been described in connection with CMOS circuit structures 32 and 20 , it should be understood that the method of filling the trenches and opening the trenches prior to dicing is applicable to any technology and is not limited to CMOS technology is.

A major advantage of the present invention is that the described method can be repeated any number of times in order to obtain any number of components of a highly integrated three-dimensional circuit. The substrate stack shown in FIG. 3 can act in an analogous manner again as the first substrate to which a new layer 12 of circuit chips 14 can be applied. Thus, a modular manufacturing process has been described that enables three-dimensional systems with direct electrical connections via so-called interchip Vialö cher between two superimposed vertically adjacent circuit chips. Another advantage of the method according to the invention is the fact that the contacts between circuit structures of the joined layers 12 can be freely selected from component layers and can be produced by means of inexpensive lithography steps for planar surfaces, which results in a favorable freedom of design.

Another advantage of the present invention is that the areas between the circuit chips 14 can be used before for geous for bond or measurement pads that can be easily opened after the manufacture of the three-dimensional inte grated circuits. Since the thickness of the planarizing layer present according to the prior art is several micrometers - the thickness corresponds approximately to the height of the applied and preferably thinned circuit chips 14 - the opening of the layer by means of etching is very complex and therefore expensive. This accordingly costly manufacturing step is eliminated in the manufacturing method according to the invention.

Claims (16)

1. A method for producing three-dimensional circuits ( 1 ) with the following steps:
Providing a first substrate ( 10 ) with at least one metallization structure ( 24 a, 24 b, 24 c);
Arranging a plurality of circuit chips ( 14 ) on the first substrate ( 10 ) and connecting to the first substrate ( 10 ) to obtain a substrate stack, wherein individual circuit chips ( 14 ) of the plurality of circuit chips ( 14 ) by a trench ( 16 ) are spaced;
Filling the trench with a fill material ( 50 ) to obtain a substantially planar surface of the substrate stack;
Connecting the metallization structure ( 24 a, 24 b, 24 c) of the first substrate ( 10 ) with a metallization structure ( 36 a, 36 b, 36 c) of a circuit chip ( 14 ) in order to obtain a three-dimensional mother circuit arrangement; and
Dividing the three-dimensional mother circuit arrangement to obtain three-dimensional circuits ( 1 );
characterized by
that before the step of dividing the trench ( 16 ) ge is opened. 2. The method of claim 1, wherein opening the trench ( 16 ) comprises selectively etching the fill material ( 50 ) to remove the fill material ( 50 ) to the bottom of the trench ( 16 ). 3. The method of claim 1, wherein opening the trench comprises incinerating the filler ( 50 ) in an oxygen plasma reactor and then cleaning it. 4. The method according to any one of the preceding claims, wherein the step of dividing comprises sawing the first substrate ( 10 ) along the open trench ( 16 ). 5. The method according to any one of the preceding claims, wherein the step of filling the trench ( 16 ) comprises the following steps:
Applying the filler material ( 50 ) to the surface of the substrate stack which has the trench ( 16 ); and
Etching back the filler material such that only filler material ( 50 ) remains in the trench ( 16 ), where a substantially planar surface of the substrate stack is obtained. 6. The method according to any one of the preceding claims, wherein the first substrate ( 10 ) is produced by the following steps:
Processing a semiconductor wafer ( 18 ) to obtain an electronic component ( 20 ); and
Forming the metallization structure ( 24 a, 24 b, 24 c), which has at least two inner metallization levels ( 24 b, 24 c), which are insulated from one another by an intermetallic dielectric ( 22 ), the metallization structure having at least one outer metallization level ( 24 a) has on the surface of the inter metal dielectric ( 22 ). 7. The method of claim 6, wherein the step of arranging the circuit chips ( 14 ) further comprises the following steps:
Applying an adhesive layer ( 28 ) on the surface of the first substrate ( 10 ) having the outer metallization level ( 24 a); and
adjusted placement of the circuit chips ( 14 ) on the adhesive layer ( 28 ). The method of claim 7, wherein the step of opening the trench further comprises the step of removing the adhesive layer ( 28 ) in the trench ( 16 ) where the trench ( 16 ) extends to the surface of the first substrate ( 10 ) . 9. The method according to any one of the preceding claims, further comprising the steps of:
Processing a second substrate to form a plurality of electronic components ( 32 ) and the metallization structure ( 36 a, 36 b, 36 c) in the same, whereby the circuit chips ( 14 ) are defined;
Separating the second substrate in order to obtain the plurality of circuit chips ( 14 ), a circuit chip having at least one electronic component ( 32 ) and a metallization structure ( 36 a, 36 b, 36 c);
wherein the step of processing the second substrate comprises the following steps:
Processing a semiconductor wafer ( 30 ) to obtain the electronic component ( 32 );
Forming the metallization structure ( 36 a, 36 b, 36 c);
Forming through holes ( 40 ) through the second substrate, so that a certain metallization level ( 36 a, 36 b, 36 c) of the second substrate with a certain metallization level ( 24 a, 24 b, 24 c) of the first substrate ( 10 ) is connectable; and
Passivating ( 38 ) the second substrate. 10. The method of claim 9, wherein the step of connecting comprises the following steps:
Removing a passivation layer ( 26 ) of the first substrate ( 10 ) in the through holes ( 40 );
Continuation of the through holes up to a specific metallization level ( 24 a, 24 b, 24 c) of the first substrate ( 10 );
Depositing metal on the surface of the wafer stack; and
Etching back of the deposited metal, such that metal plugs ( 46 ) remain in the through holes ( 40 ), whereby at least one metallization level ( 24 a) of the first substrate ( 10 ) is connected to a metallization level ( 36 a) of the second substrate ( 57 ). 11. The method according to any one of claims 1 to 9, wherein the step of connecting comprises the following step:
photolithographically patterning the surface of the substrate stack using photoresist ( 52 ) to define contact holes ( 54 ) for metallization connections of the three-dimensional circuits ( 1 ). 12. The method according to claim 11, wherein the filling material ( 50 ) by a in the trenches ( 16 ) remaining photoresist ( 52 ), which was applied in the step of photolithographic structuring, is formed. 13. The method according to any one of the preceding claims, in which the following steps are carried out before connecting circuit chips ( 14 ):
Checking the electronic components of the second sub strate for operability in order to distinguish functional circuit chips from non-functional circuit chips; and
Selecting the functional circuit chips; and
wherein in the step of arranging only selected functional circuit chips ( 14 ) are connected to the first substrate ( 10 ). 14. The method according to any one of the preceding claims, wherein the first substrate ( 10 ) has an electronic component ( 20 ). 15. The method according to claim 14, wherein the electronic components ( 20 , 32 ) in the first substrate ( 10 ) and in the circuit chips ( 14 ) are MOS components. 16. The method according to any one of the preceding claims, wherein the first substrate ( 10 ) is a wafer stack arrangement.