DE19844140C1 - Coder/decoder for block interleaving and de-interleaving - Google Patents

Abstract

The coder/decoder uses a memory (1) and an address line modifying unit (2). Depending on a read or write signal for the memory, the address lines adjacent to the memory are modified so that a read or write of data into or from the memory results in a block interleaving or de-interleaving. The address line modifying unit has a multiplexer (3) with its first input, second input (5) and output (6) to connect the first or second input with the output according to the read or write signal. A large number of the input address lines are connected with the second input directly and connected with the first input so that a rotational displacement to the lower value input address lines occurs.

Description

The invention relates to a coding or decoding direction for performing block interleaving or Block deinterleaving.

In particular, the present invention relates to a Coding or decoding device as for the digital Mo bilfunkfunk is used, whereby to reduce Bit error rates by minimizing burst errors Block interleaving or deinterleaving is used.

In digital cellular transmission between a base There are usually several stations and one mobile station possible ways of spread. Reflection and scattering of waves lead to buildings, mountains, trees and other obstacles to the fact that the reception field strength consists of several, in general my different strengths and different delays components. The individual waves can overlap either constructively or destructively, whereby Pe changes strongly in a spatial reception area gel courses result. A mobile receiver passes through such reception area, this leads to location-dependent greatly changing reception levels, what as fading or as Fast fading is called.

These fading drops generate in a mobile receiver So-called burst errors or burst errors, which results in a noticeable disturbance.

To reduce such burst errors is in many digita len cellular standards interleaving provided. Under Inter leaving means the rearrangement and spreading of time of symbols in a clear, deterministic way. Thereby  can ver bundle errors in such a way in a transmission channel be shared that this becomes almost "memoryless" where in combination with error detection devices errors can be reduced to a suitable level.

There are a multitude of options for interleaving, where the diagonal interleaving that block interleaving and folding interleaving are best known.

With block interleaving, a data stream is written line by line into an x × y matrix and then read out again in columns.
Registration of the data:

1 5 3 4 7 9 6 8 2

in an x × y matrix gives the block:

1 5 3
4 7 9
6 8 2.

Reading out this block in columns now results in an encoded data stream:

1 4 6 5 7 8 3 9 2.

If a burst error occurs, for example the Da ten 4, 7 and 9 damaged and therefore a noticeable block mistake error is caused after block interleaving spread or distributed in the data stream, which in ge proper error correction an improved transmission quality action.

Block interleaving or reordering of the data usually happens with a corresponding software routine  ne that performs a special address calculation, or with a special hardware that consists of several in a row driven shift registers exists.

The disadvantage here is the large amount of time and / or Circuit effort for such a block interleaver.

From US 5,659,580 a data memory, a counter, a Multiplexer and means for swapping memory addresses known, encoded data among those generated by the counter consecutive contiguous memory addresses ge is saved. After the encoded data is completely ge are stored, the multiplexer connects the means for ver exchange of addresses, the incoherent or not successive addresses generated with the data store, so that the encoded data is in a contiguous row sequence can be read out.

From WO 89/01265 A1 an arrangement is known in which Data are temporarily stored in a memory and that The data is then read out, in an inconsistent manner hang order, using a variety of counters are used to generate addresses.

The invention is therefore based on the object of / Decoding device for performing a block interlea ving / deinterleavings to create the most cost effective is to produce and a quick re-sorting of the data possible.

This object is achieved with the in claim 1 specified features solved.

Further developments are specified in the subclaims.

In particular through the use of an address line modifi cation device which, depending on a writing / Read signal a variety of input address lines modifi graces, can be by using a registered data  the unmodified address lines and reading the Data using the modified address lines very fast block interleaving cost-effectively implemented become.

The address line modification device consists of a switching device with two inputs and one output, the one with an address input of a conventional RAM memory connected is. The switching device is from Read-write signal of the memory is controlled such that it either the first or the second input with the output of the multiplexer and the associated memory det. The variety of address lines are either directly connected to one input or to the other one connected in such a way that there is a rotational displacement from the higher order to the lower order address lines results. This means, for example, that a  valid address directly to the memory, while the Reading the data from the memory by rotating the Address lines unsorted according to block interleaving te data can be read from the memory. Because of the use of conventional hardware components and the very simple structure results in an extraordinary knockout savings and a reduction in electricity needs, which in the manufacture of future mobile devices te is essential.

The invention is illustrated below by means of an embodiment game described in more detail with reference to the drawing.

It shows:

Fig. 1 is a block diagram of a coding / decoding device for performing block interleaving / deinterleaving.

Fig. 1 shows an embodiment of the coding / decoding device for performing a block interleaving / deinter leaving. The reference numeral 1 designates a memory into which data to be coded or a data stream to be coded is written. The memory 1 is connected to an address line modification device 2 via an address bus 7 consisting of a plurality of address lines. The address line modification device 2 also has at its input a plurality of input address lines a ₀ to a ₄ , which are modified as a function of a read / write signal r / w and serve as respective address lines for the memory 1 . The reference numeral 8 denotes a read / write line, via which the read / write signal r / w of the address line modification device 2 and the memory 1 is supplied.

A block interleaving is achieved according to the present invention in that when data is written via a data bus 9 into the memory 1, the input address lines a ₀ to a _{4 are} directly, ie not modified, connected to the address bus 7 . By gradually increasing the address and simultaneously writing the data into the memory 1 , data is stored in a predetermined order in the memory 1 . In the subsequent reading process, however, the input address lines a ₀ to a _{4 are} modified and connected to the address bus 7 in such a way that when the same address sequence is applied to the input address lines a ₀ to a _4, data from the memory 1 is spread over time via the data bus 9 can be read out, which corresponds to block interleaving.

Fig. 1 shows a particularly advantageous construction of such a modification address line device 2. It essentially consists of a changeover switch or multiplexer 3 , which has a first input 4 , a second input 5 and an output 6 . The multiplexer 3 has a write / read line 8 as the control line, with which the memory 1 is also controlled. Depending on the read / write signal r / w, the output 6 of the multiplexer 3 is either connected to the first input 4 or to the second input 5 . Address lines are switched on to the inputs 4 , 5 and the output 6 of the multiplexer 3 . The Adreßlei lines of the output 6 are connected directly to the address input of the memory 1 . In contrast, the address lines of the inputs 4 and 5 of the multiplexer 3 are connected in a special way with the input address lines a ₀ to a ₄ .

Referring to FIG. 1, the input address lines A ₀ to A ₄ di rectly connected to the second input 5 of the multiplexer 3, while the same input address lines A ₀ to A ₄ modified to the first input 4 of multiplexer 3 ver connected are that the three low-order input address lines a ₀ , a ₁ and a ₂ are shifted or rotated by three places to the right, whereby the higher-order input address lines a ₃ and a ₄ each replace the previous address lines a ₀ and a _{1 be} moved. The modification of the input address lines according to FIG. 1 thus corresponds to a rotational shift of the input address lines a ₀ to a ₄ from the higher order to the lower order lines or a shift to the right by three places. Such a circuit is especially space-saving and energy-saving for block interleaving, which is of great importance for mobile devices. In addition, the production is inexpensive.

The mode of operation of the coding-decoding device for carrying out block interleaving / deinterleaving according to FIG. 1 is described in detail. First, a data stream is written into the memory 1 via the data bus 9 in a write operation. In this case, the second input 5 is connected to the output 6 via the read / write line 8 in the multiplexer 3 . This means that the input address lines a ₀ to a _{4 are} directly, that is, in an unchanged order with the address input of the memory 1 in connec tion. A large number of data can thus be written in by gradually increasing the addresses present on the input address lines a ₀ to a ₄ . In a subsequent read operation, the first input 4 is connected to the output 6 via the read / write line 8 in the multiplexer 3 . Due to the fact that the address lines applied to the first input 4 have a changed or modified sequence of the input address lines a ₀ to a ₄ , the input address lines a ₀ to a _{4 are} in a different (rotationally shifted) form on the memory during the reading process 1 on. This results in a block interleaving of the read data stream, although the address present on the input address lines a ₀ to a _{4 is} gradually increased by 1.

In the event that the number of rows y and columns x of the block interleaving matrix result in a power of two, a conventional random access memory (RAM) can be used. Block interleaving for an (x, y) matrix with y = 2 ^m rows and x = 2 ⁿ columns can thus be implemented with very little hardware expenditure and minimal run times. In particular, this eliminates the complex and time-consuming address calculation that is carried out in conventional block interleaving.

The decoding or deinterleaving is carried out with the same circuit, but using the modified address lines for writing the data and the unmodified for reading. More specifically, in the decoding device for performing a block deinterleaving in the multiplexer 3, the first input 4 would be connected to the output 6 in a write operation, while the second input 5 would be connected to the output 6 in the read operation.

The embodiment of FIG. 1 is designed for a block interleaving / deinterleaving for a matrix with y = 2 ^m = 8 rows and x = 2 ⁿ = 4 columns. This results in n + m = 5 address lines, an address line path being shifted to the right by m = 3 places. Here, m and n are natural numbers from the set of values {0, 1, 2, 3, ...}.

However, other block interleaving / deinterters can also be used leaving can be realized, as follows based on two Examples is described.

According to a first example, the following data stream is to be pushed into an interleaver, the addresses matching the data for the sake of simplicity:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15.

The block interleaving matrix consists of x = 4 columns and y = 4 rows:

After block interleaving has been carried out, the coded data stream results:

0 4 8 12 1 5 9 13 2 6 10 14 3 7 11 15.

According to this example, the matrix has x = 2 ⁿ = 4 columns and y = 2 ^m = 4 rows. This means that n = m = 2. This results in n + m = 4 address lines:

a ₃ a ₂ a ₁ a ₀ .

Furthermore, according to the present invention, the address lines in an input path of the multiplexer 3 have to be rotated or shifted to the right by m positions. If two positions of the four address lines a ₀ to a _{3 are} shifted in the direction of the lower-order address lines, the following modification results for the address lines at the first input 4 of the multiplexer 3 :

a ₁ a ₀ a ₃ a ₂ .

If you compare the binary representation of the two sequences, then this corresponds exactly to the result of the desired block Interleaving, which means increasing gradually the address on the input address lines generated correct addresses, which in this case with the ent speaking coding data match.  

Due to the simple structure of the required hardware compared to conventional coding / decoding devices a cost saving and a reduced space requirement.

Another example of block interleaving is described below, in which the matrix consists of x = 8 = 2 ³ columns and y = 2 = 2 ¹ rows. As a result, n = 3 and m = 1.

The data stream:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

therefore has the form in the matrix with 8 columns and 2 rows:

After block interleaving, the data stream results:

0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15.

The n + m = 4 address lines must therefore be in one path of the multiplexer by m = 1 digit to the right ro  tiert or towards the lower-order address lines be moved.

The input address lines

a ₃ a ₂ a ₁ a ₀

are therefore modified so that the order at an input of the multiplexer

a ₀ a ₃ a ₂ a ₁

exhibit.

Comparing the binary representation of the two sequences again exactly corresponds to the result of the desired block interleaving:

Accordingly, with the present invention, a block Interleaving can be realized in a particularly simple manner, which in particular reduces the manufacturing costs. Due to the hardware implementation, you also get mini male runtimes, which is particularly true for mobile applications is important. Furthermore, the circuit for implementation the block interleaving / deinterlea described above ving an extremely low energy requirement, what  battery-powered mobile devices a major advantage is.

The present invention has been particularly useful for users described in mobile phones in GSM / UMTS standards. However, it is not limited to this and can be used for all knockouts dier / decoder devices are used in which a fast and inexpensive block interleaving / deinterlea ving is required.

Claims (4)

1. coding / decoding device for performing a block interleaving / deinterleaving with an addressable storage device ( 1 ) for storing data, a plurality of input address lines (a ₀ ... a ₄ ) for addressing the storage device ( 1 ), and an address line modification device ( 2 ) which, depending on a read / write signal (r / w), modifies the plurality of input address lines (a ₀ ... a ₄ ), characterized in that the address line modification device ( 2 ) a switching device ( 3 ) with a first input ( 4 ), a second input ( 5 ) and an output ( 6 ) for connecting the respective first ( 4 ) or second input ( 5 ) with the output ( 6 ) in Dependence on the read / write signal (r / w), the plurality of input address lines (a ₀ ... a ₄ ) being connected directly to the second input ( 5 ) and to the first input ( 4 ) such that a rotational shift from the heights value to the low-order input address lines is present. 2. Device according to claim 1, characterized in that the block interleaving / deinterleaving is carried out for a matrix of y = 2 ^m rows and x = 2 ⁿ columns, the plurality of input address lines (a ₀ ... a ₄ ) have n + m address lines and are shifted by m digits at the first input ( 4 ), where n and m are natural numbers. 3. Device according to one of the claims 1 to 2, characterized in that the memory device ( 1 ) is a read / write memory with random access. 4. Device according to one of the claims 1 to 3, characterized in that the switching device ( 3 ) is a multiplexer.