DE2004934A1 - - Google Patents

Description

IBM Germany Internationale Büro-Maschinen Gesellschaft mbH

Boeblingen, February 2, 1970 ru / du

Applicant s

International Business Machines Corporation, Armonk, N.Y. 105t> 4

Official File number;

New registration

Applicant's file number:

Docket UK 968 020

Memory arrangement with error detection and correction

The invention relates to a memory arrangement with means for Error detection and correction of those stored in the memory Information by dividing the memory into groups of Memory modules that store data or error correction code bits.

Memory arrangements, in particular matrix memories made from ferrite cores or from semiconductor integrated circuits, are used for the modern Data processing systems in an automatic manufacturing process generated. Although very high demands are placed on the devices for producing these memory matrices in particular it is unavoidable that in a matrix memory with several million bits of storage capacity, i.

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several million Linzel components, faulty or damaged Memory locations occur. It is also possible that after a long period of operation of such a memory, different memory cells fail. However, since a memory for a data processing system must be error-free, the individual types of memory various possibilities have become known to uia the damaging

Determine ^ adhere locations within the memory and to tag W

draw or replace it with other non-damaged memory locations. It is also known when saving within a stored word to detect errors and automatically by applying an error correction code to a limited extent to correct.

In addition, in the case of matrix memories with magnetic cores, attempts have been made to replace the defective memory locations by providing more word lines with memory cells from the outset than are actually required for the desired memory capacity. If an error now occurs at a memory location in a word line, then the entire word line is rendered ineffective and one of the redundant lines is activated in its place. However, this type of compensation for defective memory cells within a matrix memory has the great disadvantage that entire cell groups in the memory are redundant, which increases the price of the memory considerably. In addition, with a memory organized in this way it is not possible to have individual defective bit positions on a plurality of word lines

Docket BK 968 020 009834/1702 BAD

determine and correct, as only a certain limited Number of redundant word lines can be built in, at the price of such an organized memory to be kept within acceptable limits.

The American patent 3 222 653 discloses a circuit arrangement has become known, the memory locations within of the storage system is automatically replaced via a control network. If, for example, a defective memory location is activated when the memory is called, then a comparison circuit causes an alternative address, which designates a free, non-defective memory cell, is controlled automatically. However, this additional control network is technically extremely complicated and expensive and it also takes a relatively long time to compensate for errors.

Furthermore, there is a circuit arrangement for compensating for Defective memory cells have been proposed, which is characterized in that each data block is an overflow block in the Memory is assigned, which is known to control the memory blocks and counting from a block address counter, which contains the respective header address and a further block counter that counts the data blocks transferred, as well as through a word address counter that records the word cells within a Block determined by advancing by one and a word counter, who counts the transmitted words, takes place, and that one

Docket'Ιίκ ^f Äö 020 0 0 9 8 3 A / 1 7 0 2 _BAD original

Circuit generates a signal in the presence of a defective word cell within a block, which enables the further switching of the Word counter at this point in time, which results in / uafruf of all word cells in a block the word counter is not on that The setpoint is available and the remaining words of a data block are transmitted via existing, known addressing circuits controls in an assigned overflow block. In addition, there is a further proposal is that each word line of the memory is divided into a plurality of sub-word registers, and that with the main memory is connected to a read-only memory, which is divided into an error code part and a replacement address part is subdivided, via an error correction circuit and a control circuit, a replacement memory, which is in sub-word registers is divided, select one of the sub-word registers and with the defective sub-word register des Connect memory. The circuit effort for the two last-mentioned circuit arrangements, which can only compensate for a defective memory cell in a memory, is in the Relation to the possibility of compensation extremely high. aside from that it was proposed to subdivide a magnetic core memory into m + n partial memories. The number of bits in a memory word is included the sum of m + n, where m is the information bits and η is the error correction bits. Each partial memory has proposed according to this Solution to have its own address register, its own control circuitry and its own data register. The address register aiier '^ eilupeicher are connected in parallel, so that in each part

Docket UK 968 020 00 9 8 3 4/1702 BAD ORIGINAL

memory the same place can be addressed. Thus, it is possible j that ~ can be so many partial memory simultaneously without interruption ', as errors can be corrected by the error correction circuit, but this correction capability is made possible by a very high technical effort, resulting from the allocation of a separate address register, a own control circuit and a separate data register for each partial memory results in »

The invention is based on the object of a memory arrangement to create with error detection and automatic error correction, which by using error correction code bits a variable ■ automatic error correction of the memory words read with made possible with little technical effort.

The inventive solution to the problem is that the memory is divided into a first part for storing words from m data bits and η, error correction code bits and a second part for storing words from m _o data bits and η error correction code bits , where n, greater than m ₂ and n ^ greater than n. "* that a common address register is assigned to the two memory parts and that memory correction circuits common to the memory address register and the two memory parts for correcting errors in © Inem consisting of m. or m_pacce bits Word that is or has been read from the memory are allied.

Docket UK 968 Q2O 00 983 4/1? 02

200A93A

The advantage of error detection and correction according to the invention in a storage arrangement is that the capacity of a storage arrangement organized like this without further can be increased many times over without a special technical effort or a change in the storage concept is required. The high flexibility of the automatic Error correction system also comes with a very low technical effort compared to the known correction systems for memories and the known compensation circuits achieved for bad bits within a memory word.

The invention will now be based on in FIGS. 1 to 3 shown Embodiments described in more detail.

The data memory shown in FIG. 1 is divided into two memory parts or two memory units 1 and 2. The capacity of the memory unit 1 is 8000 (8k) memory words of 72 bits each and the memory capacity of the Memory unit 2 is 8000 (8k) memory words with 22 bits each.

The memory unit 1 contains 72 memory modules, each of which can store 8k bits. The storage unit 1 is also like this organizes that each memory module has 1 bit of each in the Storage unit 1 contains stored memory word. Each memory word contains 64 data bits and 8 error correction code bits to enable a single error correction. The storage

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Docket UK 968 020 009834/1702 ⁰ ^

hext 2 consists of .22 memory modules, each of which Memory module stores 1 bit of each word. Every word in the Memory unit 2 consists of 16 data bits and 6 error correction code bits.

The two memory units 1 and 2 are addressed in bytes. The addresses of the bytes in each word are contiguous, or in other words, they are contiguous. The · memory address register 3, which is 32 bits in size, stores the address of the byte / which is required at memory output 4. Bits 15 to 28 from memory address register 3 are used to access a memory word of the memory unit 1 and bits 18 to 30 are used to access a memory word of the To get memory part 2 »Bits 16 and 17 are both zero, when the memory unit 2 is addressed. Bits 29, 30 and 31 from memory address register 3 are used to set 1 of 8 bytes to select when the word is fetched from memory unit 1 and bit 31 is used to select one of two bytes ρ if the word of, the. Fetched storage unit 2 shall be. The higher-order bits 0 to 15 in the memory address register 3 select either the storage unit 1 or the storage unit 2. The highest combination of bits 0 to 15 in the Memory address registers select memory unit 2. Most importantly, all of the possible combinations of bits. 0 to 15, which in the present Ai3sleitbeispiel used are for / -uaswahl the Storage units 1 and 2 are required so that the remaining

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Combinations with a desired increase in storage capacity can be used.

The 32 bits of each word that is fetched from the memory part 1 is transferred to the 32-bit register 6 via the input gate element 5 registered. The bits stored in the register 8 are then passed into a downstream error correction circuit 7, the Can detect double errors and can display the positions in register 6 in which there are individual errors. If a single mistake occurs, the error correction circuit 7 shows the position of the individual error in register 6 by generating an error bit display which causes 64 reverse switching at the output. Each of the 64 reverse circuits 8 can be the output signal from one Pass position in the register unchanged to the corresponding gate circuit 9 if there is no error. However, there is a mistake in a position before, then the output signal In the corresponding Position inverted, which corrects the error. The word read out remains in register 6 until another word the entrance gate member 5 happens. The output gate member 9 gives the required byte to the output 4 under control the byte selection bits as previously described. The check bit used for the selected byte is generated by a check generator 10, which is connected to the error correction circuit 7 in a conventional manner. When a 21-bit word comes from memory unit 2 the data bits O to 15 are assigned to positions O to 15 of the

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gisters 6 and the error correction code bits 16 to 21 are given to positions 64 to 69 of register 6. Each of the unused data positions 16 to 63 is set to zero and the _J error correction code positions 70 and 71 of the register 6 are set to Hins by the gates 5 at which there are no input signals. The value to which an unused position in register 6 is set is determined by the error correction code used. The operation then takes place as soon as the word is read out from the memory unit 1, with the exception that only bits 0 to 15 of the register 16 contain meaningful data. , '

When a double error is detected by the error correction circuit 7 an uncorrectable error signal is generated. This Signal can cause access to the appropriate Memory cell is repeated again. To increase the working speed, a byte can be placed on the memory output before the error correction circuit 7 has completed the error detection. When a correctable error is detected, a correctable error signal can be generated which cause know that the corresponding byte is on the memory output is ignored and that the corrected byte that is then added to the Memory output is transferred, · is accepted. · ·

Eight error correlation code bytes can be used for each word contained in the Storage unit 2 is stored, can be used. This requires

Doqket OK 968 020 00 9834/170 2

-lodert two additional modules for the memory unit 2. Fig. 2 shows a data memory similar to that of Fig. 1, with the exception that the memory unit 2 consists of 39 modules, 32 for data storage and 7 for the error correction code bits. The storage capacity of the storage unit 2 is 32k bytes of data. The way of working is the same as previously described in connection with the memory shown in Fig. 1, except that if the word was fetched in register 6 from storage unit 2, register 6 contains four meaningful data bytes. Two byte selection bits 30 and 31 are required to have one of four bytes for transmission to select the exit.

In Fig. 3 a smaller memory unit is shown in which two bits are avoided in the memory units 1 and 2 are stored in the same module. The memory unit 1 contains 36 modules, each of which stores 8k bits in order to be able to store 4k words of 72 bits (64 data and 8 error correction code bits), ie there is a data storage capacity of 32k bytes. The memory unit 2 consists of 20 identical modules to store 4k locations of 40 bits (32 data and 8 error correction codobits). This corresponds to a data byte capacity of 16k. The operation of the memory of FIG. 3 is the same as the operation of the memories shown in FIGS. 1 and 2 are shown to be with the exception that in this example, the Ausyang two bytes in size, and the bits 30 and 31 or the bit 31 are used to provide the required two bytes to the output. One

Docket UK 968 020 009834/1702

- ■ 11 - - "'■

Do.ppelferror correction be made rough when the memory should continue to work with a defective or removed module.

Increased storage capacity can be achieved by adding a additional storage unit or several additional storage units corresponding to the memory unit 1 in the Pign. 1 and 3 can be used. Small increases in memory can be achieved ■ are by a unit such as the storage unit 2, their Capacity is a binary fraction of the capacity of the storage unit i. For example, if the storage unit 1 has a storage capacity of 64k bytes, then the storage unit 2 should have a storage capacity of 8k, 16k or 32k bytes. Bits O to 15 in the memory * - address registers 3 are used to select the partial storage unit.

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Docket UK 968 020 OQ 9 8 3 4/1702

Claims (8)

PATENT CLAIMS 1. Memory arrangement with circuits for error detection and correcting errors in the information stored in the memory by dividing the memory into groups of memory modules which store data or error correction code bits, characterized in that the Memory in a first part (1) for storing words from m data bits and η error correction code bits and a second part (2) for storing words of m_ data bits and η error correction code bits below & 2. divides, where η is greater than m and n .. greater than n2, that a common memory address register (3) is assigned to the two memory parts (1 and 2) and that with the memory address register (3) and the two memory parts (1 and 2) memory correction circuits (6, 7 and 8) are connected to correct errors in a word consisting of m or m data bits, which consists of the Memory is or has been read out. 2. Memory arrangement according to claim 1, characterized in that the memory consists of a plurality of modules, each module having one bit of each word in one which stores parts from memory. Docket UK 968 O2o 0 0 9 8 3 A / 1 7 0 2 3, memory array of claim 1, characterized in t that the memory contains a number of memory modules, each module contains two bits from each of the words in one of the items from store. 4,. _. ' ^: Memory arrangement according to claims 1 to 3 1 thereby characterized in that the circuits for error detection and error correction a register (6) include that m + n -, - bit positions for storing one from memory fetched word includes / that with said register (6) an error correction circuit (7) and a Reversing circuit (8) to display the error position or « is connected to invert the incorrect position or positions. 5. - Storage arrangement according to claim 4, characterized in that that when entering a word with m + η ,, - bit positions from the memory part 2 into the register 6 input gate elements (5) are provided in each unused bit position of the register .6 a predetermined from Error correction code dependent bit * for executing the Error correction entries. 6. Memory arrangement according to claims 1 to 5, characterized characterized in that the memory address register (3) most significant bits to control the supply Docket UK 968 020 009834/1702 used to access a memory word and the lower-digit bits the byte or bytes of the read
Control word that is to be transferred to the output. 7. Memory arrangement according to claims 1 to β, characterized in that the memory contains a number of memory positions in which words of m data bits and η "error correction code bits are stored and in which the value of nu is different in each position. 8. Memory arrangement according to one of claims 1 to 7, characterized characterized in that m_ is a binary fraction of m. Docket UK 968 020 0 0 9 8 3 4/1702